227 results about "Logic implementation" patented technology

A system and method for extending AI-enhanced decision platforms with deontic and normative reasoning capabilities that enhance adjustably autonomous decision-making through a novel integration of symbolic and neural approaches. The invention uses hierarchical and fuzzy deontic logic implementations alongside connectionist AI / ML to manage obligations, permissions, and prohibitions while maintaining observer awareness to achieve goals while incorporating knowledge across multiple expert domains. The system employs dynamic event and spatio-temporal knowledge graphs along with debate mechanisms, enabling high-assurance automated reasoning while preserving explainability through neuro-symbolic integration. In at least one embodiment, the invention operates through a federated distributed computational graph architecture that allows for arbitrary scaling while maintaining coherence, consistency and supporting compound workflows. The invention provides a framework for AI systems to make logically consistent, ethically-aware decisions by combining deontic reasoning with multi-agent coordination, token space communications and knowledge, including on intermediate results, enabling automated decision-making for a variety of applications.

A system and method for extending AI-enhanced decision platforms with deontic and normative reasoning capabilities that enhance adjustably autonomous decision-making through a novel integration of symbolic and neural approaches alongside quantum-inspired token management. The invention uses hierarchical and fuzzy deontic logic implementations and quantum-inspired state representations that combine complex amplitudes and phase information to manage obligations, permissions, and prohibitions while maintaining observer awareness to achieve complex goals while incorporating knowledge across multiple expert domains. The system employs dynamic event and spatio-temporal knowledge graphs along with debate mechanisms, enabling high-assurance automated reasoning while preserving explainability through neuro-symbolic integration and information-theoretic metrics. The platform is capable of operating through a federated distributed computational graph architecture that allows for arbitrary scaling while maintaining system coherence and logical consistency using quantum-inspired token operations and phase alignment transformations for optimizing information transfer between states.

The invention relates to a multi-type industrial equipment PLC control method and device based on a hardware abstraction layer, and the method comprises the steps: constructing the hardware abstraction layer comprising a core layer and an adaptation layer; the core layer is provided with a standardized interface set, the adaptation layer is provided with a special adaptation module, and a control protocol is converted through a protocol analysis engine. And generating a unified instruction set based on the standardized interface set, and establishing a data interaction channel supporting priority scheduling. And identifying the newly-added equipment, matching the equipment configuration library, and generating a newly-added adapter drive if the equipment configuration library fails. And acquiring a device state by using a data interaction channel, and constructing a cooperative control logic to realize linkage. Equipment load and task queues are monitored in real time, and dynamic task scheduling and grading fault processing are carried out. And when an adapter configuration updating instruction is detected, the adaptive layer thermally loads the updated drive, and unified, intelligent, efficient and stable PLC control of multiple types of industrial equipment is realized through cooperation of the core layer and the adaptive layer.

A slidably extendable barrier for placement between two relative positions is provided, including a first sliding partition plate, a second sliding partition plate, a locking assembly, and an adjusting and pressure-applying assembly. The first sliding partition plate and the second sliding partition plate can slide relative to each other along a length direction; the locking assembly is used for optionally locking the first sliding partition plate and the second sliding partition plate along the length direction. The adjusting and pressure-applying assembly enables the slidably extendable barrier to be fixed between the two relative positions. During use, following the logic of “sliding adjustment locking and positioning-pressure-applying fixation”, the core advantages of “flexible adaptation, rapid installation, stability and reliability” are achieved. It is suitable for application scenarios with high requirements on installation convenience, environmental friendliness, and scenario adaptability, integrating functionality and practicability, and enhancing the user experience.

The invention discloses a tensor processing architecture based on reconfigurable calculation, a working mode of the tensor processing architecture and an FPGA (Field Programmable Gate Array) development board. The overall architecture comprises a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, an RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module and a result return network. The working modes of the overall architecture are divided into two modes: a CPU control mode and a cluster computing mode, wherein the CPU control mode is used for controlling global computing and output through a CPU during single-chip computing; the cluster calculation mode is used for being connected with an upper computer to cooperate with the upper computer to execute calculation tasks such as matrix calculation; the whole architecture is realized through an FPGA (Field Programmable Gate Array) development board, and the FPGA development board adopts Virtex UltraScale + VU13P as a main logic realization platform. Through the dynamic granularity configuration of the on-chip microcode, multiple operation modes can be realized, and the utilization rate of hardware is improved; and hardware realizes multiple configuration strategies, and the universality is high.

A test method, system, apparatus and device for an energy storage control system, and a storage medium. The test method comprises: receiving test indication information (S201); on the basis of the test indication information, simulating an associated device connected to a device to be tested in an energy storage control system, and determining simulation-associated parameters (S202); and on the basis of the simulation-associated parameters and the test indication information, testing the device to be tested, and receiving a test result of the device to be tested (S203). A test device (104) can implement the simulation of any device associated with a device to be tested in an energy storage control system. Specifically, interface implementations and function execution logic implementations of any device can be simulated, and the simulated interface implementations or function implementations are implemented by means of simulation-associated parameters. Therefore, the test process is not limited to testing a specific type of device to be tested, and multiple types of tests can be implemented, thereby improving the applicability of the test method to a certain extent.

The invention discloses a data security communication system of the Internet of Things, which relates to the technical field of data security communication of the Internet of Things, and comprises the steps of equipment identity authentication, adoption of a Hash encryption and challenge response mechanism, dynamic key negotiation and combination with a Diffie-Hellman algorithm and an equipment operation state to generate a session key; the data encryption transmission uses AES-256 encryption and is transmitted through a TLS1.3 protocol, and abnormal traffic detection and prediction are carried out through DBSCAN clustering and an LSTM model; the data integrity is ensured through double verification of the receiving end; flexible access authority control is realized based on attributes in combination with fuzzy logic; recording an operation log and intelligently analyzing to complete safety audit; secret key updating is triggered according to a period or threat, and a new secret key is protected by a digital signature. According to the method, illegal access is prevented through multiple authentication, confidentiality is enhanced through a dynamic key, threats are intelligently detected, authority is flexibly controlled, logs are effectively audited, the key is updated in time, vulnerabilities are repaired, data leakage and attack loss are reduced, and a safety barrier is built for application of the Internet of Things.

The invention provides a configurable processing method, system and device for multi-form process event linkage and a medium, and belongs to the technical field of low-code development platforms. A basic database containing associated fields is constructed, a process database is constructed, and a data mapping relation is established between the process database and the basic database through the associated fields; according to the current node identifier of the process database and the service state of the basic database, determining a relationship between nodes; cross-form data query or editing is realized by binding the process model and the associated field; configuring an operable button according to the business rule and the operation authority; the method comprises the following steps: configuring a custom script, creating a process model, configuring a process event, defining a process approval node and a process rule, ensuring process jump after state change, and forming end-to-end state synchronization. According to the invention, the business logic realization process can be simplified, and all related business rules and verifications can be ensured to be executed at correct opportunities, so that the business processing efficiency is effectively improved.

The invention relates to the technical field of computer system structures, in particular to a unified memory and data transmission system and management method for an FPGA heterogeneous platform, and the system comprises a CPU component which is used for detecting and initializing an FPGA component, constructing a globally unified virtual address space view, managing a global page table, maintaining a mapping table, managing PCIe communication and processing exceptions; the FPGA component is used for PCIe DMA data transmission, conversion from a virtual address to a physical address, striped on-chip storage and storage of user acceleration function logic implementation; and the PCIe bus is used for data transmission of the CPU component and the FPGA component. Physical memory resources of the CPU component and the FPGA component are integrated and dynamically mapped to a unified virtual address space in a software and hardware cooperation mode, a simple, safe and flexible unified memory system and management method are provided, and efficient memory management and data transmission between the CPU and the FPGA are achieved.

The invention discloses a transformer substation anti-error logic verification method, system and device and a storage medium. The method comprises the following steps: configuring secondary locking primary logic for primary equipment; only secondary locking secondary logic needs to be configured for the protection pressing plate, and primary locking secondary logic does not need to be configured; when the primary equipment is operated, secondary locking primary logic is verified; when the protection pressing plate is operated, the secondary locking secondary logic is verified, and meanwhile, the secondary locking primary logic is verified based on the expected state of the simulation pressing plate, so that primary locking secondary verification is achieved. According to the method, the problem that secondary anti-error configuration of an existing transformer substation is complex can be solved, the engineering configuration efficiency is greatly improved, the logic rule acceptance time is shortened, the configuration error risk caused by human errors is reduced, the system reliability is remarkably improved, and the practical level of secondary anti-error configuration of the transformer substation is improved.

The invention discloses a substrate management controller firmware integrity verification method and electronic equipment, and relates to the technical field of server management, and the method comprises the steps: building a tree structure layered according to a storage path prefix through obtaining the storage path and content data of each function module, the full-coverage verification of all functional modules of the firmware of the baseboard management controller is realized; according to the method, the security level labels in the structured description information are screened, and the verification path is determined for the target function module, so that the redundant operation of full firmware mirror image hash calculation is avoided, and the calculation amount and time consumption in the verification process are reduced; hash is recalculated based on the target function module and path consistency is verified, whether the target function module is tampered or not can be rapidly judged, all firmware data does not need to be traversed, verification comprehensiveness and efficiency are both considered, and bandwidth resource consumption is reduced; all function modules are associated through a storage path and content data, tree structure verification logic is combined, and refinement of firmware verification from a full mirror image level to a function module level is achieved.

The invention provides an SOA-based application layer software architecture construction method and device. The method comprises the following steps: establishing a communication connection between an underlying protocol stack and an external Ethernet; establishing a connection between the underlying protocol stack and a software component in the SOA service processing module; creating a first executable entity in the software component, and creating a second executable entity in the application layer logic implementation module; establishing communication connection between the software component and the application layer logic implementation module; the functional logic is built based on the logic development tool, the first executable entity and the second executable entity. In the scheme, compared with the prior art, the SOA service processing module is added to realize the layering of a bottom layer and an application layer, so that the whole architecture is clearer, debugging information can be added in each layer when a problem occurs, which part has the problem can be positioned, and when software platform reuse is carried out, the debugging efficiency is greatly improved. And only a receiving interface at the SOA service processing module needs to be modified, so that modularized software reuse can be realized.

The invention discloses a clock synchronization method and system based on an FPGA, and the method comprises the steps: obtaining the frequency of a synchronization signal and the period of a local clock signal, carrying out the first frequency division processing of the local clock signal through the first internal logic of the FPGA, and obtaining a first clock signal; calculating a phase difference and a frequency difference between the first clock signal and the synchronizing signal through a second internal logic of the FPGA; and according to the frequency difference and the phase difference, synchronous locking of the local clock signal and the synchronous signal is realized through the first internal logic and the second internal logic of the FPGA, and the synchronized clock signal is output, so that the cost of clock synchronization is reduced. Wherein the clock synchronization is realized by only depending on FPGA soft logic in a pure digital mode, and does not depend on an additional analog circuit.

The invention discloses a header field intelligent benchmarking method and system based on semantic index segmentation, relates to the technical field of data management, and aims to solve the problems that in the prior art, header field standardization depends on manpower, efficiency is low, and semantic fuzzy and non-Chinese fields are difficult to process. An intelligent benchmarking scheme fusing semantic comprehension and vector matching is provided. According to the method, header fields are decomposed through a large language model to generate an initial word bank, and a historical benchmarking database is constructed to realize rapid matching; semantic segmentation is carried out by adopting a fine tuning BERT model, and precise benchmarking is completed in combination with vector library retrieval and Top-K recommendation; code set recognition is achieved by applying regular rules and semantic logic for non-Chinese fields. The system comprises a lexicon construction module, a history matching module, a semantic segmentation module, a vector matching module and the like. The device comprises hardware units such as a processor and a memory. According to the invention, automatic standardized processing of header fields is realized, and the data governance efficiency is improved.

The invention discloses an interface testing method and device and a storage medium. The method comprises the steps that whether output data of a to-be-tested interface meets expected requirements or not can be automatically verified through an intelligent agent so as to determine whether the function of the to-be-tested interface is normal or not, response data simulating user behaviors are generated based on a preset knowledge base, interaction logic of the interface is further verified, the automatic testing process is achieved, and the testing efficiency is improved. The time for manually compiling and executing the test case can be shortened, the workload of testers is reduced, and the test efficiency of interface testing is improved. Moreover, the response data of the previous test task and the input parameters of the current test task are combined, so that the continuity of actual user operation can be simulated, the authenticity of a test scene is improved, the test is closer to the actual use condition, and the accuracy of a test result is further improved.

The invention discloses a front-end code generation method and device and a storage medium, and relates to the technical field of front-end development. According to the method, by obtaining the pre-configuration data of the to-be-executed project, the project demand can be accurately grasped. According to the method, the attribute information is analyzed, complex project requirements are refined into specific dimension configuration data, then the data are matched with the front-end configuration resource pools of the multiple dimensions, the target codes are rapidly generated, the code obtaining time is greatly shortened, and the tedious work that developers blindly search and write a large number of codes is avoided. Finally, the target front-end codes are generated through combination according to the preset format, repeated development is effectively avoided, developers do not need to write basic codes, more energy can be concentrated on core business logic implementation, the technical problems that in the front-end development process, code writing efficiency is low, errors are prone to occurring, and resource reusability is poor are solved, and the development efficiency is improved. The technical effects of improving the front-end development efficiency, improving the code quality and enhancing the code reusability are achieved.

The embodiment of the invention provides an equipment control method and device, electronic equipment and a storage medium, and relates to the technical field of equipment control, and the method comprises the steps: responding to the power-on of central control equipment, and loading a configuration file corresponding to a target application program, the configuration file comprising a configuration table corresponding to smart home equipment; obtaining a file path corresponding to the configuration table, and converting the file path into a path code; obtaining a first path code of the first smart home equipment in response to the equipment state change of the first smart home equipment or an equipment control instruction for the first smart home equipment; the first configuration table of the first smart home device is read according to the first path code, and the corresponding first control interface is rendered according to the first configuration table and the device state change or the device control instruction to control the first smart home device, so that the software logic implementation flexibility is improved, the code repetition rate is reduced, and the user experience is improved. And the control efficiency of the smart home equipment is improved.

The invention is suitable for the technical field of LED backlight driving, and provides a starting time sequence control circuit and a control chip. The starting time sequence control circuit comprises a switching module, a comparison module, a threshold adjusting module and a switch module, the comparison module is electrically connected with the switching module, the threshold adjusting module and the switch module, the switching module is electrically connected with the detection selection module and the error amplification module, and the comparison module is electrically connected with the feedback module. The threshold adjusting module is electrically connected with the logic driving module, and the switch module is electrically connected with the logic driving module and the control module. According to the starting time sequence control circuit provided by the embodiment of the invention, the error amplification module is configured as the unity gain buffer in the starting stage, and the error amplification module and the control module are connected to the closed loop when the output voltage is close to the target value; and the over-current protection threshold value is gradually increased through the threshold value adjusting module so as to relax the staged cooperative control logic of the current limitation, so that the stable rise of the output voltage is realized.

The invention relates to a test method, a test system, a device and equipment for an energy storage control system and a storage medium. The method comprises the following steps: receiving test indication information, simulating associated equipment connected with equipment to be tested in the energy storage control system according to the test indication information, and determining simulation associated parameters; and testing the to-be-tested equipment according to the simulation correlation parameters and the test indication information, and receiving a test result of the to-be-tested equipment. In the test method, the test device can simulate any device associated with the device to be tested in the energy storage control system, specifically, the test device can simulate interface implementation and function execution logic implementation of any device, and the simulated interface implementation or function implementation is realized by simulating the associated parameters. Therefore, the test process is not limited to test the to-be-tested equipment of a specific type, various types of tests can be realized, and the applicability of the test method is improved to a certain extent.

The invention discloses a double-node interaction system architecture design method, device and equipment and a medium, and relates to the field of integrated circuits, and the method comprises the steps: configuring corresponding communication bus modules for a first node and a second node in double nodes; the communication bus module comprises a universal serial bus function realized based on integrated logic; the communication bus modules for controlling the double nodes are connected with respective video graphic array modules, management component transport protocol modules, data access interaction modules and universal extension control interfaces, and the respective video graphic array modules for controlling the double nodes are connected with respective image coding and decoding modules; the bandwidth of the communication bus module is calculated according to the bus characteristics of the communication bus module, and the bandwidth of the storage space is calculated according to the storage characteristics of the storage space, so that the bandwidth requirement of the double nodes is met. The problem of high cost of the multi-node server is effectively solved, the utilization rate of the substrate management controller is greatly improved, and simultaneous online control management of the host of the multi-node server is realized.

The invention relates to a system and method for achieving PCIe bus synchronous serial port expansion and CAN interface conversion, the system comprises an external connector, an FPGA, an RS422 serial port transceiver and a CAN interface chip, PCIe bus protocol analysis logic, asynchronous serial port IP core logic and CAN interface chip control logic are constructed according to the connection relation of the PCIe bus synchronous serial port expansion and CAN interface conversion system, and the external connector is connected with the external connector. And the PCIe bus synchronous expansion serial port and CAN interface conversion is realized. According to the invention, the asynchronous serial port receiving and transmitting function is realized through the asynchronous serial port IP core; and meanwhile, a CAN interface communication function is realized through CAN interface chip control logic, and finally, two kinds of signals with different time sequences, namely asynchronous serial port IP core control signals and CAN interface chip control signals, are synchronously accessed into PCIe bus protocol analysis transceiving logic, so that the function of synchronously expanding the serial port and the CAN interface by the PCIe bus is realized.

The present invention discloses a SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture, which relates to the field of system-level chip testing, and implements the access of the PHY to be tested based on a preset access logic, wherein the preset access logic specifically includes: connecting the test interfaces of multiple PHYs of the same type in parallel through a JTAG_HUB module, and accessing the JTAG Chain via the JTAG_HUB module; based on the type of PHY, if the number of the current type of PHY is only one, directly accessing the JTAG Chain when it is a JTAG test interface, and accessing the JTAG Chain via a TAP_FSM module when it is a TDR test interface; inserting a JTAG_PIPE module based on the distance between access nodes in the JTAG Chain. The present application can effectively solve the problem of PHY test duration.

The embodiments of the present application belong to the technical field of link stress testing. Provided are a link stress testing method and system based on a micro-service architecture, and a device and a storage medium. In the present solution, by means of adding a coloring token to stress testing traffic and performing performance monitoring on a link under test on the basis of a distributed system tracing tool, a problematic node in the link under test can be quickly positioned during stress testing on the basis of the coloring token and collected performance data; and message passing logic and storage logic of application services in an actual production environment for stress testing data are modified efficiently and non-invasively on the basis of a dependency management tool, isolating the stress testing data from authentic data, such that a stress testing result is more authentic and reliable.

The invention relates to a security flash memory module verification method and system based on a parameterized reference model, and aims to realize one-time writing and multi-position calling through packaging encryption judgment and data comparison logic, greatly reduce the duplicate code quantity of a test case, and reduce duplicate labor by using a uniform interface. By means of a parameter randomization mechanism in a construction script, automatic and multi-parameter combined verification of the secure flash memory module is realized, and the verification coverage rate is improved by parameterized automatic execution. AES key carrying is used as base class function packaging, case writing is simplified, process consistency is kept, key carrying process modularization is achieved, and maintenance cost is reduced. Various verification processes are executed under a unified framework, manual intervention is reduced, the human error probability is reduced, verification efficiency and stability are improved, meanwhile, stability and expandability of a simulation environment are improved, and the method can adapt to design and verification requirements of various security flash memory modules.

The invention discloses a relay protection cooperation relation evaluation method and system for intermittent faults, and the method comprises the steps: constructing a multi-scene intermittent fault current model library, applying current with the amplitude and duration dynamically changing to an upper-stage relay protection device and a lower-stage relay protection device, so as to simulate a single-time intermittent fault, a multiple intermittent fault and a high-resistance intermittent fault, the minimum return intervals T21 and T22 of the upper-level overcurrent protection and the lower-level overcurrent protection are obtained in combination with environment correction; the T21 and the T22 are integrated, and the maloperation risk of the upper-stage relay protection cooperation relation and the lower-stage relay protection cooperation relation is evaluated; if the maloperation risk exists, upper and lower level overcurrent protection constant value parameters are adaptively adjusted, and the upper and lower level relay protection cooperation relation is optimized. By simulating the occurrence process of the intermittent fault in a real power grid, whether each protection device can meet the requirements of selectivity, quickness and reliability according to set logic or not is tested, and the coordination and response capability of the relay protection device under the intermittent fault can be systematically verified and evaluated in a standardized mode.

The invention discloses a dynamic reasoning method and system for industrial design multi-modal constraint verification. The method comprises the steps that an input geometric image and a problem text are converted into formalized language description of the same symbology system through an analyzer; inputting the formalized language description into a symbol solver, and solving the symbolized representation of the geometric problem by introducing a named relationship and a state machine; under the condition that input questions are given, similar questions with question solving theorem guidance are found out, and contents and thinking directions of the similar questions serve as a part of cue words Prompt to participate in construction of the thinking tree; a geometric reasoning normal form of a tree-shaped structure is adopted according to the thinking tree, proposal and evaluation are conducted in combination with a large language model, whether a stopping condition is met or not and whether searching is continued or not are judged through a controller, and the optimal problem solving path and the problem solving process are determined. The method can fully stimulate the capability of a large model in the field of plane geometry problems, effectively fuses geometric information and text logic, and achieves a good question and answer effect.

A circuit and corresponding method perform timestamp filtering. The circuit includes recursive filter logic that implements a recursive least-squares (RLS) filter. The circuit (i) generates a filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic applies the RLS filter to a portion of the received timestamp. A number of bits of the portion is less relative to a total number of bits of the received timestamp. The circuit outputs the filtered timestamp generated. Applying the RLS filter to the portion enables the circuit to be more efficient (e.g., smaller adders, fewer flipflops, etc.), thereby reducing area and power consumption of the circuit.

The application belongs to the technical field of integrated circuits, and particularly relates to a UART decimal correction circuit and a correction method. The UART decimal correction circuit comprises a frequency division coefficient preloading circuit, an integer frequency division up counter, a decimal correction down counter, and a decimal correction algorithm circuit. The decimal correction algorithm circuit is used for inputting a count value cnt_i[9:0] and a count value cnt_f[3:0], determining a decimal correction sampling point through a shift, negation and comparison mode, and outputting a pulse signal reload to the integer frequency division up counter, the decimal correction down counter and a D flip-flop. When the pulse signal reload is valid, it is determined whether the integer frequency division up counter needs to be added by 1 and whether the decimal correction down counter needs to be subtracted by 1. The D flip-flop is used. The application determines the decimal correction sampling point through the shift, negation and comparison algorithm, so that a more accurate baud rate is realized with less logic.

The invention discloses a pipeline dynamic control method, system and device based on external system interaction and a medium, and the method comprises the steps: in a pipeline execution process, setting a calling node at a specific stage or a plug-in execution link, and interacting with an external system through REST API, a message queue, database query and other modes to obtain data; analyzing the returned data and assigning the data to pipeline variables, wherein the variables are divided into a global type and a local type; and according to variable setting condition judgment logic, realizing dynamic control on whether the plug-in is executed or not and plug-in parameters in the assembly line stage. According to the method, the problems of static configuration, poor flexibility, weak response capability, high manual intervention cost, low service adaptability and the like of the existing assembly line execution process are effectively solved. Through real-time interaction with an external system and dynamic control based on data, the assembly line can adjust the execution process according to real-time business data, the assembly line arrangement efficiency and the task execution reliability are remarkably improved, and the research, development, operation and maintenance cost of an enterprise is reduced.

The present application relates to the technical field of product warehouse dynamic cleaning, and particularly relates to a product warehouse customized dynamic cleaning implementation method and system.The implementation method comprises the following steps: a business layer is responsible for scene logic implementation, and has a system type, an environment and a time range set by a user;S2: setting a cleaning rule, adopting a time priority scheduling algorithm, arranging a cleaning task execution order according to a task execution priority and a current product warehouse load state;S3: an execution layer is responsible for screening out products needing to be cleaned in a logic layer, and performing product cleaning by calling a system level command.The present application realizes accurate product warehouse cleaning, maximizes storage space release, reduces operation and maintenance costs, and improves product warehouse storage efficiency and service stability on the premise of guaranteeing core product safety.