148 results about "Logic implementation" patented technology

A slidably extendable barrier for placement between two relative positions is provided, including a first sliding partition plate, a second sliding partition plate, a locking assembly, and an adjusting and pressure-applying assembly. The first sliding partition plate and the second sliding partition plate can slide relative to each other along a length direction; the locking assembly is used for optionally locking the first sliding partition plate and the second sliding partition plate along the length direction. The adjusting and pressure-applying assembly enables the slidably extendable barrier to be fixed between the two relative positions. During use, following the logic of “sliding adjustment locking and positioning-pressure-applying fixation”, the core advantages of “flexible adaptation, rapid installation, stability and reliability” are achieved. It is suitable for application scenarios with high requirements on installation convenience, environmental friendliness, and scenario adaptability, integrating functionality and practicability, and enhancing the user experience.

The invention provides a configurable processing method, system and device for multi-form process event linkage and a medium, and belongs to the technical field of low-code development platforms. A basic database containing associated fields is constructed, a process database is constructed, and a data mapping relation is established between the process database and the basic database through the associated fields; according to the current node identifier of the process database and the service state of the basic database, determining a relationship between nodes; cross-form data query or editing is realized by binding the process model and the associated field; configuring an operable button according to the business rule and the operation authority; the method comprises the following steps: configuring a custom script, creating a process model, configuring a process event, defining a process approval node and a process rule, ensuring process jump after state change, and forming end-to-end state synchronization. According to the invention, the business logic realization process can be simplified, and all related business rules and verifications can be ensured to be executed at correct opportunities, so that the business processing efficiency is effectively improved.

The invention relates to the technical field of computer system structures, in particular to a unified memory and data transmission system and management method for an FPGA heterogeneous platform, and the system comprises a CPU component which is used for detecting and initializing an FPGA component, constructing a globally unified virtual address space view, managing a global page table, maintaining a mapping table, managing PCIe communication and processing exceptions; the FPGA component is used for PCIe DMA data transmission, conversion from a virtual address to a physical address, striped on-chip storage and storage of user acceleration function logic implementation; and the PCIe bus is used for data transmission of the CPU component and the FPGA component. Physical memory resources of the CPU component and the FPGA component are integrated and dynamically mapped to a unified virtual address space in a software and hardware cooperation mode, a simple, safe and flexible unified memory system and management method are provided, and efficient memory management and data transmission between the CPU and the FPGA are achieved.

The invention discloses a transformer substation anti-error logic verification method, system and device and a storage medium. The method comprises the following steps: configuring secondary locking primary logic for primary equipment; only secondary locking secondary logic needs to be configured for the protection pressing plate, and primary locking secondary logic does not need to be configured; when the primary equipment is operated, secondary locking primary logic is verified; when the protection pressing plate is operated, the secondary locking secondary logic is verified, and meanwhile, the secondary locking primary logic is verified based on the expected state of the simulation pressing plate, so that primary locking secondary verification is achieved. According to the method, the problem that secondary anti-error configuration of an existing transformer substation is complex can be solved, the engineering configuration efficiency is greatly improved, the logic rule acceptance time is shortened, the configuration error risk caused by human errors is reduced, the system reliability is remarkably improved, and the practical level of secondary anti-error configuration of the transformer substation is improved.

The invention discloses a substrate management controller firmware integrity verification method and electronic equipment, and relates to the technical field of server management, and the method comprises the steps: building a tree structure layered according to a storage path prefix through obtaining the storage path and content data of each function module, the full-coverage verification of all functional modules of the firmware of the baseboard management controller is realized; according to the method, the security level labels in the structured description information are screened, and the verification path is determined for the target function module, so that the redundant operation of full firmware mirror image hash calculation is avoided, and the calculation amount and time consumption in the verification process are reduced; hash is recalculated based on the target function module and path consistency is verified, whether the target function module is tampered or not can be rapidly judged, all firmware data does not need to be traversed, verification comprehensiveness and efficiency are both considered, and bandwidth resource consumption is reduced; all function modules are associated through a storage path and content data, tree structure verification logic is combined, and refinement of firmware verification from a full mirror image level to a function module level is achieved.

The invention discloses a header field intelligent benchmarking method and system based on semantic index segmentation, relates to the technical field of data management, and aims to solve the problems that in the prior art, header field standardization depends on manpower, efficiency is low, and semantic fuzzy and non-Chinese fields are difficult to process. An intelligent benchmarking scheme fusing semantic comprehension and vector matching is provided. According to the method, header fields are decomposed through a large language model to generate an initial word bank, and a historical benchmarking database is constructed to realize rapid matching; semantic segmentation is carried out by adopting a fine tuning BERT model, and precise benchmarking is completed in combination with vector library retrieval and Top-K recommendation; code set recognition is achieved by applying regular rules and semantic logic for non-Chinese fields. The system comprises a lexicon construction module, a history matching module, a semantic segmentation module, a vector matching module and the like. The device comprises hardware units such as a processor and a memory. According to the invention, automatic standardized processing of header fields is realized, and the data governance efficiency is improved.

The invention is suitable for the technical field of LED backlight driving, and provides a starting time sequence control circuit and a control chip. The starting time sequence control circuit comprises a switching module, a comparison module, a threshold adjusting module and a switch module, the comparison module is electrically connected with the switching module, the threshold adjusting module and the switch module, the switching module is electrically connected with the detection selection module and the error amplification module, and the comparison module is electrically connected with the feedback module. The threshold adjusting module is electrically connected with the logic driving module, and the switch module is electrically connected with the logic driving module and the control module. According to the starting time sequence control circuit provided by the embodiment of the invention, the error amplification module is configured as the unity gain buffer in the starting stage, and the error amplification module and the control module are connected to the closed loop when the output voltage is close to the target value; and the over-current protection threshold value is gradually increased through the threshold value adjusting module so as to relax the staged cooperative control logic of the current limitation, so that the stable rise of the output voltage is realized.

The invention relates to a security flash memory module verification method and system based on a parameterized reference model, and aims to realize one-time writing and multi-position calling through packaging encryption judgment and data comparison logic, greatly reduce the duplicate code quantity of a test case, and reduce duplicate labor by using a uniform interface. By means of a parameter randomization mechanism in a construction script, automatic and multi-parameter combined verification of the secure flash memory module is realized, and the verification coverage rate is improved by parameterized automatic execution. AES key carrying is used as base class function packaging, case writing is simplified, process consistency is kept, key carrying process modularization is achieved, and maintenance cost is reduced. Various verification processes are executed under a unified framework, manual intervention is reduced, the human error probability is reduced, verification efficiency and stability are improved, meanwhile, stability and expandability of a simulation environment are improved, and the method can adapt to design and verification requirements of various security flash memory modules.

The invention discloses a dynamic reasoning method and system for industrial design multi-modal constraint verification. The method comprises the steps that an input geometric image and a problem text are converted into formalized language description of the same symbology system through an analyzer; inputting the formalized language description into a symbol solver, and solving the symbolized representation of the geometric problem by introducing a named relationship and a state machine; under the condition that input questions are given, similar questions with question solving theorem guidance are found out, and contents and thinking directions of the similar questions serve as a part of cue words Prompt to participate in construction of the thinking tree; a geometric reasoning normal form of a tree-shaped structure is adopted according to the thinking tree, proposal and evaluation are conducted in combination with a large language model, whether a stopping condition is met or not and whether searching is continued or not are judged through a controller, and the optimal problem solving path and the problem solving process are determined. The method can fully stimulate the capability of a large model in the field of plane geometry problems, effectively fuses geometric information and text logic, and achieves a good question and answer effect.

The application belongs to the technical field of integrated circuits, and particularly relates to a UART decimal correction circuit and a correction method. The UART decimal correction circuit comprises a frequency division coefficient preloading circuit, an integer frequency division up counter, a decimal correction down counter, and a decimal correction algorithm circuit. The decimal correction algorithm circuit is used for inputting a count value cnt_i[9:0] and a count value cnt_f[3:0], determining a decimal correction sampling point through a shift, negation and comparison mode, and outputting a pulse signal reload to the integer frequency division up counter, the decimal correction down counter and a D flip-flop. When the pulse signal reload is valid, it is determined whether the integer frequency division up counter needs to be added by 1 and whether the decimal correction down counter needs to be subtracted by 1. The D flip-flop is used. The application determines the decimal correction sampling point through the shift, negation and comparison algorithm, so that a more accurate baud rate is realized with less logic.

The present application relates to the technical field of product warehouse dynamic cleaning, and particularly relates to a product warehouse customized dynamic cleaning implementation method and system.The implementation method comprises the following steps: a business layer is responsible for scene logic implementation, and has a system type, an environment and a time range set by a user;S2: setting a cleaning rule, adopting a time priority scheduling algorithm, arranging a cleaning task execution order according to a task execution priority and a current product warehouse load state;S3: an execution layer is responsible for screening out products needing to be cleaned in a logic layer, and performing product cleaning by calling a system level command.The present application realizes accurate product warehouse cleaning, maximizes storage space release, reduces operation and maintenance costs, and improves product warehouse storage efficiency and service stability on the premise of guaranteeing core product safety.

The invention discloses a digital management system based on a multi-tenant architecture, and belongs to the technical field of multi-tenant atomic capability platforms, the system comprises an application layer, a business layer, an acquisition layer and a terminal layer, the application layer performs data interaction with the business layer and an external system capability service through a service gateway and a service registration configuration center; the business layer comprises a resource management module, a comprehensive monitoring module, an intelligent operation and maintenance module and a system management module, and adapts and converts atomic service capability interfaces of various transmission protocols through interface adaptation services to obtain atomic capability services provided by application services; and the data storage module is used for realizing multi-tenant database sharing based on the shared database and the independent schema, and realizing logic isolation of the independent schema through code logic. The digital multi-tenant atomic power open system is formed, the hardware cost and the maintenance cost can be greatly reduced, and the resource utilization efficiency is improved.

The invention relates to the field of automatic machining, and discloses an automatic taking and installing system for CNC and a control method of the automatic taking and installing system. The system comprises a material taking module, a processing platform, a raw material bin, a clinker bin and a processing positioning jig. The material taking module is installed on the outer side of the CNC rack, is composed of a large lifting air cylinder, a right pushing air cylinder, a rear pushing air cylinder and a hardware fitting suction cup which are perpendicular to one another and is used for driving products to move. The raw material bin and the clinker bin are driven by an air cylinder to achieve lifting adjustment. Based on a CNC control system, all assemblies are driven to execute material taking, secondary positioning, machining and discharging actions by directly reading and responding to code instructions output by CNC. The system does not need additional external programming control, is compact in structure, can realize automatic cycle operation by using the existing CNC code logic, reduces the equipment transformation cost and the operation difficulty, also reduces the learning burden and the training cost of operators, and is convenient to quickly popularize and apply in the existing production line.

This invention discloses a firmware burning mode triggering method, an intelligent fusion terminal, and a system for embedded devices. The firmware burning mode triggering method for embedded devices is applied to an embedded device including a main control unit and at least one function key. The method includes: after the main control unit is powered on, running a bootloader; during the execution of the bootloader, monitoring the level state of a specific function key designated as a mode trigger key; when the duration of continuous pressing of the mode trigger key reaches a first preset threshold T1, determining that the user intends to enter the firmware burning mode; and responding to the determination, controlling the embedded device to enter a state of waiting to receive firmware burning data. This invention can achieve an effective firmware burning mode triggering mechanism to prevent accidental operation by reusing existing function keys and optimizing the logic of the bootloader without adding dedicated hardware.

An optical logic device and a logic implementation method therefor. The optical logic device comprises: a first straight waveguide (20), a second straight waveguide (21), two ring waveguides (3), two phase change functional units (4), four electrodes (5) and an optical detection device. The two ring waveguides (3) are spaced between the first straight waveguide (20) and the second straight waveguide (21); the two phase change functional units (4) respectively cover upper surfaces of the two ring waveguides (3); and two ends of each phase change functional unit (4) are each connected to one electrode (5). The first straight waveguide (20) comprises a first input end (a) and a first output end (b), and the second straight waveguide (21) comprises a second output end (c), wherein the first output end (b) and the first input end (a) are arranged on different sides, the second output end (c) and the first input end (a) are arranged on the same side, the first input end (a) is used for inputting an optical signal, the optical signal is a signal that does not change the state of the phase change functional unit (4), and the state of the phase change functional unit (4) comprises a crystalline state and an amorphous state. Each ring waveguide (3) comprises a second input end, wherein the second input end is composed of electrodes (5) at two ends of a phase change functional unit (4), the ring waveguide (3) is used for coupling an optical signal in the first straight waveguide (20) to the ring waveguide (3) and coupling an optical signal in the ring waveguide (3) to the second straight waveguide (21), the second input end is used for inputting an electrical signal, and the electrical signal is a signal that can change the state of the phase change functional unit (4). The optical detection device is connected to both the first output end (b) and the second output end (c), and is used for monitoring the transmittance of the optical signal outputted by the first output end (b) and the second output end (c) when the phase change functional unit (4) is in different states. The optical logic device has the characteristics of a compact structure, simple operation and a large on-off ratio, thereby improving the computational speed and capability of optical logic operations.

The invention discloses an unmanned underwater vehicle data processing and memory management method and system combined with a multi-language fusion technology. The method comprises the following steps: receiving and analyzing a user instruction based on a main control end, and determining algorithm calling logic; a compilation type numerical calculation module (such as Matlab DLL) is called through a first algorithm integration interface, and multi-source parameter fusion and correction are executed; calling an interpreted script algorithm module (such as a Python process) through a second algorithm integration interface, and executing artificial intelligence and deep learning quality control; and the cross-language memory management module is used for performing unified management and control on memory interaction of the hosting codes and the non-hosting codes. And the memory management module realizes active recovery of the memory by maintaining a running state class and a queue to be released on the basis of logic of coupling of a service time sequence and a function code. The method solves the problems of memory overflow and system robustness in a multi-language integrated environment, guarantees the high efficiency and reliability of massive observation data processing, and is suitable for the field of unmanned underwater vehicle detection.

The invention discloses a silicon controlled rectifier forward and reverse bidirectional switching solid-state module, and aims to solve the problems that an existing silicon controlled rectifier switching scheme is high in short circuit risk, high in cost and complexity and difficult to maintain, and a simple relay replacement scheme is short in service life. According to the technical scheme, the device comprises a hardware circuit structure and a single-chip microcomputer control logic part, the hardware circuit structure comprises a main loop silicon controlled rectifier unit, a relay switching unit, a single-chip microcomputer control unit, a signal acquisition unit and a power supply unit, and a mixed topological structure of three main loop silicon controlled rectifiers and a common double-pole double-throw relay is adopted. And in cooperation with closed-loop control logic of load state judgment, silicon controlled rectifier turn-off, relay switching and silicon controlled rectifier conduction, current forward and reverse safe switching is realized. Two silicon controlled rectifiers for switching are omitted, so that the risk of short circuit is thoroughly avoided; the relay is switched only when the silicon controlled rectifier has no output, so that the service life is prolonged; the circuit structure is simplified, the hardware and maintenance cost is reduced, and the anti-interference capability is remarkably improved.

The invention relates to the technical field of digital clock signal processing, in particular to a clock frequency detection system and method based on clock edge alignment detection, and the system comprises a working state monitoring module, a sampling period counting module, a clock sampling module, a state judgment and change module, and an index generation and output module. A signal of the system in a normal working state is released through the working state monitoring module, a high-frequency clock signal is input to the working state monitoring module, and the system controls a sampling period through a low-frequency clock, periodically samples the high-frequency clock, counts the number of high levels in the sampling period and judges the state change of the high-frequency clock. And judging that the rising edge of the low-frequency clock is aligned with the rising edge of the high-frequency clock, and outputting a corresponding phase index value. The device is realized by adopting pure digital logic, has anti-jitter capability, can accurately identify the phase of the high-frequency clock, and has the advantages of simple structure, high precision and strong transportability.

The invention discloses a component calling method and device, equipment, a medium and a product, and the method comprises the steps: analyzing a target component file, and obtaining function feature information of a callable function; constructing an RAG knowledge base; retrieving the RAG knowledge base to obtain semantic information matched with the function feature information; and on the basis of the semantic information and a preset large model, generating executable calling logic, so as to realize calling of the target component in the target component file on the basis of the executable calling logic. Static analysis and dynamic semantic enhancement are combined, semantic understanding and calling packaging of the function interface can be automatically completed, compiling and linkable calling codes are directly output, and the integration efficiency is remarkably improved.

The embodiment of the invention discloses a method and a device for generating various modal contents based on a knowledge base and an index, electronic equipment and a computer readable storage medium, and realizes'knowledge priori constraint 'of a generation process based on dual drive of the knowledge base and a vector index; introducing a cyclic screening and dynamic threshold control mechanism, and constructing a convergent optimization closed loop; multi-modal complementation and consistency verification logic is provided, and integrated generation of cross-modal content is achieved; through a shunting-scheduling-fusion mechanism, the problems of scheduling efficiency and consistency in a multi-model collaboration process are innovatively solved; an end-to-end closed loop is established, knowledge retrieval and content generation are truly connected, and a knowledge base is evolved into a dynamic driving engine from a static information source. According to the technical scheme provided by the invention, through hierarchical design and module decoupling, the expandability of the system is ensured, and the professionality and practicability of the generated content are also improved.

The invention relates to the technical field of networks, in particular to a network data packet analysis system, and provides a system for network data packet analysis, which comprises a protocol decoding engine, a graph optimization engine and a graph traversal engine, in a protocol decoding engine, a plain text concise language specification is adopted to describe basic logic and logic combination of formal languages, description of logic combination and complex nested structures is supported, high expression ability and good readability are achieved, the design is concise enough, the manufacturing difficulty of decoding scripts and the total number of codes can be greatly reduced, and the decoding efficiency is improved. In the graph optimization engine and the graph traversal engine, grammar logic of an original graph structure processed by the protocol decoding engine is converted into graph logic by adopting a graph algorithm to realize performance optimization during operation, and flexible analysis of different types of protocols is supported for a multi-graph engine architecture; and a graph structure designed in a classified manner comprises a character string graph, a regular graph and the like, and a standardized graph traversal mechanism is realized by unifying a multi-graph traversal engine.

The application discloses a chip bottom layer topology control method and system based on discrete space-time dual mapping, and belongs to the technical field of integrated circuit bottom layer intelligent control. In view of the bottom layer defects of traditional chip hardware and information being split, relying on external driving, architecture being solidified, scheduling being redundant, and lacking self-adaptive evolution capability, the application is based on the original TPS-CCC discrete space-time information-physical dual theory, constructs a three-dimensional topological dual mapping system, establishes hardware native topological evolution driving logic, and realizes chip computing power autonomous scheduling, hardware self-adaptive reconstruction, error self-healing correction and dynamic power consumption optimization. The application overturns the software passive control paradigm of the traditional chip, creates the next-generation chip bottom layer general paradigm of hardware-level autonomous intelligent control, has extremely high bottom layer theoretical barriers and full-coverage protection range, can be adapted to all types of high-end semiconductor chips, and has extremely strong industry monopoly and industrialization value.

The invention provides a simd-based floating point transpose logic implementation method, which comprises the following steps of: S1, respectively reading four rows of data of a matrix A by using an mx512laq2w instruction, respectively storing the four rows of data into an I0 register, an I1 register, an I2 register and an I3 register, and simultaneously reserving a space with the same size as the previous element behind each element for splicing operation; the method comprises the following steps: S1, respectively storing 64-bit low-order 32-bit data of an I1 register into 64-bit middle-high-order 32-bit data of an I0 register by using two ilvew instructions, and storing 64-bit low-order 32-bit data of an I3 register into 64-bit middle-high-order 32-bit data of an I2 register, and S3, respectively storing ab and cd at adjacent positions of the registers and storing a1b1 and c1d1 at adjacent positions of the registers for the I0 register and the I2 register by using an ilved instruction and an ilvod instruction; and S4, by using four data storage instructions saq instructions, storing front 128 bit data of the register I1 into the first row of the matrix A1, storing rear 128 bit data of the register I1 into the third row of the matrix A1, storing front 128 bit data of the register I1 into the second row of the matrix A1, and storing rear 128 bit data of the register I1 into the fourth row of the matrix A1 to obtain a matrix A transposed matrix A1.

The invention relates to an oil discharge eight-step method automatic supervision method fusing target detection and sequential logic. The method comprises the following steps: carrying out video monitoring on an oil discharge area of a gas station; collecting an oil unloading operation image when oil unloading operation is carried out in an oil unloading area of the gas station; and constructing an oil discharge eight-step method identification network and the like. According to the method, through the steps of installing the camera, collecting the oil unloading operation image and the like, an oil unloading eight-step method recognition network and cascade trigger type state machine logic are constructed, non-contact intelligent sensing of the whole process of oil unloading operation and real-time blocking of illegal behaviors are achieved, traditional civil air defense supervision is converted into standardized technical defense management and control, and the safety of the whole process of oil unloading operation is improved. Therefore, the intrinsic safety level of a petrochemical industry retail link is remarkably improved. The technical problems that in the prior art, a manual supervision mode has space-time blind areas and subjective hysteresis, a traditional universal vision algorithm is low in recognition precision on tiny key components such as an electrostatic grounding clamp, and rigid control over strict sequential logic of an operation process is lacked can be solved.

The embodiment of the invention provides a light application interaction method and device, equipment, a storage medium and a product. The method is applied to a terminal device, the terminal device runs a first application for providing a basic call function and a second application for providing a light application running environment, and the method comprises the following steps: in response to an event that an application data channel is successfully created, obtaining a target light application, and running the target light application through the second application; and displaying the interaction interface of the target light application on the interface upper layer of the interaction interface corresponding to the first application in a covering manner, thereby solving the technical problem that the existing call application is difficult to unify newly added functions, adapting to the interaction logic taking the first application as the core and the light application as the function supplement in the call scene, and improving the user experience. On-demand dynamic loading and display of services are realized; meanwhile, intelligent linkage of services and call scenes is achieved, seamless connection and rich and diversified call enhancement experience are provided for users, and the limitation that an existing call application is single in function is broken through.

The invention discloses a function enhancement method based on an activiti workflow engine, and the function enhancement method comprises the following steps: inheriting a DeFaultActivityBehaviorFactoryMappingConfiguer class, and carrying out the monitoring enhancement on the overall situation of the activiti; a core command mechanism of the Activiti is rewritten, so that the functions of randomly returning and randomly skipping the process which is not supported by the original are realized; a set of pluggable form construction factory mechanism is constructed; through an algorithm and data processing, a complex BPMN flow chart is converted into a linked list view which is easy to understand by business personnel, and future path prediction is provided; by customizing a multi-instance behavior of Activiti, real-time statistics of a passing number and a rejection number is added for a countersigning node, and countersigning judgment logic is realized. A future approval path prediction function based on an approval history linked list view and a recursive algorithm is realized, and understanding and decision support of business personnel on a process are remarkably improved.

The invention provides a frequency jittering clock signal generation method and device, and relates to the technical field of electronics. The method comprises the following steps: acquiring target jitter frequency parameters including a jitter frequency center frequency, a jitter frequency mode and a jitter frequency width; a modulation signal and a source clock signal are determined according to the target jitter frequency parameter, the amplitude of the modulation signal changes along with time, and the amplitude change range of the modulation signal is configured to enable the first-order sigma-delta modulator to work in an unsaturated linear response area; inputting the modulation signal to a first-order sigma-delta modulator, and under the driving of the source clock signal, performing pulse density modulation on the modulation signal by the first-order sigma-delta modulator and outputting a unit pulse density modulation code stream; and carrying out edge detection on the unit pulse density modulation code stream to generate a jittering frequency clock signal. According to the technical scheme, a complex phase-locked loop circuit is replaced by a scheme which is extremely simple in structure and is completely realized by digital logic, and the problem of balancing the integration level, the cost and the signal purity is synchronously solved.

The invention provides a double-active bridge resonant converter single-tube open-circuit fault detection method and system, and relates to the technical field of power electronics, and the method comprises the steps: extracting a fault characteristic quantity and constructing a judgment logic based on the characteristic analysis of a resonant capacitor voltage, a resonant current and a bridge arm current; and rapid detection and accurate positioning of the open-circuit fault of the DBSRC primary side or secondary side switch tube are realized. Compared with a traditional method, the detection process does not need to depend on a complex hardware structure or a neural network model, and the method has the advantages of being rapid in response, low in cost, convenient to deploy, high in positioning precision and the like, and is suitable for fault monitoring and fault-tolerant control in actual application scenes such as a high-frequency vehicle-mounted auxiliary converter.

The application discloses a flood scheduling gate operation logic anti-misoperation method and device based on rule self-learning, and particularly relates to the technical field of gate scheduling control systems. Trend results are generated by differentially determining the signs of the inflow and reservoir water level, consistency checking is performed in combination with the discharge variation direction and gate opening instruction to form an effective instruction sequence; the residual space amount of the downstream sensitive area is calculated, and the channel impact coefficient is generated in combination with the discharge impact amount and channel conditions; on this basis, the over-limit channel flow is reduced and distributed to the normal channel to form a rechecked sharing result. The application can realize trend dynamic judgment and instruction direction matching, guarantee discharge adjustment and hydrological condition consistency, and through the closed logic of reduction and distribution, the multi-channel flow sharing structure is optimized, the gate adjustment sequence logic is set according to the gate operation principle of the power station design, automatic matching of the discharge and gate adjustment is realized, and the situation of lower gate operation order is prevented.

The embodiment of the application discloses a decoding logic derivation method, a failed storage particle positioning method and related equipment, comprising: collecting all first error physical addresses generated by testing a same failed storage particle in a first physical slot to form a first error physical address set; collecting all second error physical addresses generated by testing the same failed storage particle in a second physical slot to form a second error physical address set; searching the first error physical address set and the second error physical address set to find k address bits, or a logical combination thereof, which is always a same value in binary logic values of all the first error physical addresses and is always an opposite value of the same value in binary logic values of all the second error physical addresses; and generating a Boolean function of the k address bits or the logical combination thereof as decoding logic. The application can automatically restore hidden physical address decoding logic and realize automatic, accurate and efficient positioning of the physical position of the failed storage particle.