7 results about "Test register" patented technology

The application discloses an SPI communication module and an SPI communication system, and belongs to the technical field of integrated circuits.The SPI communication module comprises an SPI function module and a test module, and the test logic of the test module and the function logic of the SPI function module are independent of each other.The test module comprises a plurality of test registers; the plurality of test registers are configured based on a CPU, and control the SPI communication module to work in a normal mode or a test mode; when the SPI communication module works in the normal mode, the test module does not work, and the SPI function module normally performs a communication function; when the SPI communication module works in the test mode, input signals and output signals of the SPI function module can be monitored through read-write access to the plurality of test registers, so that the test of the SPI communication module is realized.The design can help users to quickly locate an error source, reduces the test difficulty, improves the test efficiency, and simultaneously improves the test coverage.

The invention discloses a time delay circuit which comprises a first selector, a plurality of series-connected time delay units, an NAND gate, a second selector and a plurality of phase inverters, a first data input end of the first selector is connected with a first enable signal, and the first enable signal serves as an input signal of the time delay circuit in an input mode; the delay units are connected with the output end of the first selector, the first input end of the NAND gate is connected to the output end of the last-stage delay unit, the second input end of the NAND gate is connected with a second enable signal, the second enable signal is used for controlling the working mode of the delay circuit, and the selection control end of the second selector is connected to the output end of the NAND gate. The first data input end and the second data input end are connected through the first phase inverter, the output end is connected to the second data input end of the first selector through the second phase inverter, and the third phase inverter is connected to the output end of the second selector and used for outputting an output signal of the time delay circuit. The method is used for testing register establishment time and retention time.

The invention discloses a logic built-in self-test circuit and a related test method thereof.A chip module level circuit comprises an input port and a module register, and the input port is connected with the input end of the module register; the logic built-in self-test circuit comprises a signal blocking circuit which is connected between an input port and the input end of a module register, the signal blocking circuit comprises a selector and a test register, the first input end of the selector is connected with the input port, the second input end of the selector is connected with the output end of the test register, and the first input end of the selector is connected with the input port; the output end of the selector is connected with the input end of the module register; and the controller is connected with the selection end of the selector, is connected with the scanning input end, the scanning enabling end and the clock end of the module register, and is connected with the scanning input end, the scanning enabling end and the clock end of the test register. According to the scheme, the unknown state signal of the input port can be blocked, and the chip module level circuit can be tested.

A memory component includes: a memory cell comprising an array of memory cells; a controller for the memory cell; and a JTAG test interface including a plurality of contact pads adapted to connect the memory component to a host device and / or a test machine, wherein the test interface further includes a plurality of test registers configured to store operational instructions for performing the tests on the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. Related system-on-a-chip devices and related methods are also disclosed.

The application discloses a delay circuit, which comprises a first selector, a plurality of serially connected delay units, a NAND gate, a second selector and a plurality of inverters, wherein a first data input end of the first selector is connected with a first enable signal, the first enable signal is used as an input signal of the delay circuit in an input mode, the delay units are connected with an output end of the first selector, a first input end of the NAND gate is connected with an output end of the last stage delay unit, a second input end is connected with a second enable signal, the second enable signal is used for controlling a working mode of the delay circuit, a selection control end of the second selector is connected with an output end of the NAND gate, a first data input end and a second data input end are connected through a first inverter, an output end is connected with a second data input end of the first selector through a second inverter, a third inverter is connected with an output end of the second selector and is used for outputting an output signal of the delay circuit. The delay circuit is used for testing register setup time and hold time.

The application discloses a single-register multiplexing circuit and parameter configuration method for parameter configuration, and relates to the technical field of parameter configuration.The circuit comprises a group of configuration registers for storing and providing calibration parameters to an analog IP, wherein the configuration registers are multiplexed in a test mode and a normal working mode; and a multiplexing module coupled to the data input end of the configuration registers, used for selecting one way of data from a plurality of configuration data sources according to a preset priority strategy and writing the data into the configuration registers; wherein the plurality of configuration data sources at least include a default initial value, a nonvolatile memory loaded value and a test interface written value.The application effectively eliminates the problem that parameters cannot be effectively in real time in the traditional double-register architecture due to the separation of test registers and working registers, so that the calibration parameters written through the interface in the test stage can directly act on the analog IP, and it is not necessary to re-verify the power supply after burning the memory, thereby significantly improving the calibration efficiency.

The invention relates to a power consumption adjusting method for generating test excitation by an automatic test pattern. The method comprises the following steps: providing a test register module; analyzing the distribution condition of clock gating units ICG in the integrated circuit; and dynamically controlling an enabling signal of the ICG through the test register module based on an analysis result of the ICG distribution condition, so as to realize power consumption adjustment of ATPG test excitation generated by an automatic test pattern. By dynamically controlling the enable signal of the clock gating unit, the power consumption adjustment method for ATPG test excitation is realized, and the problems that the yield is reduced due to over-high test power consumption, the traditional threshold adjustment effect is poor and the like are solved.