A testable multiprocessor system and a method for testing a processor system

Abstract

A testable processor system (10,20) comprises a plurality of modules (11,12,...In). Each module (11) comprises a processor unit (110) and a debug controller (111). The debug controllers are coupled to a common test access point controller (TAP- controller 20), and have a test data input (Tin), a test data output (Tout) and at least one test register (112, 113). The test data inputs and outputs of the debug controllers (111, 121, 131, ...,InI) are arranged in a scan chain having an input for receiving test input data (TDI) from the TAP-controller and an output for providing test output data (TDO) to the TAP-controller. At least one debug controller (111) has a selection facility (115) to select whether data in the scanchain is either shifted through the at least one test register (112) of that debug controller (111) or is immediately forwarded from the test data input (Tin) to the test data output (Tout) of that debug controller. The at least one debug controller has a bypass register (117) which controls the selection facility. The TAP-controller (20) provides a control signal (BYPASS CNTRL) which, when active, selects the bypass register as part of the scan chain.

Description

Background technique [0001] The growing number of more complex systems requires test tools that support system debugging. In order to support this requirement, JTAG (Joint Test Action Group, Joint Test Action Group) has developed a standard, which provides a generally accepted interface. Among them, it is proposed to test the system by connecting the system register groups to be tested in the scan chain. The registers may be registers that have been set up for normal operation, or may be specially created registers for testing. Move the input test data into the scan chain. After one or more cycles of operation, the output test data is shifted out of the scan chain and can be analyzed. This makes it possible to read and write large amounts of test data using only a small bandwidth connection. [0002] If each module in a multiprocessor system had such a scan chain, the bandwidth required in the multiprocessor system would still be large, which would diminish the advantages....

AI Technical Summary

Problems solved by technology

For example, in a multiprocessor with 200 modules, whenever a 16-bit test address register needs to be written or read, an additional 200 bypass bits need to be written or read, which is more than 10 times the overhead

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