149 results about "Multi processor" patented technology

The invention belongs to the technical field of artificial intelligence and high-performance computing, and particularly relates to a neural network large model efficient reasoning method based on multiple GPGPUs. The method aims to solve the problems of high communication overhead, non-uniform load, low resource utilization rate, high data transmission delay and the like among multiple processors. Dividing a calculation task into a plurality of sub-graphs through static analysis and mixed granularity partitioning of a model calculation graph; distributing the sub-graphs to the optimal GPGPU based on a weighted cost function in combination with heterogeneous resource perception and a dynamic mapping strategy; a global pipeline scheduling plan is constructed by using communication topology perception, and calculation and communication overlap are maximized; data are loaded in advance through a host side hierarchical caching and asynchronous prefetching mechanism, and transmission delay is hidden; multi-stream concurrent execution and event-based lightweight synchronization are adopted on each GPGPU, so that waiting overhead is reduced. According to the method, the reasoning delay can be remarkably reduced, the throughput and the hardware utilization rate are improved, and the method has good adaptivity and expandability.

A symmetric auto-compiler system (1) and method for high performance hardware optimized auto-parallelization of program code (3) executed by a multi-core or multi-processor parallel processing system (2) having a plurality of processing units (21) that simultaneously process instructions for data in the parallel processing system (2) by executing the program code (3). The automatic compiler system (1) converts serial source code (31) of program code (3) into parallel processing machine code (32) comprising a plurality of instructions executable by a plurality of processing units (21) of the parallel processing system (2) or controlling operation of the plurality of processing units (21).

Techniques described herein can use a hybrid load balancing approach to balance loads on paths in a switch fabric. The switch fabric can deliver synchronization data between processors in a multi-processor cluster, and the synchronization data can load the paths on which it is sent. First paths can be identified in the switch fabric, and first synchronization data can be distributed to the first paths using a first load balancing approach, such as a telemetry assisted load balancing approach. Second paths can be identified in the switch fabric, and second synchronization data can be distributed to the second paths using a second load balancing approach, such as a packet spraying load balancing approach.

A system and method for universal static multi-transmit CPU design with a static pipeline for automatically parallelizing code is presented. A multi-core and / or multi-processor integrated circuit (2) has a plurality of processing units (21) and / or processing pipelines (53) that simultaneously process instructions for data by executing parallel processing machine code (32). The execution of the parallelized processing code (32) by the parallel processing multi-core and / or multi-processor integrated circuit (2) comprises the occurrence of a delay time (26), wherein the delay time is given by an idle time between the processing unit (21) returning the data after processing a specific instruction block of the processing code (32) for the data and receiving the data required by the processing unit (21) to execute a consecutive instruction block of the processing code (32). The parallel pipeline (53) comprises means for: (i) forwarding by providing a data forwarding from a MEM stage as an EX / MEM register to an EX stage as an ID / EX-stage register; (ii) exchanging by making the results of the Ex-ME-phase registers accessible by the Ex phase of a parallel pipeline (53) to provide a result exchange between the pipelines; and (iii) implementing branch pipeline refresh by providing control conflicts by refreshing only those pipelines (53) dependent on one pipeline (53) based on branch address computation conditions.

This invention relates to the field of multi-processor multi-task joint scheduling technology, specifically disclosing a typed task joint scheduling system and method based on a heterogeneous multi-core architecture. It introduces a joint scheduling mechanism to divide and sort tasks according to task size and priority. Based on this, for the time-limited characteristics of real-time tasks, an inertial weight coefficient particle swarm optimization method is used to iteratively update the load balancing strategy, minimizing the maximum response time of real-time tasks while meeting their schedulability requirements. Simultaneously, for the low-priority characteristics of non-real-time tasks, the problem-solving is simplified using a Lagrange-based convex optimization approach, and an energy-constrained binary search algorithm is employed to effectively reduce the average response time of non-real-time tasks, achieving optimal load distribution for the system.

A multi-processor communication framework (MCF) based on Transmission Control Protocol / Internet Protocol (TCP / IP) architecture is defined that can be used for inter-processor communication between heterogenous processing nodes. The MCF includes an application layer, a transport layer, a network layer, and an inter-processor communication (IPC) layer for each processing node. The IPC layer can be used to facilitate data transfer between two processing nodes via a physical channel within an electronic device, or through shared memory. The MCF can support multicast, broadcast, unicast, and zero-copy features like the TCP / IP stack.

A GEMM load-oriented GPU modeling method is characterized in that through a multi-stage collaborative modeling mechanism, cache behaviors, instruction overhead and calculation intensity are deeply coupled, accurate performance prediction of GPU execution GEMM operators is realized, the method can be widely applied to scheduling optimization of GPU intensive scenes such as AI training and scientific calculation, firstly, a three-stage cache weight distribution mechanism is established, and then, a three-stage cache weight distribution mechanism is established; quantifying the contribution of the L1 / L2 cache hit rate and the DRAM bandwidth degradation factor to the effective bandwidth; secondly, an instruction-level memory access overhead correction mechanism is introduced, and the mixing precision and the real calculation strength of a sparse calculation scene are captured through dynamic parameter adjustment and optimization; then combining the calculation force peak value and the bandwidth upper limit to construct a double-boundary constraint model, and generating a theoretical performance critical value; further predicting a stream multiprocessor utilization rate based on a neural network, and quantifying efficiency loss caused by hardware resource contention through a multi-layer perceptron structure; and finally, the integration module outputs task execution time to realize end-to-end performance prediction.

A multi-processor computing system (e.g., a system-on-chip) can store, in a shared memory, (i) a reservation table that is accessible by the one or more workload processors, and (ii) a scheduling program. The system can further execute the scheduling program to schedule execution of a set of workloads by one or more workload processors in accordance with an optimized compute graph, an optimized data positioning graph, and a coherence protocol that is precomputed based on the optimized compute graph and the optimized data positioning graph.

The application provides a GPU Warp scheduling method and device based on a chessboard scheduling strategy, and the method comprises the following steps: a stream multiprocessor assigns a Warp number to each task of different task types received through a facing Warp numbering mechanism, the priority of each Warp is determined according to the task type and the Warp number, the Warp with high priority is preferentially executed, if the current Warp execution is overdue, the priority of the Warp is dynamically adjusted, and the Warp with low priority is executed in turn. The facing Warp numbering mechanism is used to realize the priority ordering of the Warps of different task types, and the dynamic priority adjustment mechanism based on the execution time threshold can guarantee that the high-priority task is preferentially executed, also take into account that the low-priority task can be executed in a hidden manner, ensure fairness, and improve resource utilization.

The invention discloses an access address configuration method, a processor, a multiprocessor system, a medium and a product. The method comprises the following steps: configuring an independent register block for each thread bundle in the processor; wherein the register group is used for storing coordinate information of tensor data used in the execution process of a corresponding thread bundle program; reading the coordinate information of the tensor data to be processed from the register group, and sending the read coordinate information to a coprocessor to carry out access address calculation of the corresponding tensor data; according to the method, each thread bundle is provided with a group of entity registers for storing the coordinate information of the tensor data, multiple multiplexing of the coordinate information can be supported, and a large number of instructions for specifying coordinates are saved, so that the number of assembly instructions is reduced, the instruction overhead is effectively reduced, the execution time of a processor is saved, and the processing efficiency of the processor is improved.

Apparatuses, systems, and techniques to facilitate memory management. In at least one embodiment, data from one or more first shared physical memory locations is accessed based, at least in part, on one or more virtual addresses corresponding to one or more second shared physical memory locations.

A task scheduling system and method of a BPF-based on-chip heterogeneous multiprocessor system, comprising: a scheduling module and a sending module located at a general operating system Linux end, a receiving module located at a real-time operating system end, a BPF bytecode analysis and execution module and a calculation module, the application uses BPF virtual machine technology, uses BPF bytecode as the transmission carrier between the general operating system Linux and the real-time operating system of the on-chip heterogeneous multiprocessor, and schedules the to-be-processed application program in the part of the general operating system Linux to the real-time operating system in real time, and executes in the BPF instruction analysis and BPF virtual machine. The application can achieve certain load balancing and maximize the use of on-chip heterogeneous multiprocessor resources of the system without increasing the hardware design cost.

A symmetric automatic compiler system (1) and method for high-performance, hardware-optimized automatic parallelization of program code (3) for execution by a multicore or multiprocessor parallel processing system (2) having multiple processing units (21) that simultaneously process instructions for data in a parallel processing system (2) by executing program code (3). The automatic compiler system (1) converts the sequential source code (31) of program code (3) into parallel processing machine code (32) which includes several instructions that can be executed by multiple processing units (21) of the parallel processing system (2) or that control the operation of multiple processing units (21).

The invention discloses a method and system for deploying a multi-client operating system for preventing resource contention, and the method comprises the steps: generating a grouping information table and a resource distribution table based on the business demands and the total number of hardware resources of a multi-core processor system, the number of the processing groups is configured to be smaller than or equal to the total number of hardware resources which can be independently divided in the multi-core processor system, and the resource allocation table is used for storing a plurality of pieces of hardware resource allocation information corresponding to the processing groups; dividing the plurality of processing cores into each processing group based on the service requirements of the multi-core processor system and the grouping information table; and based on the resource allocation table, performing hardware resource configuration on each processing group so as to obtain a plurality of hardware resource isolated client operating systems. Based on the deployment method, isolation of hardware resources among multi-client operating systems can be realized, and the performance and resource occupation of a multi-processor system are optimized.

Examples include a communication device including a user interface (UI), a first electronic processor configured to detect and process UI input events, and a second electronic processor communicatively connected to the first electronic processor and configured to detect and process UI input events. The first electronic processor executes an application having a user inactivity timeout feature by initializing a countdown timer for a first time period, and, in response to expiration of the countdown timer, determining a user inactivity time for the communication device. The user inactivity time is a lesser of a time since a UI input event was last detected by the first electronic processor and a time since a UI input event was last detected by the second electronic processor. In response to the user inactivity time being greater than or equal to the first time period, the first electronic processor performs an application timeout function.

The invention discloses a cache coherence interconnection method, a cache coherence node and a multiprocessor system, relates to the field of computers, and provides the cache coherence interconnection method for solving the problems that a traditional cache coherence interconnection module is large in hardware resource overhead and insufficient in flexibility. Analyzing the memory access request to determine a source identifier; the source identifier is a unique identifier corresponding to a source processor of the memory access request sender; generating a monitoring address frame which carries the source identifier and corresponds to the memory access request, and sending the monitoring address frame to other processors through the interconnection module; after the monitoring data load returned in response is received, the memory access request is completed according to the monitoring data load. The method can get rid of dependence on complex structures such as directories, the cache consistency function can be achieved by using fewer hardware resources, decoupling between the cache consistency function and an interconnection structure can be achieved, and application of the cache consistency function is more flexible.

A multiprocessor system and method for swapping applications executing on the multiprocessor system are disclosed. The plurality of applications may include a first application and a plurality of other applications. The first application may be dynamically swapped with a second application. The swapping may be performed without stopping the plurality of other applications. The plurality of other applications may continue to execute during the swapping to perform a real-time operation and process real-time data. After the swapping, the plurality of other applications may continue to execute with the second application, and at least a subset of the plurality of other applications may communicate with the second application to perform the real time operation and process the real time data.

A system and method for designing a general-purpose static multi-issue CPU using static pipelining of automatically parallelized code is proposed. A multicore and / or multiprocessor integrated circuit has multiple processing units and / or processing pipelines that simultaneously process instructions for data by executing parallelized processing machine code. The execution of parallelized processing code by a multicore and / or multiprocessor integrated circuit that performs parallel processing involves the occurrence of latency, which is given by the idle time of the processing unit between the time the processing unit processes a particular block of instructions in the processing code for data and sends the data back, and the time the processing unit receives the data necessary to execute a successive block of instructions in the processing code. The parallel pipeline includes means for (i) forwarding by providing data forwarding from the MEM stage as an EX / MEM register to the EX stage as an ID / EX stage register, (ii) exchange by providing result exchange between pipelines by making the Ex-MEM stage register results accessible to the EX stage of the parallel pipeline, and (iii) means for branch pipeline flushing with control hazards by flushing only pipelines that depend on one pipeline that calculates conditions based on branch addresses.

A method is provided for performing transaction processing in a system. The system includes a plurality of processors and a corresponding table. Each processor executes the same transaction. Two of the processors receive a request to process the same transaction. Each of the two processors execute the request to process the same transaction. The executing of the request generates the data and at least some of the data is expected diverging data. Each of the two processors create indicia from the data. Some of the indicia is diverging indicia generated from the expected diverging data. The same transaction tag is assigned to each of the indicia. The correspondence table is populated with the transaction tag and the expected diverging data, thereby mapping the diverging indicia created by each of the two processors that executed the same transaction. The indicia associated with the same transaction tag are compared to each other. The mapping of the diverging indicia allows for a comparison of the indicia so as to determine whether the indicia associated with the same transaction tag match each other. A remediation action is taken when the indicia associated with the same transaction tag do not match each other.

The application provides a method and system for multiprocessor time division multiplexing GPIO, the method runs in a chip and comprises the following steps: initializing the value of each bit of a register to indicate the priority of a processor, the processor is connected with the corresponding bit of the register; gating a first processor to control a GPIO module; when the Nth processor needs to obtain the control right of the GPIO module, modifying the value of the corresponding bit of the register connected with the Nth processor in response to the interaction between the Nth processor and the first processor to obtain the control right; sending an enable signal of a bus control operation to enable the Nth processor to send a bus control operation to the back end; the Nth processor is any processor different from the first processor. Based on the method, a system for multiprocessor time division multiplexing GPIO is also provided. The application adopts the mode of multiprocessor time division multiplexing, uses the existing pins, and when the number of processors increases, different processors can be time division multiplexed through the priority arbitration scheme mechanism.

The application belongs to the technical field of artificial intelligence and high-performance computing, and specifically relates to a neural network large model efficient inference method based on multiple GPGPUs. The method aims to solve the problems of large communication overhead between multiple processors, uneven load, low resource utilization, and high data transmission delay. Through static analysis and mixed-granularity partitioning of the model computation graph, the computation task is divided into multiple subgraphs; combined with heterogeneous resource perception and dynamic mapping strategy, the subgraphs are allocated to the optimal GPGPU based on a weighted cost function; a global pipeline scheduling plan is constructed using communication topology perception to maximize computation and communication overlap; data is loaded in advance through the host-side hierarchical cache and asynchronous prefetch mechanism to hide transmission delay; and multi-stream concurrent execution and event-based lightweight synchronization are adopted on each GPGPU to reduce the waiting overhead. The application can significantly reduce inference delay, improve throughput and hardware utilization, and has good adaptability and scalability.

According to certain implementations, a motherboard is provided that enables operation as either multiple independent single-processor systems or a single multiple-processor system. In response to a request to configure the motherboard as multiple independent single-processor systems, a control block is implemented for each processor attached to the motherboard, where the control blocks configure the processors to boot and operate independently of each other, and the processors utilize separate motherboard resources. In response to a request to configure the motherboard as multiple independent single-processor systems, a single control block is implemented all processors attached to the motherboard, where the single control block configures all processors to boot and operate in a connected state, and the processors share all motherboard resources.

This invention relates to the field of artificial intelligence and industrial nondestructive testing, and discloses a multi-processor nondestructive defect detection method based on multimodal information fusion. The method includes: spatial registration of CT data and infrared thermal imaging data; dividing the registered data into multiple image blocks and extracting primary features; screening based on D-S evidence theory to identify suspicious image blocks; inputting the CT image blocks and infrared image blocks corresponding to the suspicious image blocks into a dual-stream convolutional neural network to output a set of suspicious image blocks; marking the connected regions of the output set, merging adjacent image blocks of the same category, calculating defect parameters, filtering out noise regions, and generating the final detection result. This invention can achieve accurate detection of various internal defects such as pores and cracks by fully utilizing the internal structural information provided by CT and the thermal diffusion anomaly information provided by infrared without damaging the multi-processor workpiece, and effectively handles sensor information conflicts and uncertainties.

The application discloses a multi-core inter-core real-time communication system and method, which comprises a hardware layer, a driver layer and a communication layer. Firstly, the hardware layer is used for managing and classifying a plurality of processors, and corresponding memory spaces are divided according to the classification results, and the shared memory is used to realize the access of the processors to the shared resources. Then, the driver layer is used for loading and managing an RPMsg driver program on a virtual hardware platform provided by the hardware layer, registering a driver device to provide data storage services, creating a driver component to provide data transmission services, and providing driver services for the communication layer through a driver calling interface. Finally, the communication layer is used for calling a driver interface function to manipulate an RPMsg driver module, realizing the receiving and transmitting operations of data, and establishing an inter-core logical connection through an RPMsg channel, so as to realize the inter-core communication of the multi-core. The inter-core communication technology based on the RPMsg channel is adopted, and a solution is provided for solving the parallel running and collaborative scheduling of the plurality of processors.

The invention relates to an MIPS multiprocessor system based on a CXL interface and computer equipment. The system comprises: at least one MIPS processor core; the consistency management module is connected with each MIPS processor core through an MCP bus, and the consistency management module is used for managing the internal cache consistency of each MIPS processor core; and the CXL controller is integrated in the consistency management module and is used for managing the cache consistency between the MIPS multiprocessor system and the external heterogeneous CXL equipment based on a CXL protocol. The consistency management module of the system internally manages the internal cache consistency of each MIPS processor core, and externally realizes the cache consistency between the MIPS multiprocessor system and an external heterogeneous CXL device through the CXL controller, so that a double-level consistency architecture is realized, and the processing performance of a heterogeneous computing unit is improved.

The invention discloses a parallel processor cluster, a topology switching method, electronic equipment and a storage medium, and is applied to the field of multiprocessor systems. The parallel processor cluster comprises M parallel processors and N optical circuit switches, N ports on each parallel processor are coupled with the N optical circuit switches in a one-to-one correspondence mode, the total number of the ports of each parallel processor is larger than M, N is smaller than M. A topological structure of the parallel processor cluster comprises a first topological structure and a second topological structure, the parallel processor cluster supports switching of a first topological structure and a second topological structure, in the first topological structure, M parallel processors are divided into L groups, each group comprises M / L parallel processors, the M / L parallel processors are fully connected, in the second topological structure, the M parallel processors are fully connected, and M, N and L are positive integers. The parallel processor cluster can adapt to different network models, can achieve better performance in the different network models, and gives full play to hardware resource performance.

Techniques described herein can use a hybrid load balancing approach to balance loads on paths in a switch fabric. The switch fabric can deliver synchronization data between processors in a multi-processor cluster, and the synchronization data can load the paths on which it is sent. First paths can be identified in the switch fabric, and first synchronization data can be distributed to the first paths using a first load balancing approach, such as a telemetry assisted load balancing approach. Second paths can be identified in the switch fabric, and second synchronization data can be distributed to the second paths using a second load balancing approach, such as a packet spraying load balancing approach.

The application discloses a GPU space resource partitioning method and system based on a persistent thread, and belongs to the field of high-performance computing and computer system structure.The method extracts original PTX code from a binary module by dynamically intercepting a CUDA interface at a driver layer; a static compiling conversion technology is used to recombine an instruction stream, construct a persistent thread structure, and innovatively introduce a "kernel fusion" mechanism in the persistent thread; through instruction body multiplication and virtual index remapping, the static demand of a single physical thread block for registers and shared memory is artificially doubled, so that the single physical thread block reaches the upper limit of hardware resources of a streaming multiprocessor; finally, a kernel starting interface is intercepted, and the original kernel is transparently replaced by the converted kernel.The application effectively solves the defect that traditional persistent threads cannot realize strict physical exclusive on a streaming multiprocessor due to unsaturated resource occupation, and realizes fine-grained and deterministic partitioning and isolation of GPU space resources without modifying user source code.

The application discloses a first graphics processor, a remote communication method, a chip, a server and equipment, and belongs to the chip field.The first graphics processor comprises a plurality of processors, a data loading engine and a global storage unit, the data loading engine comprises a remote communication channel;the remote communication channel is used for receiving a remote communication instruction sent by the plurality of processors;and the remote communication channel is used for reading target data from the global storage unit in response to the remote communication instruction and sending the target data to a second graphics processor.The application sets the remote communication channel on the data loading engine, reads the target data by the remote communication channel when the plurality of processors execute a remote communication task, and sends the target data to the second graphics processor, without temporarily storing and forwarding the target data by the storage resource in the plurality of processors, so that the internal resource of the plurality of processors can be inclined to a calculation task, and the calculation task and the remote communication task can be concurrently executed on the same plurality of processors.

The invention provides an online dynamic adjustment method, system and device for control parameters and a medium, and the method comprises the steps: collecting storage use data from each processor node, processing state fluctuation in a multi-node environment through employing a distributed collection protocol, and obtaining the current storage occupation proportion of each node; determining high-load state nodes by adopting a threshold comparison method according to the current storage occupation proportion of each node; analyzing a storage state of a processor node adjacent to the high-load state node, and determining a target node of the migration task; and sending a part of data packets of the high-load node to a target node through a transmission path based on an encrypted transmission protocol to complete online dynamic adjustment. According to the method, real-time monitoring of the storage state is realized in a multiprocessor environment, and storage resources are dynamically balanced through a collaboration mechanism among nodes.