505 results about "Multi processor" patented technology

The invention relates to the technical field of large models, in particular to a large-model-oriented reasoning service system and an inter-stage resource adjustment method, and the system comprises a pre-filling processor and a decoding processor; a computing resource controller implementing computing resource control of the prefill processor and the decode processor based on a multi-process service, the multi-process service allowing a target number of streaming multiprocessors to be designated to a prefill process representing an entity of the prefill processor and a decode process representing an entity of the decode processor; and the unified storage manager is used for managing the storage utilization rate of the system and the storage access of the pre-filling processor and the decoding processor to the large model weight and the KV cache. Therefore, the problems of delay interference, low storage efficiency and the like between pre-filling and decoding in related technologies are solved.

The invention provides a many-core cache consistency system, a many-core cache consistency method, electronic equipment, a storage medium and a product, and the system is based on a network-on-chip architecture, and a plurality of nodes, corresponding routers and distributed directories deployed in the routers are introduced. Each node comprises one or more processor cores and a distributed last-stage cache, and a memory address is divided into a plurality of address blocks and is associated with the distributed last-stage cache through a dynamic address mapping rule. The distributed directories and the distributed last-stage caches are in one-to-one correspondence and used for recording the states of cache lines, the router is responsible for receiving and responding to requests from local or remote nodes, querying the distributed directories and updating the states of the cache lines, and efficient management of cache consistency is achieved. The technical scheme belongs to the technical field of communication, effectively solves the problems of high load and communication delay of a main node in a traditional cache consistency protocol, and improves data consistency and access efficiency in a multiprocessor system and a large-scale parallel computing environment.

The invention relates to the field of satellite navigation anti-interference and the technical field of computers, and discloses a multi-processor core communication method and device, electronic equipment and a storage medium, and the method comprises the steps that a second processor core writes target information into a shared memory, and obtains a first idle channel number; the second processor obtains a first interrupt signal based on an interrupt trigger register corresponding to the first idle channel number; the first processor core reads target information in a shared memory according to the first interrupt signal; the first processor core processes the target information to obtain a processing result, and writes the processing result into the shared memory to obtain a second idle channel number; the first processor core obtains a second interrupt signal based on an interrupt trigger register corresponding to the second idle channel number; and the second processor core reads the processing result in the shared memory according to the second interrupt signal, and writes the processing result into the cache region. The multi-processor core communication method is suitable for different operating systems and is high in transportability.

Aspects of the present disclosure generally relate to systems and methods for flight control of aircrafts driven by electric propulsion systems and in other types of vehicles. In some embodiments, a computer-implemented method for controlling an aircraft is disclosed, comprising: receiving, from a source processor, a first copy of a signal corresponding to an input device; sending a second copy of the signal to all other processors; receiving a number of second copies of the signal from all other processors, the number of second copies being equal to the number of all other processors excluding the source processor; determining a consensus signal based on the first copy and the second copies of the signal; and determining a command signal for an effector of the aircraft based on the consensus signal, and wherein no two processors are configured to receive signals from a same input device.

The invention belongs to the technical field of artificial intelligence and high-performance computing, and particularly relates to a neural network large model efficient reasoning method based on multiple GPGPUs. The method aims to solve the problems of high communication overhead, non-uniform load, low resource utilization rate, high data transmission delay and the like among multiple processors. Dividing a calculation task into a plurality of sub-graphs through static analysis and mixed granularity partitioning of a model calculation graph; distributing the sub-graphs to the optimal GPGPU based on a weighted cost function in combination with heterogeneous resource perception and a dynamic mapping strategy; a global pipeline scheduling plan is constructed by using communication topology perception, and calculation and communication overlap are maximized; data are loaded in advance through a host side hierarchical caching and asynchronous prefetching mechanism, and transmission delay is hidden; multi-stream concurrent execution and event-based lightweight synchronization are adopted on each GPGPU, so that waiting overhead is reduced. According to the method, the reasoning delay can be remarkably reduced, the throughput and the hardware utilization rate are improved, and the method has good adaptivity and expandability.

Approaches presented herein provide systems and methods for allocating streaming multiprocessors (SMs) to execute one or more tasks. A utilization for a given task may be determined by one or more parameters, such as a task execution time or a period. The utilization may then be used to assign a proportionate number of SMs associated with a processing unit, such as a graphics processing unit (GPU) or other type of processing unit, executing the task. The SMs may then be identified, allocated, and reserved until execution of the task is complete.

A material transfer machine comprises a material container containing material and a material transfer system capable of transferring the material from the material container to another location, wherein the material transfer system comprises a discharge pipe movable between an operating position and a storage position and an actuator driving the movement of the discharge pipe between the operating position and the storage position.The material transfer machine further comprises one or more processors, a memory, and computer-executable instructions stored in the memory which, when executed by the one or more processors, configure the one or more processors to: receive an input indicating that the unloading tube should be moved from the operating position to the storage position; identify a pivot zone that defines an area in which the unloading tube will move when moved by the actuator from the operating position to the storage position; and generate a control signal based on the determination.

Systems and techniques are described for training and using a generative adversarial network (GAN) to produce intermediate stages and final setups for clear tray aligners (CTAs) including receiving, by one or more computer processors, a first digital representation of a patient's teeth, using, by the one or more computer processors and to determine a prediction for one or more tooth movements, a generator that is a neural network included in a GAN and that has been trained to predict one or more tooth movements, and producing, by the one or more processors, an output state that includes at least one of a final setup and one or more intermediate stages.

The invention provides a thread block scheduling module, a general-purpose computing graphic processing unit, equipment and a product, and relates to the technical field of data process.The method comprises the steps that an operation data analysis unit conducts data analysis on all first thread blocks of a computing task issued by a host, and second thread blocks sharing data with all the first thread blocks are determined; the mapping relation between the first thread block and the second thread block is written into a thread block data mapping table of the queue management unit; the resource management unit is used for recording available resources and used resources of each streaming multiprocessor and information of a thread block currently allocated to each streaming multiprocessor; and the thread block allocation unit is used for allocating the thread blocks of the first target thread block to the corresponding stream multiprocessors according to the thread block data mapping table of the first target thread block under the condition of detecting that any stream multiprocessor recorded by the resource management unit has idle available resources.

Certain aspects of the present disclosure provide techniques and apparatus for scheduling execution of machine learning model operations on a multiprocessor computing device. The method generally includes during execution of operations in a first portion of a machine learning model on a first processing unit of the computing device, measuring a temperature for each of a plurality of locations on the computing device. It is determined that a temperature measured for the first processing unit exceeds a threshold temperature. Based on one or more operating parameters for the computing device, a second processing unit of the computing device is selected to use in executing operations in a second portion of the machine learning model. Execution of operations in the second portion of the machine learning model on the second processing unit is scheduled.

The invention relates to the technical field of parallel computing chips, in particular to a multiprocessor management method and device based on a parallel computing chip and a medium. The method comprises the steps that a plurality of stream processors are organized according to a hierarchical arrangement mode, a hierarchical SM cluster is formed, and each stage of SM core only keeps cache consistency with a lower stage of SM core directly controlled by the SM core; data of an external storage module enters a scheduling core through an L2 cache, and the scheduling core splits the data into thread bundles and dynamically allocates the thread bundles to a target SM core; when the thread processing demand of the target SM core exceeds the current capacity, starting a lower-level SM core according to a preset hierarchy rule, and expanding the processing capacity step by step; and skipping an unprocessed thread bundle over the current SM core through a thread bundle scheduler, splitting the unprocessed thread bundle, transmitting the split unprocessed thread bundle to a lower-level SM core, and merging calculation results of the lower-level SM core step by step through a shared memory. According to the invention, extra resources allocated by the system can be reduced, and the whole system is more efficient and ordered on the basis of ensuring consistency.

A symmetric auto-compiler system (1) and method for high performance hardware optimized auto-parallelization of program code (3) executed by a multi-core or multi-processor parallel processing system (2) having a plurality of processing units (21) that simultaneously process instructions for data in the parallel processing system (2) by executing the program code (3). The automatic compiler system (1) converts serial source code (31) of program code (3) into parallel processing machine code (32) comprising a plurality of instructions executable by a plurality of processing units (21) of the parallel processing system (2) or controlling operation of the plurality of processing units (21).

The invention discloses a task processing method and system, electronic equipment, a storage medium and a program product, and relates to the technical field of computers. The method comprises the following steps: when multiple processors cooperatively execute a to-be-processed task, determining that the to-be-processed task belongs to a communication dominant task according to memory access behavior characteristics of the to-be-processed task, and synchronizing far-end data of each processor to a local far-end data cache space. Reading target read data from the far-end data cache space when the far-end read operation is carried out; when far-end write operation is carried out, target write data written into the target local cache space is written into the local far-end data cache space, and meanwhile corresponding data in the target local cache space is invalid and synchronized to the target local cache space. According to the invention, the problem of low calculation efficiency of multiprocessor cooperative processing tasks in the prior art can be solved, the communication delay of the multiprocessor cooperative processing tasks can be reduced, the efficiency of the multiprocessor cooperative processing tasks is effectively improved, and the task processing performance of the multiprocessor is improved.

An agricultural system comprises: one or more weight sensors that detect the weight of the material in a first material container and generate sensor data indicating this weight; one or more processors; a memory; and computer-executable instructions stored in the memory which, when executed by the one or more processors, configure the one or more processors to: determine a weight change of the material in the first material container based on first sensor data indicating a weight of the material in the first material container at a first time point, and second sensor data indicating a weight of the material in the first material container at a second time point; determine a material overload rate indicating a rate at which a material overloading subsystem overloads material based on the determined weight change;and to determine a material fill level in a second material container based on the specified material overload rate.

The invention provides a thread block scheduling method and system for a universal graphics processor, and belongs to the technical field of computational graphics process.The method comprises the steps that a computational task from a host is received, and the computational task comprises at least one thread block; according to the workload of each thread block, all the thread blocks are distributed to at least one thread block queue, and each thread block queue corresponds to one capacity; obtaining the free resource quantity of each streaming multiprocessor in the universal graphics processor; determining a matched thread block queue according to the free resource quantity of any available streaming multiprocessor, extracting thread blocks from the matched thread block queue, and distributing the thread blocks to the available streaming multiprocessors; the available streaming multiprocessors are streaming multiprocessors of which the free resource quantity meets a preset thread block allocation standard. According to the method, a plurality of thread block queues are arranged, and the thread blocks are dynamically selected according to the real-time idle resources of the streaming multiprocessor for fine distribution, so that the overall calculation performance and the operation efficiency of the GPGPU are improved.

Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.

The invention discloses a server, and relates to the technical field of servers, the server comprises at least one mainboard and at least one backboard, each mainboard comprises a central processing unit, the central processing units are mutually independently arranged, each backboard is provided with at least one hard disk, each hard disk is based on a disk sequence of the hard disks, and each hard disk is provided with at least one hard disk. According to the technical scheme, the central processing unit is connected with the nearest central processing unit, so that the central processing units can independently operate and execute the functions of data storage and data operation, the problem of load imbalance existing in the multiple central processing units in the server can be avoided, and the operation efficiency in a multi-processor mode is improved.

For concurrent data transmission, an example method includes acquiring a processor utilization rate related to transmission of historical data packet(s) and a bandwidth utilization rate of a data link within a target time period. A time consumption for transmitting a target data packet, a splitting processing resource related to a splitting operation, and a packaging processing resource related to a packaging operation are determined. Based on the processor utilization rate, the bandwidth utilization rate, the time consumption, the splitting processing resource, and the packaging processing resource, a split number is determined for the target data packet to concurrently transmit the target data packet. In this way, a data transmission speed can be improved, time consumed for transmitting the target data packet can be reduced, and meanwhile, it can also alleviate problems such as excessive processing resource consumption and overloaded operation of the processor caused by concurrent transmission.

The invention discloses a GPGPU thread block synchronization method and device based on a thread lock and a medium, and relates to the technical field of electric digital data processing. The method comprises the following steps: a thread block scheduling module allocates thread blocks for each stream multiprocessor and calculates a thread start ID (Identity) to maintain a corresponding thread lock table; analyzing whether a dependency relationship exists between the memory access request and a thread in the currently occupied thread block or not under the condition that the memory access requirement exists, and if yes, adding the memory access request with the dependency relationship to a lock queue; querying a thread lock state of a thread having a dependency relationship with the memory access request in a corresponding thread lock table so as to add the thread lock state to an entry state corresponding to the lock queue; and dequeuing the memory access request from the lock queue under the condition that the entry states of all the threads with the entries in the lock queue and the thread bundle having the dependency relationship are unlocked, and performing memory access according to the memory access request to realize synchronization of GPGPU thread blocks.

A system contains a network of processors arranged in a plurality of nodes. Each node comprises a respective plurality of processors connected via local links, and different nodes are connected via global links. The processors of the network communicate with each other to establish a global counter for the network, enabling deterministic communication between the processors of the network. A compiler is configured to explicitly schedule communication traffic across the global and local links of the network of processors based upon the deterministic links between the processors, which enable software-scheduled networking with explicit send or receive instructions executed by functional units of the processors at specific times, to establish a specific ordering of operations performed by the network of processors. In some embodiments, the processors of the network of processors are tensor streaming processors (TSPs).

The invention relates to the field of sparse matrix calculation, and discloses a sparse calculation unit, method, device and medium under a GPGPU architecture, the sparse calculation unit comprises a sparse matrix operation unit arranged in a streaming multiprocessor, and the sparse matrix operation unit is connected with a transmitting module and a write-back module; the sparse matrix operation unit comprises a selector, an algorithm module, an accumulator and a plurality of second buffer modules; the sparse matrix operation unit is used for calculating the sparse matrix; a calculation algorithm is stored in the algorithm module and used for calculating matrix elements, and the calculation algorithm comprises an improved SPGEMM algorithm and an addition algorithm; and the memory access unit scheduling module is connected with the plurality of streaming multiprocessors and is used for coordinating and scheduling the memory access units on the plurality of streaming multiprocessors. And the sparse matrix calculation unit is added, so that the processing capability of the GPGPU on the sparse matrix is improved, and the operation speed of the GPGPU on the sparse matrix calculation task is improved.

Methods and systems are disclosed using an execution pipeline on a multi-processor platform for deep learning network execution. In one example, a network workload analyzer receives a workload, analyzes a computation distribution of the workload, and groups the network nodes into groups. A network executor assigns each group to a processing core of the multi-core platform so that the respective processing core handle computation tasks of the received workload for the respective group.

Methods and systems are disclosed using an execution pipeline on a multi-processor platform for deep learning network execution. In one example, a network workload analyzer receives a workload, analyzes a computation distribution of the workload, and groups the network nodes into groups. A network executor assigns each group to a processing core of the multi-core platform so that the respective processing core handle computation tasks of the received workload for the respective group.

The present disclosure provides a method, apparatus and system for monitoring ultra-high frequency partial discharge of a hydro-generator, and belongs to the technical field of hydro-generator partial discharge monitoring. The method includes: cleaning a partial discharge pulse sequence using a cleaning threshold to obtain a valid pulse sequence; performing redundant data filtering on each data unit divided from the valid pulse sequence to obtain a first target pulse sequence for short-period partial discharge monitoring; determining sub-sequences that are partial discharge events from the valid pulse sequence, forming a second target pulse sequence after associating an amplitude statistical feature of the sub-sequences, and storing the second target pulse sequence. The aforementioned method combines data cleaning, redundant data filtering, and partial discharge event identification, which enhances the real-time performance of partial discharge monitoring and records the long-period partial discharge change trend. The corresponding system adopts a multi-buffer zone and multi-processor architecture, thus further improving the real-time performance of partial discharge monitoring.

A device can provide a unified and scalable multiprocessor communication framework that enables communication between multiple processor cores in a multicore device. For example, the device may be configured to perform data payload management using a Smart Message Queue (SMQ) and / or shared memory. Additionally or alternatively, the communication framework may enable the processors to communicate with each other and / or peripherals of the device while abstracting details of various communication protocols, hardware interfaces, and / or the like. For example, the communication framework may provide a common interface for applications, enabling a first application associated with a processor to establish a connection to any processor and / or peripheral without knowing details of a communication protocol for each connection.

Techniques described herein can use a hybrid load balancing approach to balance loads on paths in a switch fabric. The switch fabric can deliver synchronization data between processors in a multi-processor cluster, and the synchronization data can load the paths on which it is sent. First paths can be identified in the switch fabric, and first synchronization data can be distributed to the first paths using a first load balancing approach, such as a telemetry assisted load balancing approach. Second paths can be identified in the switch fabric, and second synchronization data can be distributed to the second paths using a second load balancing approach, such as a packet spraying load balancing approach.

There is provided a computer-implemented method of predicting a timeseries of time delays resulting from contention between tasks running in parallel on a multi-processor system using a trained Machine Learning based Task Contention Model, ML based TCM. The method comprises: executing a plurality of actual execution tasks on the multi-processor system in isolation, and for each task and during execution of the respective task, capturing a timeseries comprising a plurality of uWindows by capturing a plurality of snapshots, each snapshot comprising an array of performance monitoring counters, PMCs, since the previous snapshot, and the time since the previous snapshot. The method also includes inferring, from a time-agnostic ML based regressor, a predicted contention delay for the first uWindow of the timeseries when two or more of the plurality of actual execution tasks are executed on parallel on the multi-processor system given the first captured snapshot for each of the tasks to be completed in parallel. The method further includes inferring, from a Non-linear AutoRegressor with exogenous inputs, NARX, predicted contention delays for each subsequent uWindow of the timeseries based on the respective captured snapshot, and the predicted values for the previous time periods fed back into the NARX.

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

Various embodiments include techniques for processing memory operations in a computing system. The computing system includes a central processing unit (CPU) and an auxiliary processor, such as a parallel processing unit (PPU). The PPU can be divided into multiple partitions. Although the partitions are included in a single PPU, the CPU can track the partitions as if the partitions are independent devices rather than different portions of a single device. When two different partitions generate memory operations that access the same memory address in CPU memory address space, the two partitions employ two different data paths. The CPU can use path information for the two different paths to identify which partition generated each memory operation. As a result, the CPU can maintain data consistency and memory coherency in a system where a PPU is divided into multiple partitions.

A multi-processor computing system (e.g., a system-on-chip) can store, in a shared memory, (i) a reservation table that is accessible by the one or more workload processors, and (ii) a scheduling program. The system can further execute the scheduling program to schedule execution of a set of workloads by one or more workload processors in accordance with an optimized compute graph, an optimized data positioning graph, and a coherence protocol that is precomputed based on the optimized compute graph and the optimized data positioning graph.