12 results about "Symmetric multiprocessing" patented technology

A platform architecture design method for the operating mode of a multi-core CPU. The platform architecture design method includes the following steps: The homogeneous multi-core CPU first starts the main core, and the main core is core0 of the homogeneous multi-core CPU; The main core wakes up the slave cores during the initialization phase; After the slave cores are started, the slave cores operate in a combined manner of AMP / SMP; The main core runs the general underlying software of the platform. Here, CPU is the central processing unit, AMP is asymmetric multi-processing, and SMP is symmetric multi-processing. The EHMP operating mode proposed by the present invention combines the advantages of the traditional AMP and SMP modes, follows the principle of realizing high-reliability and high-real-time functions in the bare-running mode and realizing non-strong real-time functions in the operating system mode, takes into account the reliability, real-time performance and CPU processing power of the product, and ensures the security of multi-core operation and system reliability.

Embodiments are for processor cross-core cache line contention management. A computer-implemented method includes sending a cross-invalidate command to one or more caches based on receiving a cache state change request for a cache line in a symmetric multiprocessing system and determining a retry delay based on receiving a cross-invalidate reject response from at least one of the one or more caches. The computer-implemented method also includes waiting until a retry delay period associated with the retry delay has elapsed to resend the cross-invalidate command to the one or more caches and granting the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.

A system and method of handling interrupts in a symmetric multiprocessing system is disclosed. The symmetric multiprocessing system may comprise a plurality of ARM processors, such as Cortex-M processors. All of the possible interrupt sources are routed to all of the processing units. A message handling unit (MHU) is used to communicate between processing units to relay information about the interrupts. A MHU interrupt service routine is used to handle the enabling and disabling of the various interrupt sources, as requested by the other processing unit. The MHU interrupt service routine also tracks whether the interrupt that is to be disabled is currently executing.

Efficient central processing unit overcommit for virtual machines with symmetric multi-processing may be provided by, in response to receiving a preemption-disable request on behalf of a virtual machine (VM) running on a physical central processing unit (PCPU), initiating a counter on the PCPU; in response to receiving a preempting task from a hypervisor to perform on the PCPU, checking a counter status for the counter; in response to the counter status being active: performing an ongoing task from the VM on the PCPU; and delaying performance of the preempting task until the counter status is inactive.

This disclosure discloses a task migration method, apparatus, electronic device, and storage medium, relating to the field of computer technology, and particularly to the field of asymmetric multiprocessor systems. The specific implementation is as follows: In response to detecting an operational anomaly in an asymmetric multiprocessor system, load information of the asymmetric multiprocessor system and error information of the abnormal processor core are obtained. The asymmetric multiprocessor system includes multiple processor cores with independent memory address spaces. Based on the error information, at least one candidate processor core from the multiple processor cores and the target task to be migrated from the abnormal processor core are determined. Based on the load information, the target processor core is determined from the at least one candidate processor core. The target task to be migrated is then migrated to the target processor core.

Embodiments include an asymmetric multiprocessing (AMP) system having two or more central processing unit (CPU) clusters of a first core type and a CPU cluster of a second core type. Some embodiments include determining a control effort for an active thread group, and assigning the thread group to a first performance island according to the control effort range of the first performance island. The first performance island can include a first CPU cluster of the first core type, where a second performance island includes a second CPU cluster of the first core type, where the second performance island corresponds to a different control effort range than the first performance island. Some embodiments include assigning the first CPU cluster as a preferred CPU cluster of the first thread group, and transmitting a first signal identifying the first CPU cluster as the preferred CPU cluster assigned to the first thread group.

The present invention proposes a task processing method and device based on a multi-core system, the method comprising: dividing the CPU core into a business core set domain and a control core set domain; binding the business processing task to the business core in the business core set domain, and having the business core process the business processing task. According to the task processing method based on a multi-core system of the present invention, by dividing the CPU into a business core set domain and a control core set domain, binding the business processing task to the business core, and having the business core process the business processing task, in a symmetric multi-processing system, it can dynamically and smoothly switch to an asymmetric multi-processing state in the business logic, so that the business processing task completely exclusively runs the business core, and will not cause bottlenecks due to system jitter, thereby affecting business performance and indicators, thereby making full use of the single-core CPU processing power of the business core and improving business processing performance.

According to certain embodiments, a system includes one or more processors and one or more computer-readable non-transitory storage media comprising instructions that, when executed by the one or more processors, cause one or more components to perform operations including executing a software process of a secondary instance, the secondary instance running in parallel with a primary instance and associated with a plurality of cores including a bootstrap core, registering a non-maskable interrupt for the bootstrap core in the secondary instance, determining whether the secondary instance is in a fault state, wherein, if the secondary instance is in the fault state, halting the plurality of cores associated with the secondary instance, without impact to the primary instance, and recovering the bootstrap core by switching a context of the bootstrap core from the secondary instance to the primary instance via the non-maskable interrupt.

An interrupt routing method includes receiving an incoming interrupt. The method also includes assigning the incoming interrupt to a selected processor core of a set of processor cores based on a current processor running state of each processor core of the set of processor cores. The current processor running state of each processor core indicates whether a respective processor core is running a routine preventing processing of the incoming interrupt.

The invention provides a method for accelerating logic-to-physical address lookup operation and a flash memory controller. The flash memory controller comprises a processor and a lookup acceleration circuit. The processor includes a plurality of processing cores. The lookup acceleration circuit comprises a message processing circuit and a logic-to-physical mapping table lookup circuit. The message processing circuitry uses the request queue to receive a request message from the processing core, and in response to detecting that a conflict occurs between a first logical address range of the incoming request message and a second logical address range in a message context corresponding to the active request message, puts the incoming request message into a conflict queue to be processed. The logic-to-physical mapping table lookup circuit looks up the logic-to-physical mapping table to convert the second logic address range into the first physical address. The message processing circuitry uses a first physical address associated with the second logical address range to perform a flash memory access operation on the volatile memory corresponding to the activity request message.

An interrupt routing method includes receiving an incoming interrupt. The method also includes assigning the incoming interrupt to a selected processor core of a set of processor cores based on a current processor running state of each processor core of the set of processor cores. The current processor running state of each processor core indicates whether a respective processor core is running a routine preventing processing of the incoming interrupt.

The application discloses a symmetric multiprocessor CPU scheduling method and device, and the method comprises the following steps: listening to whether a cache coherence event occurs in a symmetric multiprocessor system; when the cache coherence event is listened to in the symmetric multiprocessor, obtaining the process number of each CPU in all CPUs; and determining the scheduling group corresponding to the process number of each CPU according to the process number of each CPU; determining one or more thread groups of each scheduling group; for each thread group, performing a matched scheduling operation on the scheduling CPU corresponding to the thread group according to the binding time corresponding to the thread group. It can be seen that the application can reduce the cache coherence running overhead introduced when multithreading concurrently reads and writes shared data, can improve the running efficiency of the symmetric multiprocessor system, and thus improves the CPU performance of the symmetric multiprocessor system.