7 results about "Symmetric multiprocessing" patented technology

Embodiments are for processor cross-core cache line contention management. A computer-implemented method includes sending a cross-invalidate command to one or more caches based on receiving a cache state change request for a cache line in a symmetric multiprocessing system and determining a retry delay based on receiving a cross-invalidate reject response from at least one of the one or more caches. The computer-implemented method also includes waiting until a retry delay period associated with the retry delay has elapsed to resend the cross-invalidate command to the one or more caches and granting the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.

A system and method of handling interrupts in a symmetric multiprocessing system is disclosed. The symmetric multiprocessing system may comprise a plurality of ARM processors, such as Cortex-M processors. All of the possible interrupt sources are routed to all of the processing units. A message handling unit (MHU) is used to communicate between processing units to relay information about the interrupts. A MHU interrupt service routine is used to handle the enabling and disabling of the various interrupt sources, as requested by the other processing unit. The MHU interrupt service routine also tracks whether the interrupt that is to be disabled is currently executing.

This disclosure discloses a task migration method, apparatus, electronic device, and storage medium, relating to the field of computer technology, and particularly to the field of asymmetric multiprocessor systems. The specific implementation is as follows: In response to detecting an operational anomaly in an asymmetric multiprocessor system, load information of the asymmetric multiprocessor system and error information of the abnormal processor core are obtained. The asymmetric multiprocessor system includes multiple processor cores with independent memory address spaces. Based on the error information, at least one candidate processor core from the multiple processor cores and the target task to be migrated from the abnormal processor core are determined. Based on the load information, the target processor core is determined from the at least one candidate processor core. The target task to be migrated is then migrated to the target processor core.

Embodiments include an asymmetric multiprocessing (AMP) system having two or more central processing unit (CPU) clusters of a first core type and a CPU cluster of a second core type. Some embodiments include determining a control effort for an active thread group, and assigning the thread group to a first performance island according to the control effort range of the first performance island. The first performance island can include a first CPU cluster of the first core type, where a second performance island includes a second CPU cluster of the first core type, where the second performance island corresponds to a different control effort range than the first performance island. Some embodiments include assigning the first CPU cluster as a preferred CPU cluster of the first thread group, and transmitting a first signal identifying the first CPU cluster as the preferred CPU cluster assigned to the first thread group.

An interrupt routing method includes receiving an incoming interrupt. The method also includes assigning the incoming interrupt to a selected processor core of a set of processor cores based on a current processor running state of each processor core of the set of processor cores. The current processor running state of each processor core indicates whether a respective processor core is running a routine preventing processing of the incoming interrupt.

An interrupt routing method includes receiving an incoming interrupt. The method also includes assigning the incoming interrupt to a selected processor core of a set of processor cores based on a current processor running state of each processor core of the set of processor cores. The current processor running state of each processor core indicates whether a respective processor core is running a routine preventing processing of the incoming interrupt.

The application discloses a symmetric multiprocessor CPU scheduling method and device, and the method comprises the following steps: listening to whether a cache coherence event occurs in a symmetric multiprocessor system; when the cache coherence event is listened to in the symmetric multiprocessor, obtaining the process number of each CPU in all CPUs; and determining the scheduling group corresponding to the process number of each CPU according to the process number of each CPU; determining one or more thread groups of each scheduling group; for each thread group, performing a matched scheduling operation on the scheduling CPU corresponding to the thread group according to the binding time corresponding to the thread group. It can be seen that the application can reduce the cache coherence running overhead introduced when multithreading concurrently reads and writes shared data, can improve the running efficiency of the symmetric multiprocessor system, and thus improves the CPU performance of the symmetric multiprocessor system.