70 results about "Computer performance" patented technology

The invention provides a computer hardware performance evaluation method and system based on an analogue simulation model, and relates to the technical field of computer performance evaluation. According to the method, hardware component models such as a processor, a memory and I / O are constructed by analyzing a system structure description file, semantic analysis is performed on an instruction stream or a parallel computing graph of a to-be-evaluated application, and a task load model is formed. The model is input into an event-driven scheduling module, simulation is executed on the hardware component model, task-resource mapping is generated, and task time delay, communication traffic and power consumption are recorded. And calculating average response time delay, data bandwidth and unit energy consumption according to the simulation data, and outputting an evaluation report compared with the performance baseline. According to the method, real load-oriented multi-dimensional performance prediction can be realized, and the method can be used for architecture optimization and scheme selection.

In some aspects, a cloud-based computer system includes: a quantum computing system comprising a quantum processing unit; a container management and execution system configured to receive a container and execute a program within the container; and a communication channel between the container management and execution system and the quantum computing system for providing program instructions to the quantum computing system. The container management and execution system and the quantum computer system may be co-located in a data center or located in different data centers. The latency of the communication channel may be selected to optimize cost for a required computer performance.

The invention provides a computer performance dynamic adjusting system and method based on user operation behaviors, and relates to the technical field of computers. Comprising an event capture module, an operation semantic association module, a system resource optimization module and an adaptive correction module. The event capturing module obtains user operation data and generates an operation event sequence with a timestamp. The operation semantic association module is used for matching an operation event and an operation mode through a nonlinear time axis, and generating a resource demand vector in combination with a window focus and a process stack calling relationship. And the system resource optimization module selects a resource allocation scheme with the lowest power consumption on the basis of an ant colony algorithm under the condition that response time constraints are met, and reallocates resources. And the adaptive correction module adjusts the matching weight of the operation mode by comparing the deviation between the actual response time and the expected response time, and feeds back a corrected matching threshold. The system can dynamically adjust computer performance, improve response speed and reduce power consumption.

A component for improving the performance of computers using high speed memories while retaining the flexibility to install only a subset of the memories the computer can support. The component may have a blade portion configured for insertion into the mating interface of connectors forming memory sockets in the computer. The blade portion may include absorptive material selectively placed adjacent conductive elements within the connector so as to damp or prevent undesirable electromagnetic characteristics, such as stub resonances, within memory sockets that are not populated with memories. The component may have absorptive material coupled to signal and ground conductive elements of unpopulated card edge connectors and may have insulative regions that provide isolation between the absorptive material and power conductive elements. The component may be shaped for easy insertion and retention and later removal from the connector to allow a memory card to be later added to the computer.

The invention relates to the technical field of computer system performance and security testing, in particular to a computer performance security testing method and system. The method specifically comprises the steps that performance indexes, behavior characteristics and security event data of a target system are obtained in real time and subjected to standardization processing, clustering modeling is conducted on the behavior characteristics subjected to dimension reduction through a Gaussian mixture model so as to establish a normal behavior pattern cluster, and time sequence analysis is conducted on a behavior sequence in combination with a hidden Markov model so as to recognize a system state transition path; adopting a weighted combination strategy to mix and inject a normal load and an aggressive load, and adjusting an abnormal behavior chain through a disturbance function; constructing directed weighted association between the abnormal event and the performance index based on an event-driven causal performance diagram, quantifying a system risk index and triggering an alarm; outputting performance bottlenecks, security vulnerabilities and optimization suggestions, and updating the knowledge base to optimize subsequent models. According to the invention, deep coupling of performance and safety testing, intelligent scheduling of dynamic loads and interpretable positioning of risk paths are realized.

Estimated and actual processor runtimes improve computer functioning in fairly sharing computing resources. Today's computers and cloud-based services serve many users and many software applications sharing CPU resources. An operating system thus implements a scheduling policy that fairly allocates CPU time. A scheduler thread implements the scheduling policy based on estimated processor runtimes, and actual processor runtimes, associated with tasks. The operating system may maintain running tallies or totals for a user / group / organization based on credits (e.g., the estimated processor runtimes) and / or on penalties (e.g., the actual processor runtimes). The scheduler thread may select tasks for worker threads based on the credits and / or the penalties, thus ensuring that no user / group / organization unfairly consumes CPU time.

The invention relates to a system performance testing method and device, computer equipment and a readable storage medium, and relates to the technical field of computer performance testing. The method comprises the following steps: determining an initial pressure value and a test script of a to-be-tested system; testing the performance of the to-be-tested system under the initial pressure value through the test script to obtain performance index data of the to-be-tested system under the initial pressure value; increasing the initial pressure value to obtain a new pressure value, and returning to the step of testing the performance of the to-be-tested system under the initial pressure value through the test script until an iteration ending condition is met, so as to obtain performance index data of the to-be-tested system under the plurality of pressure values; and according to the performance index data under each pressure value, determining the critical pressure of the to-be-tested system entering the performance bottleneck period. By adopting the method, the test efficiency can be improved.

The present invention relates to the technical field of computer performance testing, and discloses a self-detection method for script performance testing, comprising: obtaining performance test parameters and asset server parameters of a device under test; configuring operation instructions for the asset server in the performance test parameters; running a script performance test file; causing a monitoring module and a package sending module on a performance test press to interact by running the script performance test file, and obtaining the interaction results between the monitoring module and the package sending module; calculating the resources consumed by the package sending module, and configuring and adding resources to the performance test press based on the total resource consumption of users; and recording the resource consumption of the performance test press. The present invention is used for a performance test press, so that the performance test press no longer needs to understand its own performance level in advance, directly simplifying the tester's workflow and the complexity of performance testing, improving the utilization rate of the performance test press, and lowering the threshold for performance testing.

The invention provides a plant-network-river integrated dispatching simulation calculation method and system based on parallel calculation, and the method comprises the steps: obtaining drainage facility attributes, canal plane distribution and section topography, regional digital elevation and land utilization distribution of a dispatching region, and building an SWMM model; collecting rainfall, surface runoff, and water level, flow and water quality monitoring data in the pipe duct confluence and transmission process of different sessions, and performing parameter calibration on the SWMM model to obtain a calibrated SWMM model; constructing a joint optimization scheduling algorithm model by utilizing a particle swarm algorithm, outputting a drainage facility joint regulation and control rule, inputting the joint regulation and control rule into the calibrated SWMM model, and obtaining a simulation calculation result by adopting a parallel calculation mode; and setting a scheduling rule evaluation index to evaluate the simulation calculation result, and outputting an optimal drainage facility joint regulation and control rule. According to the invention, a CPU parallel computing mode is adopted to realize analog computation of factory-network-river integrated operation scheduling, computer performance is fully exerted, and scheduling decision efficiency is improved.

The invention relates to a model rendering method, a surgery simulation method and a computer readable storage medium, and the method comprises the steps: responding to the interaction between a user and a data model, and determining a user attention region in the data model, the data model comprising voxel data and grid data associated with a preset region of interest; and rendering at least one part of the data model based on the voxel data and the grid data according to the user attention area to obtain a target rendering result. By adopting the method, the reality sense of operation simulation can be improved, and meanwhile, the computer performance requirement required by operation simulation is reduced.

Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and / or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

The application belongs to the technical field of computer control, and discloses a notebook computer intelligent heat dissipation control system based on a multi-modal sensor, which comprises the following steps: collecting multi-modal thermal sensing data of a notebook computer; identifying a current running scene type and obtaining user heat dissipation preferences based on the multi-modal thermal sensing data; calculating a thermal trend index of each hardware component of the notebook computer according to historical multi-modal thermal sensing data and the current running scene type; generating a heat dissipation regulation scheme with scene adaptability based on the thermal trend index, the current running scene type and the user heat dissipation preferences; and realizing notebook computer intelligent heat dissipation control in a progressive regulation mode according to the heat dissipation regulation scheme, so that the stability of the notebook computer performance is greatly improved and the hardware service life is prolonged.

The embodiment of the invention provides a memory super-division processing method and system, the memory super-division processing method is applied to a host machine, the host machine runs a plurality of virtual machines, and the method comprises the following steps: determining missing page state data of the plurality of virtual machines in a first historical time period; determining performance loss results of the plurality of virtual machines according to the missing page state data; according to historical cold page data of the multiple virtual machines in a second historical time period, predicted cold page data of the multiple virtual machines in the future time period is determined, the duration of the second historical time period is smaller than or equal to that of the first historical time period, and the duration of the second historical time period is the same as that of the future time period; according to the performance loss result and the predicted cold page data, determining memory super-resolution indexes of the plurality of virtual machines in the future time period; according to the method, the page replacement pressure and the address conversion pressure of the virtual machine are reduced, the performance reduction probability of the host machine is reduced, and the stability of the memory and operation of the host machine is improved.

The invention discloses a computer performance real-time evaluation method and device based on user experience perception, a storage medium and computer equipment, and the method comprises the steps: obtaining the current operation data of the computer equipment, carrying out the use scene recognition based on the current operation data, and determining a current use scene; obtaining a plurality of user experience perception performance indexes corresponding to the current use scene and the index weight of each user experience perception performance index in a pre-constructed use scene and user experience perception performance weight mapping table; performing performance index data acquisition on the computer equipment according to each user experience perception performance index, and calculating a comprehensive performance score of the computer equipment according to each acquired user experience perception performance index data and the corresponding index weight; and performing real-time performance feedback of the computer equipment according to the comprehensive performance score.

The invention discloses a game CPU-oriented model identification method and system, and belongs to the technical field of computer performance optimization, and the method comprises the following steps: S1, collecting a real-time performance vector from a CPU core performance monitoring unit; S2, obtaining a predictive load vector from a game engine; s3, adjusting the dynamic learning rate based on the change degree of the predictive load vectors at the current moment and the previous moment; s4, calculating an instantaneous matching degree for each candidate model in a preset candidate CPU micro-architecture model set based on the real-time performance vector, the predictive load vector and a preset reference performance matrix associated with the candidate model; and S5, updating and generating a dynamic confidence score for each candidate model in combination with the confidence, the instantaneous matching degree and the dynamic learning rate of the previous moment, and winning a precious time window for predictive performance optimization of a game engine.

The application belongs to the technical field of computer hardware testing, and discloses a multi-sensor integrated detection dock system for notebook computer performance testing, which comprises a multi-sensor module, a data acquisition and interface module, a main control module and a hardware component. The application has the following remarkable advantages: high integration and improved efficiency; data synchronization precision and improved analysis value; high automation degree and reduction of human error; consistent test conditions and strong result comparability.

The present application provides a map data processing method, device, electronic device, and storage medium. The method includes: determining the distance between each grid node in the first-level grid of the map and the viewing position; determining whether the grid node is an aggregatable node based on the distance between each grid node in the first-level grid and the viewing position; if so, displaying a target aggregation point at the location of the aggregatable node on the map; if not, obtaining each grid subnode of the grid node, and displaying the target aggregation point or obtaining the next-level grid subnode of the grid subnode based on the distance between the grid subnode and the viewing position, and looping through these steps until the current grid subnode is the last-level grid subnode. The method can calculate aggregated content by determining the distance between the grid node and the viewing position, thereby reducing computing pressure, lowering computer performance loss, and avoiding lag issues during rendering.

This invention discloses a computer performance data acquisition method and system, relating to the field of computer data processing technology. Based on the load prediction value Ldp, the system automatically adjusts its operating rhythm. When the device is under high pressure, the sampling adjustment coefficient Frs is suppressed due to the increase in the acquisition overhead value Coi, thereby dynamically lengthening the sampling interval Del, thus preventing the acquisition behavior from exacerbating congestion. When the device is idle, the processing utilization Cpuu, memory utilization Memu, and thread switching rate Ths remain at low values, and the load prediction value Ldp derived from the trend base value Tbs and the acquisition overhead value Coi is low, causing the sampling interval Del to be actively shortened. This allows for early capture even when the user is not operating but background programs are gradually increasing. Traditional fixed-frequency acquisition methods often fail to identify performance degradation inflection points in a timely manner, while the continuous accumulation of the trend base value Tbs triggers an increase in the sampling frequency at an early stage.

The invention discloses a performance monitoring method and device for an image-text mixed data set, a storage medium and a product, and relates to the technical field of computer performance monitoring, the method is applied to a client, the client comprises a to-be-monitored browser, and the method comprises the steps that in response to a starting instruction of running an image-text mixed data set page by the browser, the image-text mixed data set page is started; collecting a performance log when the browser runs the image-text mixed data set page; the collected performance logs are uploaded to a server in batches, so that the server analyzes the performance logs to obtain a performance analysis result of the browser, and a corresponding optimization strategy is determined based on the performance analysis result; and obtaining an optimization strategy, and adjusting the operation mode of the browser and the display parameters of the image-text mixed data set based on the optimization strategy. According to the method and the device, the performance of the browser for processing the image-text mixed data set can be monitored, so that the performance of the browser is improved.

The present invention belongs to the technical field of computer performance detection, and specifically relates to a computer performance detection device, including a base; two columns are fixedly connected to the top of the base; mounting disks are installed above both of the two columns; turntables are provided on the opposite sides of both of the two mounting disks, and the turntables are respectively rotatably arranged on the adjacent mounting disks; a first motor is fixedly connected to the mounting disk, and the first motor is used to drive the mounting disk; two pairs of opposite L-shaped plates are fixedly connected to the upper and lower sides of both of the two turntables; a first convex groove is formed on the turntable between the two L-shaped plates; electric push rods are fixedly connected to the opposite end faces of the two L-shaped plates located on the turntable, and the extending rods of the electric push rods extend to the opposite sides of the two L-shaped plates; two clamping assemblies are arranged between the two turntables, and the clamping assemblies include a first clamping assembly and a second clamping assembly; by providing the detection device, the states of a laptop computer falling under different conditions can be simulated.

The present invention proposes an efficient application performance monitoring and prediction method based on the Anolis OS, belonging to the field of computer performance technology. First, a basic model architecture is defined, and pre-trained using the gwa-t-12-bitbrains dataset. After obtaining the pre-trained model, it is exported as an onnx model and embedded with a data prediction plugin, which is managed by the plugin manager. A data collection plugin based on pidstat and Prometheus is developed to obtain the real data of local application processes. On the one hand, the data is stored in a time series database for convenient subsequent model training and invocation. On the other hand, after data processing, it is transmitted to the data prediction plugin to evaluate the prediction effect for further improving the prediction model. Finally, a data visualization page is developed, and at the same time, the plugin manager is improved to add a data pipeline function to integrate plugins such as data collection and data prediction. The entire application framework is organized to facilitate the expansion of application functions and adapt to the monitoring and prediction requirements in different scenarios.

Techniques to help reduce latency and improve computer performance including managing latency between client computers over a network with server computers including determining configurable time period, communicating quote data to client computers, determining most recent quote data from a cache and determining whether to execute quote data based on quote version data and time data associated with the quote data and based on the configurable time period.

The invention relates to the technical field of computer performance evaluation, and discloses a three-valued optical computer performance and energy consumption balancing method based on partial synchronous vacation, which introduces a partial service desk synchronous vacation strategy and constructs a three-stage service model comprising task input, core calculation and result output. Key performance indexes such as the average queue length and the average waiting time of each stage are obtained, so that the optimal balance point between the performance and the energy consumption is obtained, and a social utility function comprehensively considering the system performance and the energy consumption is constructed by introducing Nash equilibrium and a social optimal strategy; the three-valued optical computer is controlled to be at an optimal balance point between performance and energy consumption through an operation result, so that low energy consumption is ensured while high performance is achieved.

The invention discloses an industrial personal computer performance acquisition method and terminal based on a third-party control, and the method comprises the steps: firstly judging whether a to-be-acquired industrial personal computer is a local terminal or not, and then automatically selecting a mode of direct calling or remote calling based on a secure shell protocol to acquire the performance; and a third-party control interface is uniformly called to realize efficient acquisition of hardware performance of the industrial personal computer, so that an optimal calling path is automatically selected in a local scene and a far-end scene. Compared with a traditional mode of directly reading the system file, the method has the advantages that a Linux kernel file structure does not need to be deeply analyzed; a key pair is configured between a local industrial personal computer and a to-be-acquired industrial personal computer in advance, and cross-industrial-personal-computer and cross-network remote acquisition is realized by using a secure shell protocol SSH, so that the safety and reliability of cross-computer performance data acquisition are improved. In conclusion, the method obviously improves the efficiency, accuracy and maintainability of performance acquisition of the industrial personal computer.

The invention discloses a computer performance detection method and system based on artificial intelligence and a medium, and the method comprises the steps: obtaining a utilization rate of a CPU of a to-be-detected computer in a preset detection period, and determining a temperature coefficient of the CPU based on the utilization rate; if the temperature coefficient belongs to a risk coefficient, determining a first temperature of the CPU based on a preset network model, and obtaining a reference temperature interval corresponding to the CPU; determining a to-be-cooled temperature according to the reference temperature interval and the first temperature, and obtaining a cooling duration corresponding to the to-be-cooled temperature; and after the heat dissipation element operates for the heat dissipation duration, detecting a second temperature of the CPU, and detecting the heat dissipation performance of the to-be-detected computer according to the second temperature. The first temperature is determined through the preset network model in combination with various factors of the environment where the CPU is located, so that the first temperature accurately reflects the actual temperature of the CPU, the determined to-be-cooled temperature and the cooling duration are more accurate, and the cooling performance detection accuracy of the to-be-detected computer is improved.

The invention discloses a user-friendly brain-computer interface system, and relates to the technical field of brain-computer interfaces. The system comprises a stimulation presentation module, a signal acquisition module, a signal processing module and a signal decoding module. The stimulus presentation module is used for presenting static color block stimulus at different positions on the display equipment; the signal acquisition module is used for acquiring scalp surface electroencephalogram signals when a user watches a color block; the signal processing module adopts a TRCA algorithm to carry out signal-to-noise ratio enhancement on the electroencephalogram signals, and an electrode channel weight coefficient is obtained by solving a target function; the signal decoding module adopts a Manhattan distance method to describe electroencephalogram signal characteristic differences stimulated by different color blocks. Visual fatigue is remarkably reduced, decoding performance is stable, color combination is visual, and requirements for different control instruction numbers can be flexibly met; static color block stimulation does not need to occupy a large number of computing resources, the high requirement of traditional flicker stimulation for computer performance is met, and the method is suitable for more hardware environments.

Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and / or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and / or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

The application relates to a CPU performance test method and application under a Conda environment, belongs to the field of computer performance evaluation and optimization, and realizes comprehensive evaluation of CPU performance in combination with LAMMPS and LLCBench tools. The method quickly builds a test platform through the Conda environment, can evaluate the computing performance and parallel processing capability of the CPU by using LAMMPS, and can test the bandwidth and delay characteristics of CPU caches (L1, L2 and L3) through LLCBench. In combination with the two tools, the method realizes comprehensive testing of the computing performance and cache performance of the CPU, has the advantages of high efficiency, repeatability and wide application range, and provides scientific support for hardware performance evaluation and optimization.

Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and / or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.