136 results about "Cache coherence" patented technology

The invention relates to the technical field of power monitoring system network security and real-time micropatch hot deployment, and discloses a power disaster recovery system-oriented micropatch non-inductive deployment engine, a resource scheduling method, a system, equipment and a medium, and the method comprises the steps: capturing system events through a kernel eBPF probe, and carrying out feature extraction and model reasoning; generating and transmitting an encrypted scheduling token; loading and verifying a patch fragment by a patch agent, inserting a jump instruction through a kernel interface to redirect an execution stream, and maintaining multi-kernel cache consistency; fusing multi-source telemetry data to carry out fusing judgment, realizing network isolation and calling a key service to cancel a key; and collecting runtime indexes and performing trend prediction, triggering a recovery or rollback operation according to a result, and storing an operation result and data through a block chain. According to the method, through combination of deep fusion of multi-source heterogeneous data, dynamic reasoning of a knowledge graph and strategy optimization of reinforcement learning, efficient perception and defense of a complex attack scene of a digital power grid are realized.

According to the read transmission bridging device and method for the AXI master device and the CHI request node, the master device which does not support cache consistency can be interconnected with a CHI bus to perform read transmission and maintain the cache consistency and address allocation of the whole system under the condition that the design is not modified, and the device has good compatibility, conforms to a standard AXI4 protocol and a standard CHI protocol, and is convenient to use. And the device maintains the cache consistency in the system, ensures the data consistency when the master device accesses the shared data, and avoids errors caused by non-updating of the cache or conflicts. According to the read transmission bridging device of the AXI master device and the CHI request node, the AXI master device is connected to the request node of a CHI bus, a central processing unit (CPU) is connected to the request node of the CHI bus, and an external device and a memory are connected to a completion node of the CHI bus.

The invention relates to a modeling and formalized verification method for cache consistency protocol verification, and the method comprises the steps: building a protocol model which comprises a plurality of processor nodes, directory nodes and a communication mechanism through a structured modeling mode, and constructing an asynchronous message mechanism to simulate disordered concurrent communication; protocol behavior rules such as processor requests, directory responses and network receiving are defined, protocol property invariants are set, semantic constraints such as data consistency, confirmation before writing and sharing state legality are covered, model verification is carried out in a state space traversal mode, breadth-first search and a symmetry recognition mechanism are supported, and the method is suitable for the protocol behavior rules. A protocol error or deadlock state is effectively found, a traceable error path is generated, a verifier can automatically generate source codes through a compiler and operate on a host platform, and rapid verification and result output of a protocol model are achieved. The method has good protocol adaptability and model reusability, and is suitable for formalized verification of various cache consistency protocols.

The invention discloses a data transmission optimization method and system in hybrid deployment of a real-time system and a non-real-time system based on Jailhouse, belongs to the technical field of data transmission, and solves the problems of low data transmission efficiency, high copy overhead, lack of universality of interfaces and the like in an existing system. Comprising the steps that a hybrid deployment platform including a real-time system and a non-real-time system is built on a multi-core processor platform, and the hybrid deployment platform runs in an isolation environment of a Jailhouse partition manager; building an abstract transmission interface layer as a unified channel for accessing a shared memory by a real-time system and a non-real-time system; establishing a plurality of shared memory channels in the abstract transmission interface layer and scheduling according to the priority of tasks; establishing a data transmission path, and compressing a memory copy operation into one time by adopting a memory mapping multiplexing technology and a DMA (Direct Memory Access) collaboration mechanism; and a cache consistency maintenance technology is adopted, so that the data consistency is ensured, and the optimization of data transmission is completed. The method is suitable for application scenes such as industrial automation, intelligent connected automobiles and edge calculation.

The invention discloses a circuit, a data processing method, equipment, a medium and a program product in the technical field of computers. In the application, the three-dimensional heterogeneous computing body layer can adapt to diversified computing power requirements, and is beneficial to realizing higher routing and higher data transmission efficiency between nodes. The shared cache layer is beneficial to realizing cache consistency of different heterogeneous computing nodes, and the cache utilization rate is improved. The internal interconnection module and the external interconnection module provided by the interface layer are easy to realize internal and external efficient communication. A first channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the three-dimensional heterogeneous computing body layer and direct connection of physical channels between the control layer and the shared cache layer; a second channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the interface layer; therefore, the communication delay between different levels can be reduced, the data transmission efficiency between different levels can be improved, and a high-bandwidth application scene can be met.

The invention discloses an interface conversion device and circuit, electronic equipment and an interface conversion method, and relates to the technical field of computer system structures. Extracting a cache or memory transaction request from the first preset interface signal through a channel processing module, generating consistency transaction information, sending the consistency transaction information to a consistency transaction concurrent processing module, receiving response data of the consistency transaction concurrent processing module, and packaging the response data into a second preset interface signal; the consistency transaction concurrent processing module carries out processing according to the received consistency transaction information to obtain a concurrent signal; and the interface conversion module decodes and converts the concurrent signal into a first target protocol control signal, and / or converts the authorized transaction into a second target protocol control signal. Therefore, concurrent analysis, consistency transaction mapping and direct conversion are carried out on a multi-channel protocol through a configurable modular hardware architecture, and high-concurrency and low-delay protocol conversion and cache consistency maintenance between an inter-chip consistency interconnection protocol and an on-chip bus protocol are realized.

The invention discloses an Ethernet-based distributed cache coherence protocol, an implementation method, an implementation device and an implementation system. A plurality of computing nodes are connected through a packet switching network. Each computing node comprises a CPU / GPU (Central Processing Unit / Graphics Processing Unit) and a local cache thereof, and is provided with a cache agent. The far-end memory is organized in home nodes, and each home node manages a part of physical address space and is equipped with a directory controller. When the CPU of the computing node accesses a far-end memory address and does not hit in the local cache, the CA of the computing node replaces the far-end memory address and communicates with the DC managing the address through the network so as to maintain the cache consistency of the data among all the nodes. Based on a cache consistency protocol of a directory, the CXL.cache consistency of a plurality of independent computing nodes can be maintained in a low-overhead and high-reliability mode on a high-delay and lossy packet switching network, and broadcast storm caused by a monitoring protocol is avoided.

A system for managing cache coherency comprises memory areas, processing cores, cache nodes each associated with at least one of the processing cores, and a hardware processor configured to: for each of the memory areas: cluster the processing cores into clusters according to memory access metrics in relation to the memory area; and for each of the clusters, associate the memory area with a caching scheme; and configure the processing cores to: receive from a first core a memory access command comprising a memory address associated with a memory area, where the first core is a member of a first cluster for the memory area; compute a determination of a target cache node according to the memory access command, where the target cache node is associated with a second core; and access the memory area according to the caching scheme associated with the memory area for the first cluster.

The invention discloses a low-delay interrupt processing method and system of an intelligent control center, and belongs to the field of industrial control computer system architecture. The method comprises the following steps: analyzing an interrupt request to obtain an event type identifier; based on a predefined event priority mapping table, matching the event priority into a corresponding interrupt priority; selecting a path from a pre-allocated and physically isolated hardware response path set according to the interrupt priority; distributing the interrupt request and the context data to a pre-bound processing core through the selected path; and the processing core executes the preloaded simplified processing routine to generate a driving instruction. Through combination of event semantic mapping and physical isolation hardware paths, a deterministic low-delay response channel is provided for core emergency interrupt, system reliability is improved through a load balancing mechanism based on cache consistency, the problem of large delay jitter of high-concurrency interrupt processing of an industrial intelligent control center is effectively solved, and the system reliability is improved. And the real-time performance of the control system is obviously improved.

Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions

The invention discloses a control system supporting concurrent access of multiple hosts, a storage device and a medium, and relates to the technical field of data storage, the system runs on a control module externally connected with the storage device, and the system comprises a communication connection management unit used for establishing connection with multiple hosts through at least two host interfaces; the access request receiving unit is used for receiving access requests sent by different hosts through an uplink port of the multi-host switching chip, and the access arbitration and scheduling unit is used for carrying out real-time arbitration and unified scheduling on the requests according to a preset strategy; and the instruction forwarding and execution unit forwards an arbitrated instruction to the storage unit for execution through a downlink port, and the system further integrates a cache consistency management unit, a configurable arbitration strategy unit, a multi-mode storage space management unit and the like, so that the data consistency, the access efficiency and the system reliability during multi-host concurrent access are ensured. According to the scheme, efficient and safe parallel access of a plurality of hosts to a single storage device is realized.

The invention discloses a maintenance, recording and transmission method, device and equipment for cache consistency, and the recording method comprises the steps: responding to a first processing unit in a processing unit array to cache a first data block, and obtaining a first position coordinate of the first processing unit in the processing unit array, the first coordinate comprises a plurality of values respectively corresponding to a plurality of dimensions of the processing unit array; according to the first coordinate data, a first directory entry corresponding to the first data block in the cache consistency directory is updated, the first directory entry comprises a plurality of arrays corresponding to a plurality of dimensions, and in the first directory entry, the first data block corresponds to the first directory entry; the array corresponding to each dimension is used for marking dimension coordinates of the processing unit which caches the first data block on the dimension. The recording method can reduce the directory capacity.

According to the writing transmission device and method for the CHI bus protocol system and the AXI4 equipment, main equipment which does not support cache consistency and a CHI bus are interconnected for writing transmission under the condition that design is not modified, the cache consistency and address allocation of the whole system are maintained, the data consistency when the main equipment accesses shared data is ensured, and the reliability of the system is improved. And errors caused by non-updating of the cache or conflicts are avoided. The device receives a write command sent by AXI4 equipment, and converts the write command into various types of write requests of a CHI protocol; comparing the write addresses sent by the AXI4 device with the addresses in the address mapping table one by one, and after the comparison is successful, obtaining a destination identification code corresponding to the cache line; the transmission identification codes are gradually increased in a transmission command by the device, judging whether the transmission identification codes are a main memory or a cache, and determining a command identification code, a cache attribute and a monitoring attribute according to the main memory and the cache; when the total transmission amount is smaller than or equal to 64 bytes, the size in the request command packet is the actual total transmission amount.

A cache memory subsystem includes virtually-indexed L1 and PIPT L2 set-associative caches having an inclusive allocation policy such that: when a first copy of a memory line specified by a physical memory line address (PMLA) is allocated into an L1 entry, a second copy of the line is also allocated into an L2 entry; when the second copy is evicted, the first copy is also evicted. For each value of the PMLA, the second copy can be allocated into only one L2 set, and an associated physical address proxy (PAP) for the PMLA includes a set index and way number that uniquely identifies the entry. For each value of the PMLA there exist two or more different L1 sets into which the first copy can be allocated, and when the L2 evicts the second copy, the L1 uses the PAP of the PMLA to evict the first copy.

The invention provides a cache consistency test method and device, electronic equipment and a computer readable storage medium. The method comprises the steps of obtaining a test sequence of a multi-core cache system; the multi-core cache system comprises at least two processor cores and a multi-level cache. The test sequence comprises an operation instruction for each processor core; inputting the test sequence into the simulation model, processing the test sequence in sequence through multi-stage caches of the simulation model according to a cache coherence protocol, and outputting a state check point of the multi-core cache system; the state check point is used for representing the current cache state of each processor core in the multi-core cache system; and testing the cache consistency of the multi-core cache system according to the state check point to obtain a test result. According to the embodiment of the invention, the reliability and comprehensiveness of the cache consistency test can be improved.

The present invention relates to the field of computers. Disclosed are a method for adaptively and jointly using cache coherence directory entries, and a computer program product. The method comprises: in response to a read request of a processor core, acquiring a first entry set corresponding to a cache; when there is an available entry in the first entry set, storing ID information of the processor core in the available entry; when there is no entry in the first entry set or there is no available entry in the first entry set, applying for a new entry and storing the ID information in the new entry; in response to a write request of the processor core, acquiring a second entry set corresponding to the cache; determining corresponding processor cores on the basis of ID information stored in entries in the second entry set, and controlling each processor core to execute an operation of invalidating a copy of the cache; and enabling the second entry set to only comprise one entry, and storing the ID information in the entry. The directory capacity is fully utilized and snoop operations for all processor cores can be reduced.

Cache memory systems employing a multi-level hierarchy cache coherency architecture, and related methods and computer readable media. A processor-based system includes multiple independent dies, each die having a processor and a local cache memory that logically forms part of a global cache memory in a system address space. To provide single point cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point cache coherency in the global cache memory. Thus, a single point cache coherency protocol can be implemented. However, the proxy cache controller circuits can also be able to locally service memory requests within their own die only, to provide lower latency memory transactions, while still being able to maintain cache coherency.

Computing systems and methods for performing remote direct memory access in a computing system are provided. In some embodiments, the system includes a storage program processing circuit, a network interface circuit, a cache coherence switch, and a first memory module. In some embodiments, the first memory module is connected to the cache coherence switch, the cache coherence switch is connected to the network interface circuit, and the storage program processing circuit is connected to the cache coherence switch.

The invention discloses a concurrent data processing method and a related device, and the method comprises the steps: responding to a deletion request for an original data record in a memory stable region, and enabling an Owner Entity to use a write instruction of a preset mechanism to carry out the state marking of whether the original data record is in a deletion state or not on the original data record; the Sharing Entity reads the original data record in the memory stable region by using a read instruction of a preset mechanism, and the read original data record is preprocessed and then sent to the Owner Entity; and the Owner Entity finds out an original data record corresponding to each preprocessed data record in the memory stable area according to the data record identifier, and rechecks a state marking result of the found original data record. Wherein the read-write instruction does not use any synchronous primitive, atomic operation and the like according to a preset mechanism, so that the cache consistency flow generated by the read operation can be avoided from the source, the problems of pipeline pause and blockage on a read-write path are eliminated, and the business processing efficiency and the data synchronous updating effect are improved.

Embodiments of the present application relate to the technical field of computers, and provide a remote data processing method, an apparatus, and a computing device, capable of improving the efficiency of remote data processing. The method is applied to a first device, and the first device remotely communicates with a second device. The method comprises: receiving an operation request for data to be processed sent by the second device, the operation request comprising: a read request or a write request; in response to the operation request, when a preset condition is satisfied, performing, on the data to be processed, an operation indicated by the operation request, the preset condition being used for indicating that the data to be processed is in a cache coherence state; and in response to the operation request, when the preset condition is not satisfied, performing an invalidation operation on the data to be processed, the invalidation operation being used for invalidating the data to be processed in a replica device, the replica device being a device that caches the data to be processed.

The application provides a multi-operation system based on an isomorphic multi-core, a communication method thereof and a chip. The multi-operation system comprises at least a first operation system and a second operation system, and the first operation system and the second operation system are located in different cores of the same processor. The communication method comprises the following steps: monitoring a first data write operation; updating the first data to a cache unit of the second operation system by the first operation system through a cache consistency mechanism; monitoring that the first data write operation is completed; sending a shared notification to the second operation system by the first operation system; and obtaining the first data from the cache unit by the second operation system after receiving the shared notification. In this way, the efficiency of data synchronization between operation systems can be improved.

The invention discloses a graphics processor, a cache data sharing method, equipment, a medium and a program product, and relates to the technical field of processors, first-level caches in one-to-one correspondence with computing cores are arranged, and pairwise communication links between the first-level caches and a central label buffer area are constructed through an interconnection interface unit; in cooperation with a global label table recording label information of all first-level cache data blocks, when a first-level cache receives a data reading request of a connected computing core and a target data block is not stored locally, other first-level caches where the target data block is located can be positioned through a central label buffer area; direct data transmission between first-level caches is achieved through the interconnection interface unit without relying on second-level cache transfer, the access pressure of the second-level caches is reduced, the bandwidth bottleneck problem is solved, the data transmission path is shortened, the data access delay is reduced, complex design brought by a traditional cache consistency protocol is avoided, the cache resource utilization rate is increased, and the data transmission efficiency is improved. And the overall operation performance of the graphics processor is optimized.

The application discloses a kind of underwater acoustic communication sending control method and system, applied to the processor with multi-level storage and cache architecture.The method allocates double-buffered storage space in advance in physical storage area;Water acoustic communication data is handled to generate time domain digital signal sequence by multi-carrier digital modulation;In response to the filling completion state of data to the first buffer, cache coherency synchronization operation is performed to write the latest data in the cache of the processor back to the physical storage area;Subsequently trigger the hardware data carrying engine independent of kernel, and send data through external interface;During data carrying, fill the subsequent generated data to the idle second buffer.The application solves the problem of memory access conflict and data transmission break under high sampling rate through multi-level storage isolation and software and hardware collaborative zero-copy pipeline mechanism, and guarantees the high quality, high continuity sending of OFDM underwater acoustic signal.

A method includes receiving a first request to allocate a line in an N-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. The method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly selecting one of the ways in the set. The method also includes, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocating the selected way for the first request.

In the described example, the coherent memory system includes a central processing unit (CPU) and level 1 and level 2 caches. The CPU is configured to execute program instructions (1000) to manipulate data in at least a first or second security context. Each of the first and second caches stores (e.g., 1050) a security code indicating the at least first or second security context through which data of a corresponding cache line is received. The level 1 and level 2 caches maintain coherence by comparing (1020) the security code of the corresponding cache line and performing a cache coherence operation (1030) in response.

The invention provides a multi-core processor cache coherence communication system based on FreeRTOS, and relates to the field of computer embedded systems, and the system comprises an application layer which comprises a plurality of tasks and is used for completing cross-core data interaction; the cache consistency communication layer is in communication connection with the application layer and the kernel layer; the cache consistency communication layer comprises a shared memory management module, a cache synchronization strategy scheduling module and a communication component synchronization adaptation module; the shared memory management module is used for tracking the cache state of the shared memory; the cache synchronization strategy scheduling module is used for selecting an optimal cache synchronization strategy according to the task and is linked with the task scheduler; the communication component synchronization adaptation module is used for identifying a corresponding shared memory block; the kernel layer comprises a memory manager, a task scheduler and a communication component; the communication component comprises queues, semaphores and event groups. According to the scheme, the problem of cache inconsistency is solved, and the correctness of cross-core data is ensured.

The invention discloses a data multi-level cache collaborative acceleration method and system, and mainly relates to the technical field of data cache acceleration. Comprising the steps of obtaining data access features and inputting a model fusing sliding window statistics and exponential decay to calculate a dynamic heat value; dynamically scheduling the data to a high-speed memory, a distributed sharing or a local file cache level according to the heat value; optimizing a cross-level query path based on the intelligent routing model; the multi-level cache consistency is maintained by adopting an asynchronous version control mechanism; executing hierarchical collaborative cleaning and elastic capacity expansion according to the real-time popularity and the capacity utilization rate; and realizing hot data preloading by utilizing the prediction model. The method has the beneficial effects that through intelligent scheduling and collaborative optimization, the cache hit rate and the system throughput are remarkably improved, the access delay and the storage cost are reduced, and the stability and the data consistency under high concurrency are enhanced.

The invention discloses a cache coherence interconnection method, a cache coherence node and a multiprocessor system, relates to the field of computers, and provides the cache coherence interconnection method for solving the problems that a traditional cache coherence interconnection module is large in hardware resource overhead and insufficient in flexibility. Analyzing the memory access request to determine a source identifier; the source identifier is a unique identifier corresponding to a source processor of the memory access request sender; generating a monitoring address frame which carries the source identifier and corresponds to the memory access request, and sending the monitoring address frame to other processors through the interconnection module; after the monitoring data load returned in response is received, the memory access request is completed according to the monitoring data load. The method can get rid of dependence on complex structures such as directories, the cache consistency function can be achieved by using fewer hardware resources, decoupling between the cache consistency function and an interconnection structure can be achieved, and application of the cache consistency function is more flexible.

The present application relates to the technical field of multi-core heterogeneous computing, and discloses a storage coherent hub chip based on core integration, a storage coherent arbitration device and an adaptive control method, aiming to solve the technical problems of high cross-core memory access latency, low coupling degree of cache coherence maintenance and memory scheduling, and slow response of operation strategy adjustment under the existing multi-core architecture. The present application takes an independently packaged storage coherent core as a globally consistent unique maintenance node, integrates a single-cycle static addressing architecture, adopts a cache coherence state machine and a memory scheduling controller with deep fusion of logic layers, realizes automatic switching between robust mode and aggressive mode through a pure hardware MHM monitoring unit, and the atomic withdrawal process is transparent to the upper layer. The present application can reduce the cross-core memory access latency by more than 40%, improve the storage access throughput by 25%, while guaranteeing 99.999% operation reliability, adapting to various heterogeneous interconnection protocols, and being applicable to various application scenarios such as servers, high-frequency financial transactions, AR / VR wearable devices, edge computing, etc.