197 results about "Cache coherence" patented technology

A system for adaptively caching network communication protocols provides improved efficiency and performance through a multi-level cache architecture. The system monitors performance metrics and synchronizes cache contents across distributed nodes using a hierarchical structure. Protocol cache requirements are predicted based on usage patterns, enabling proactive cache management. The system compresses cached protocols using existing codebooks to optimize storage and transmission efficiency. Integration with event-driven data communication systems enables seamless protocol selection and translation. The caching system works in conjunction with transaction managers and protocol predictors to enhance network communication performance. The system maintains cache coherency across local, regional, and global cache levels while minimizing network overhead and optimizing protocol availability. By predicting and pre-caching likely needed protocols, the system reduces protocol negotiation latency and improves overall network communication efficiency.

The invention discloses a heterogeneous computing system, a cache consistency maintenance method and device, equipment and a medium, and relates to the technical field of heterogeneous computing. The method comprises the step of redefining a cache coherence protocol of the heterogeneous computing system as a metadata index protocol, a multicast synchronization protocol and a hybrid response protocol. Entropy weights of different feature dimensions are determined according to feature values of all data blocks of the heterogeneous computing system, and a protocol most matched with the task load running state at the current moment is determined from a metadata index protocol, a multicast synchronization protocol and a mixed response protocol according to the entropy weights of the different feature dimensions; and determining whether to switch the protocol according to whether the current protocol is consistent with the selected protocol. According to the method, the problem that the protocol cannot be effectively optimized in related technologies can be solved, and the consistency protocol which is most matched with the current task load of the heterogeneous computing system can be accurately determined.

The invention relates to the technical field of power monitoring system network security and real-time micropatch hot deployment, and discloses a power disaster recovery system-oriented micropatch non-inductive deployment engine, a resource scheduling method, a system, equipment and a medium, and the method comprises the steps: capturing system events through a kernel eBPF probe, and carrying out feature extraction and model reasoning; generating and transmitting an encrypted scheduling token; loading and verifying a patch fragment by a patch agent, inserting a jump instruction through a kernel interface to redirect an execution stream, and maintaining multi-kernel cache consistency; fusing multi-source telemetry data to carry out fusing judgment, realizing network isolation and calling a key service to cancel a key; and collecting runtime indexes and performing trend prediction, triggering a recovery or rollback operation according to a result, and storing an operation result and data through a block chain. According to the method, through combination of deep fusion of multi-source heterogeneous data, dynamic reasoning of a knowledge graph and strategy optimization of reinforcement learning, efficient perception and defense of a complex attack scene of a digital power grid are realized.

Mechanisms for unordered input / output direct memory access operations are provided, including: issuing using a hardware processor a back invalidate snoop request to a cache coherency control unit of a host processor; and issuing an unordered input / output direct memory access operation request to a Compute Express Link memory device. In some of these mechanisms, the unordered input / output direct memory access operation request is for a read operation. In some of these mechanisms, the mechanisms further comprise receiving a response to the unordered input / output direct memory access operation request including data from the Compute Express Link memory device. In some of these mechanisms, the data was updated in response to the back invalidate snoop request. In some of these mechanisms, the unordered input / output direct memory access operation request is for a write operation.

According to the read transmission bridging device and method for the AXI master device and the CHI request node, the master device which does not support cache consistency can be interconnected with a CHI bus to perform read transmission and maintain the cache consistency and address allocation of the whole system under the condition that the design is not modified, and the device has good compatibility, conforms to a standard AXI4 protocol and a standard CHI protocol, and is convenient to use. And the device maintains the cache consistency in the system, ensures the data consistency when the master device accesses the shared data, and avoids errors caused by non-updating of the cache or conflicts. According to the read transmission bridging device of the AXI master device and the CHI request node, the AXI master device is connected to the request node of a CHI bus, a central processing unit (CPU) is connected to the request node of the CHI bus, and an external device and a memory are connected to a completion node of the CHI bus.

The invention discloses a heterogeneous computing system, a cache consistency maintenance method and device, equipment and a medium, and relates to the technical field of heterogeneous computing. The method comprises the following steps: determining a hotspot data access path at the current moment according to an access sequence and dependency relationship strength of each data block of the heterogeneous computing system at the current moment; generating current running state information according to the hotspot data access path, the workload information of the heterogeneous computing system at the current moment, the cache effective information and the cross-device communication information; and based on the relationship between the running state of the heterogeneous computing system and the cache coherence protocol type, determining the cache coherence protocol most matched with the current running state of the heterogeneous computing system according to the current running state information. According to the method, the problem that the cache consistency protocol cannot be effectively and dynamically optimized in related technologies can be solved, the cross-device data dependency relationship can be dynamically captured, the dynamic change can be accurately sensed, and the high performance and data consistency of the system can be ensured.

The invention provides a unified memory system based on heterogeneous computing, belongs to the field of parallel computing and artificial intelligence, and realizes memory sharing by constructing a global virtual address space and eliminating explicit data transmission between a host end and an equipment end. The core module comprises: 1) a cache consistency manager, which adopts an adaptive protocol (write broadcast / write invalidation) and a cache directory table (CCDT) to ensure data consistency; 2) an MMU memory management unit which supports dynamic address translation, on-demand distribution and page migration; and 3) an intelligent data migration unit which dynamically migrates the hotspot data to a near-end memory based on the prediction model and reduces the access delay. The architecture is suitable for edge AI applications with high requirements on real-time performance and energy efficiency.

The invention relates to a modeling and formalized verification method for cache consistency protocol verification, and the method comprises the steps: building a protocol model which comprises a plurality of processor nodes, directory nodes and a communication mechanism through a structured modeling mode, and constructing an asynchronous message mechanism to simulate disordered concurrent communication; protocol behavior rules such as processor requests, directory responses and network receiving are defined, protocol property invariants are set, semantic constraints such as data consistency, confirmation before writing and sharing state legality are covered, model verification is carried out in a state space traversal mode, breadth-first search and a symmetry recognition mechanism are supported, and the method is suitable for the protocol behavior rules. A protocol error or deadlock state is effectively found, a traceable error path is generated, a verifier can automatically generate source codes through a compiler and operate on a host platform, and rapid verification and result output of a protocol model are achieved. The method has good protocol adaptability and model reusability, and is suitable for formalized verification of various cache consistency protocols.

The invention discloses a data transmission optimization method and system in hybrid deployment of a real-time system and a non-real-time system based on Jailhouse, belongs to the technical field of data transmission, and solves the problems of low data transmission efficiency, high copy overhead, lack of universality of interfaces and the like in an existing system. Comprising the steps that a hybrid deployment platform including a real-time system and a non-real-time system is built on a multi-core processor platform, and the hybrid deployment platform runs in an isolation environment of a Jailhouse partition manager; building an abstract transmission interface layer as a unified channel for accessing a shared memory by a real-time system and a non-real-time system; establishing a plurality of shared memory channels in the abstract transmission interface layer and scheduling according to the priority of tasks; establishing a data transmission path, and compressing a memory copy operation into one time by adopting a memory mapping multiplexing technology and a DMA (Direct Memory Access) collaboration mechanism; and a cache consistency maintenance technology is adopted, so that the data consistency is ensured, and the optimization of data transmission is completed. The method is suitable for application scenes such as industrial automation, intelligent connected automobiles and edge calculation.

The invention relates to the technical field of parallel computing chips, in particular to a multiprocessor management method and device based on a parallel computing chip and a medium. The method comprises the steps that a plurality of stream processors are organized according to a hierarchical arrangement mode, a hierarchical SM cluster is formed, and each stage of SM core only keeps cache consistency with a lower stage of SM core directly controlled by the SM core; data of an external storage module enters a scheduling core through an L2 cache, and the scheduling core splits the data into thread bundles and dynamically allocates the thread bundles to a target SM core; when the thread processing demand of the target SM core exceeds the current capacity, starting a lower-level SM core according to a preset hierarchy rule, and expanding the processing capacity step by step; and skipping an unprocessed thread bundle over the current SM core through a thread bundle scheduler, splitting the unprocessed thread bundle, transmitting the split unprocessed thread bundle to a lower-level SM core, and merging calculation results of the lower-level SM core step by step through a shared memory. According to the invention, extra resources allocated by the system can be reduced, and the whole system is more efficient and ordered on the basis of ensuring consistency.

The invention discloses a circuit, a data processing method, equipment, a medium and a program product in the technical field of computers. In the application, the three-dimensional heterogeneous computing body layer can adapt to diversified computing power requirements, and is beneficial to realizing higher routing and higher data transmission efficiency between nodes. The shared cache layer is beneficial to realizing cache consistency of different heterogeneous computing nodes, and the cache utilization rate is improved. The internal interconnection module and the external interconnection module provided by the interface layer are easy to realize internal and external efficient communication. A first channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the three-dimensional heterogeneous computing body layer and direct connection of physical channels between the control layer and the shared cache layer; a second channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the interface layer; therefore, the communication delay between different levels can be reduced, the data transmission efficiency between different levels can be improved, and a high-bandwidth application scene can be met.

Adaptive system probe action to minimize input / output dirty data transfers is described. In one or more implementations, a system includes a processor, a memory configured to store data, and a cache configured to store a portion of the data stored in the memory for execution by the processor. The system also includes a cache coherence controller including a cache line history. The cache coherence controller is configured detect a direct memory access request from an input / output device. The direct memory access request is associated with an input / output operation involving the data. The cache coherence controller is further configured to identify a cache line associated with the direct memory access request, and, in response to the cache line history including a dirty data transfer record corresponding to the cache line, selectively send a probe to the cache based on a state of the cache line.

The invention discloses an interface conversion device and circuit, electronic equipment and an interface conversion method, and relates to the technical field of computer system structures. Extracting a cache or memory transaction request from the first preset interface signal through a channel processing module, generating consistency transaction information, sending the consistency transaction information to a consistency transaction concurrent processing module, receiving response data of the consistency transaction concurrent processing module, and packaging the response data into a second preset interface signal; the consistency transaction concurrent processing module carries out processing according to the received consistency transaction information to obtain a concurrent signal; and the interface conversion module decodes and converts the concurrent signal into a first target protocol control signal, and / or converts the authorized transaction into a second target protocol control signal. Therefore, concurrent analysis, consistency transaction mapping and direct conversion are carried out on a multi-channel protocol through a configurable modular hardware architecture, and high-concurrency and low-delay protocol conversion and cache consistency maintenance between an inter-chip consistency interconnection protocol and an on-chip bus protocol are realized.

Techniques for maintaining cache coherency while sharing data among multiple processors are disclosed. Multiple coherent elements are arranged in an M×N mesh topology. An element can include a compute coherency block (CCB), and a coherency ordering agent (COA). The COAs include a directory snoop filter (DSF), an eviction content addressable memory (eCAM), a miss and snoop queue (MSQ), and a pipeline logic. The CCB and COA include functions for interfacing with a hierarchical cache and directory snoop filter (DSF). A CCB from within one of the multiple coherent elements issues a read request. The corresponding directory snoop filter (DSF) is inspected to determine if there is a slot (way) available for storing information pertaining to the read request. In the event that no eligible vacancies are present in the DSF, a multi-pass process for handling a capacity limit in a DSF is performed.

Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions

A system for adaptively caching network communication protocols provides improved efficiency and performance through a multi-level cache architecture. The system monitors performance metrics and synchronizes cache contents across distributed nodes using a hierarchical structure. Protocol cache requirements are predicted based on usage patterns, enabling proactive cache management. The system compresses cached protocols using existing codebooks to optimize storage and transmission efficiency. Integration with event-driven data communication systems enables seamless protocol selection and translation. The caching system works in conjunction with transaction managers and protocol predictors to enhance network communication performance. The system maintains cache coherency across local, regional, and global cache levels while minimizing network overhead and optimizing protocol availability. By predicting and pre-caching likely needed protocols, the system reduces protocol negotiation latency and improves overall network communication efficiency.

In accordance with the described techniques for condensed coherence directory entries for processing in memory, a computing device includes a core that includes a cache, a memory that includes multiple banks, a coherence directory that includes a condensed entry indicating that data associated with a memory address and the multiple banks is not stored in the cache, and a cache coherence controller. The cache coherence controller receives a processing-in-memory command to the memory address and performs a single lookup in the coherence directory for the processing-in-memory command based on inclusion of the condensed entry in the coherence directory.

A computing device has a compute fast link (CXL) connection between a memory subsystem and a host system and has a memory access queue at least partially configured in the memory subsystem. The memory subsystem may attach a portion of its fast random access memory as a memory device to the host system through the connection. One or more memory access queues may be configured in the memory device. The host system may use a cache coherence memory access protocol to communicate storage access messages over the connection to the random access memory of the memory subsystem. Optionally, the host system may have a memory with a second memory access queue that may be used to access memory services of the memory subsystem over the connection using a memory access protocol.

The invention discloses an Ethernet-based distributed cache coherence protocol, an implementation method, an implementation device and an implementation system. A plurality of computing nodes are connected through a packet switching network. Each computing node comprises a CPU / GPU (Central Processing Unit / Graphics Processing Unit) and a local cache thereof, and is provided with a cache agent. The far-end memory is organized in home nodes, and each home node manages a part of physical address space and is equipped with a directory controller. When the CPU of the computing node accesses a far-end memory address and does not hit in the local cache, the CA of the computing node replaces the far-end memory address and communicates with the DC managing the address through the network so as to maintain the cache consistency of the data among all the nodes. Based on a cache consistency protocol of a directory, the CXL.cache consistency of a plurality of independent computing nodes can be maintained in a low-overhead and high-reliability mode on a high-delay and lossy packet switching network, and broadcast storm caused by a monitoring protocol is avoided.

A system for managing cache coherency comprises memory areas, processing cores, cache nodes each associated with at least one of the processing cores, and a hardware processor configured to: for each of the memory areas: cluster the processing cores into clusters according to memory access metrics in relation to the memory area; and for each of the clusters, associate the memory area with a caching scheme; and configure the processing cores to: receive from a first core a memory access command comprising a memory address associated with a memory area, where the first core is a member of a first cluster for the memory area; compute a determination of a target cache node according to the memory access command, where the target cache node is associated with a second core; and access the memory area according to the caching scheme associated with the memory area for the first cluster.

The invention discloses a low-delay interrupt processing method and system of an intelligent control center, and belongs to the field of industrial control computer system architecture. The method comprises the following steps: analyzing an interrupt request to obtain an event type identifier; based on a predefined event priority mapping table, matching the event priority into a corresponding interrupt priority; selecting a path from a pre-allocated and physically isolated hardware response path set according to the interrupt priority; distributing the interrupt request and the context data to a pre-bound processing core through the selected path; and the processing core executes the preloaded simplified processing routine to generate a driving instruction. Through combination of event semantic mapping and physical isolation hardware paths, a deterministic low-delay response channel is provided for core emergency interrupt, system reliability is improved through a load balancing mechanism based on cache consistency, the problem of large delay jitter of high-concurrency interrupt processing of an industrial intelligent control center is effectively solved, and the system reliability is improved. And the real-time performance of the control system is obviously improved.

Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions

The invention discloses a control system supporting concurrent access of multiple hosts, a storage device and a medium, and relates to the technical field of data storage, the system runs on a control module externally connected with the storage device, and the system comprises a communication connection management unit used for establishing connection with multiple hosts through at least two host interfaces; the access request receiving unit is used for receiving access requests sent by different hosts through an uplink port of the multi-host switching chip, and the access arbitration and scheduling unit is used for carrying out real-time arbitration and unified scheduling on the requests according to a preset strategy; and the instruction forwarding and execution unit forwards an arbitrated instruction to the storage unit for execution through a downlink port, and the system further integrates a cache consistency management unit, a configurable arbitration strategy unit, a multi-mode storage space management unit and the like, so that the data consistency, the access efficiency and the system reliability during multi-host concurrent access are ensured. According to the scheme, efficient and safe parallel access of a plurality of hosts to a single storage device is realized.

The invention discloses a maintenance, recording and transmission method, device and equipment for cache consistency, and the recording method comprises the steps: responding to a first processing unit in a processing unit array to cache a first data block, and obtaining a first position coordinate of the first processing unit in the processing unit array, the first coordinate comprises a plurality of values respectively corresponding to a plurality of dimensions of the processing unit array; according to the first coordinate data, a first directory entry corresponding to the first data block in the cache consistency directory is updated, the first directory entry comprises a plurality of arrays corresponding to a plurality of dimensions, and in the first directory entry, the first data block corresponds to the first directory entry; the array corresponding to each dimension is used for marking dimension coordinates of the processing unit which caches the first data block on the dimension. The recording method can reduce the directory capacity.

A method for supporting cache coherency based on a virtual address for an artificial intelligence processor having a large capacity on-chip memory and an apparatus using the same are disclosed. A method for supporting cache coherency according to an embodiment of the present invention comprises the following steps performed by an artificial intelligence processor comprising a plurality of processor cores and a plurality of caches: setting non-overlapping external memory address regions in each of the plurality of caches; and providing a virtual address for the plurality of processor cores to access the plurality of caches.

According to the writing transmission device and method for the CHI bus protocol system and the AXI4 equipment, main equipment which does not support cache consistency and a CHI bus are interconnected for writing transmission under the condition that design is not modified, the cache consistency and address allocation of the whole system are maintained, the data consistency when the main equipment accesses shared data is ensured, and the reliability of the system is improved. And errors caused by non-updating of the cache or conflicts are avoided. The device receives a write command sent by AXI4 equipment, and converts the write command into various types of write requests of a CHI protocol; comparing the write addresses sent by the AXI4 device with the addresses in the address mapping table one by one, and after the comparison is successful, obtaining a destination identification code corresponding to the cache line; the transmission identification codes are gradually increased in a transmission command by the device, judging whether the transmission identification codes are a main memory or a cache, and determining a command identification code, a cache attribute and a monitoring attribute according to the main memory and the cache; when the total transmission amount is smaller than or equal to 64 bytes, the size in the request command packet is the actual total transmission amount.

A cache memory subsystem includes virtually-indexed L1 and PIPT L2 set-associative caches having an inclusive allocation policy such that: when a first copy of a memory line specified by a physical memory line address (PMLA) is allocated into an L1 entry, a second copy of the line is also allocated into an L2 entry; when the second copy is evicted, the first copy is also evicted. For each value of the PMLA, the second copy can be allocated into only one L2 set, and an associated physical address proxy (PAP) for the PMLA includes a set index and way number that uniquely identifies the entry. For each value of the PMLA there exist two or more different L1 sets into which the first copy can be allocated, and when the L2 evicts the second copy, the L1 uses the PAP of the PMLA to evict the first copy.

The invention discloses a method for quickly and accurately updating a switch key value cache, which comprises the following steps of: distributing enough switch resources according to a cache size specified by a user, realizing logic storage through circulation, and creating two queues for query and key value pairs; allocating switch resources and creating a multi-slot buffer area for matching query and key value pairs; processing read queries through a single producer-single consumer algorithm in a switch pipeline, while write queries are sent to key value storage nodes to maintain cache coherency; identifying a new hotspot key by tracking hit times and using a voting mechanism; and replacing the unpopular key with the new hotspot key, and obtaining new data from the storage node.

In part, the disclosure relates to a fault tolerant system. The system may include one or more shared memory complexes, each memory complex comprising a group of M computer-readable memory storage devices; one or more cache coherent switches comprising two or more host ports and one or more downstream device ports, the cache coherent switch in electrical communication with the one or more shared memory storage device; a first management processor in electrical communication with the cache coherent switch; a first compute node comprising a first processor and a first cache, the first compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes; a second compute node comprising a second processor and a second cache, the second compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes.

The invention provides a cache consistency test method and device, electronic equipment and a computer readable storage medium. The method comprises the steps of obtaining a test sequence of a multi-core cache system; the multi-core cache system comprises at least two processor cores and a multi-level cache. The test sequence comprises an operation instruction for each processor core; inputting the test sequence into the simulation model, processing the test sequence in sequence through multi-stage caches of the simulation model according to a cache coherence protocol, and outputting a state check point of the multi-core cache system; the state check point is used for representing the current cache state of each processor core in the multi-core cache system; and testing the cache consistency of the multi-core cache system according to the state check point to obtain a test result. According to the embodiment of the invention, the reliability and comprehensiveness of the cache consistency test can be improved.