On-chip network system supporting cache coherence and data request method

An on-chip network and high-speed cache technology, which is applied in transmission systems, digital transmission systems, data exchange networks, etc., can solve problems such as difficulty in expanding access delays in directories, complex design of consistency protocols, etc., to reduce storage and delay overhead, simplify Design and verify process, effect to improve performance

Inactive Publication Date: 2011-01-26
TSINGHUA UNIV
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Problems solved by technology

[0014] The technical problem to be solved by the present invention is the problems of complex design, diffic

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  • On-chip network system supporting cache coherence and data request method
  • On-chip network system supporting cache coherence and data request method
  • On-chip network system supporting cache coherence and data request method

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Embodiment Construction

[0056] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0057] In multi-core processors, the operation of the cache coherence protocol is transmitted through the on-chip network. The private cache (Level 1 cache) miss request of the multi-core processor is sent to the on-chip network through the network interface component, and the response information is also transmitted to the router of the requesting node through the on-chip network, and then returned to the multi-core processor through the network interface component. Access to directories and data in the shared L2 cache is also transmitted through the network interface component. The response message of the shared secondary cache to the multi-core processor and the invali...

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Abstract

The invention discloses an on-chip network system supporting cache coherence. The network system comprises a network interface part and a router, wherein the network interface part is connected with the router, a multi-core processor and a second level cache; a consistent state cache connected with the multi-core processor is additionally arranged in the network interface part and is used for storing and maintaining the consistent state of a data block in a first level cache of the multi-core processor; and an active directory cache connected with the second level cache is also additionally arranged in the network interface part and is used for caching and maintaining the directory information of the data block usually accessed by the first level cache. Coherence maintenance work is separated from the work of a processor, directory maintenance work is separated from the work of the second level cache, and the directory structure in the second level cache is eliminated, so that the design and the verification process of the multi-core processor are simplified, the storage cost of a chip is reduced, and the performance of the multi-core processor is improved. The invention also discloses a data request method of the system.

Description

technical field [0001] The invention relates to the technical field of computer system structure, in particular to an on-chip network system supporting cache consistency and a data request method. Background technique [0002] After entering the era of one billion transistors on a single chip, the focus of architecture research has gradually shifted from how to use limited resources to realize required functions to how to make full use of ever-growing transistor resources to design processors that meet the requirements of high performance and low power consumption. Multicore processors (Multicore processors) provide an efficient and scalable solution for effectively utilizing these transistor resources, and are favored by academia and industry. A chip will integrate multiple (Multicore) or many (Manycore) processor cores, that is, a large-scale multi-core processor. The main challenges faced by large-scale multi-core processors are design complexity, scalability, and storag...

Claims

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Application Information

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IPC IPC(8): H04L12/56H04L29/06G06F15/163H04L47/30
Inventor 王惊雷汪东升
Owner TSINGHUA UNIV
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