45 results about "Cache consistency" patented technology

The invention relates to a final-stage cache design method based on near memory calculation, and belongs to the technical field of near memory calculation. And compared with a near memory processor near a traditional main memory, data access and calculation can be carried out more quickly, and the calculation throughput rate can be improved. According to the near storage calculation, a near storage processor and a last-stage cache storage array are directly designed in an integrated mode, faster memory access is achieved through an internal bus interconnection mode, and the problem of a storage wall between the calculation speed and the memory access speed and the problem of a power consumption wall of data handling are relieved to a certain degree. The last-stage cache controller cooperates with the embedded processor, and can dynamically coordinate between a standard cache function and a calculation mode. Through a synchronization mechanism in a last-stage cache controller, a memory access request from a host CPU and a calculation task executed by an embedded processor in a last-stage cache are transparently balanced, so that efficient near-memory calculation under cache consistency is realized.

The invention discloses a cache maintenance system of a heterogeneous computing system and electronic equipment, and relates to the technical field of data processing, a first directory controller manages the consistency state of a host end, and a second directory controller manages the consistency state of an equipment end. The consistency maintenance operation is firstly efficiently processed by the corresponding directory controller in the storage domain, cross-device frequent coordination communication is reduced, and when cross-domain data access occurs, the two directory controllers cooperate through an established communication coupling mechanism and execute global consistency maintenance as required. The method not only can adapt to a high-burst and high-parallel access mode of a device end, but also can avoid direct conflicts with a cache management mechanism of a host end, and realizes global consistency through distributed collaboration. The technical problem of performance bottleneck of cache consistency in the heterogeneous system is solved, and the technical effect that the overall data access efficiency of the heterogeneous system is improved while the correctness is maintained is achieved.

The invention discloses a graph database query acceleration method and system. The method comprises the following steps: constructing panoramic query observation data through non-intrusive log interception and structured processing; the query statement is analyzed into an abstract syntax tree, semantic normalization processing is carried out, and a unique hash value is generated; predicting a hotspot query template and high-frequency parameters thereof based on a popularity value score model, and asynchronously preloading a result to a cache; dynamically calculating adaptive survival time for each cache item according to the data change frequency and the access popularity; and constructing a multi-level cache architecture comprising a local cache, a distributed cache and a database built-in cache, and performing intelligent routing and collaborative backfilling based on a hash value. According to the method, intelligent and transparent acceleration of graph database query is realized, the query performance is remarkably improved, the database load is reduced, and the problems of redundancy, high cold start delay and difficulty in balancing cache consistency caused by grammar difference in traditional cache are solved.

The application relates to the chip technical field and discloses a partition unit, a partition, a chip, a network-on-chip implementation method and a medium. The partition unit comprises the following steps: obtaining an operation type and an access address corresponding to a memory access request through a secondary cache, and forwarding the memory access request to a control module of a directory corresponding to the access address when the operation type is a partial write operation; writing request data corresponding to the memory access request into a small-capacity cache through the control module, reading a target partition unit corresponding to the partition unit from a state recording module, generating a listening request according to the memory access request and sending the listening request to the target partition unit, receiving listening data fed back by the target partition unit, merging the listening data and the request data to generate complete data, and writing the complete data into a memory controller. Hardware support for cache consistency can be provided in an artificial intelligence chip with a multi-core architecture, and a network-on-chip implementation scheme supporting cache consistency is provided.

This application provides a verification system, verification method, apparatus, and related devices. The verification system includes two cache consistency slave device verification units, each configured with a main address region and a mirror address region. The mirror data in the mirror address region of one cache consistency slave device verification unit is the data in the main address region of the other cache consistency slave device verification unit. When a mirroring operation is triggered between the two cache consistency slave device verification units, the correctness of the mirror data in the mirror address region is verified. The verification is determined by comparing the data in the main address region of one cache consistency slave device verification unit with the mirror data in the mirror address region of the other cache consistency slave device verification unit. This application avoids the complex processes of traditional verification, comprehensively reduces verification overhead, and thus improves the verification efficiency of memory address mirroring functionality.

The application discloses a multi-core cache consistency debugging method based on multi-view access and belongs to the field of multi-core processor debugging. The method is characterized in that a target address is specified in a main memory by a host computer through a JTAG debugging interface, five groups of data of CPU view, L1 data cache view, L1 instruction cache view, L2 view and real memory view corresponding to the address are read in turn, whether cache is invalid is judged by comparing data consistency, and a cache level inconsistent is marked. The debugging system comprises a built-in JTAG TAP controller, an enhanced debugging access module, a storage level access arbitrator and a data and state collector. The application realizes direct access of the JTAG interface to data of each level of cache, does not need to modify hardware or disable cache, does not interfere with system operation, can quickly locate cache consistency problems under a multi-core architecture, improves debugging efficiency and accuracy, and is suitable for debugging scenes of large-scale multi-core processors.

The application relates to the technical field of storage systems in computer architecture, and relates to a cache consistency control method and system based on a static memory and electronic equipment. Through a hardware-level cache tag synchronization mechanism, the cache consistency is efficiently maintained, the cache update delay is reduced, the overall data processing speed and performance of the system are improved, protocol parameters are dynamically adjusted through an adaptive optimization strategy, the system can maintain high operation efficiency under different workloads, and the adaptability of the protocol and the system performance are enhanced.

The invention provides a cache consistency test method and device, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps that a target CPU in the system-on-chip is restored to an original environment without consistency maintenance, and a first preset test value is written into a preset memory in the original environment; according to a plurality of consistency maintenance functions corresponding to the target CPU, determining a first parameter data structure set corresponding to the target CPU, executing each first parameter data structure, and obtaining a target value at a preset memory; and determining a consistency maintenance result of the target cache according to the plurality of target values, the first preset test value and the preset parameter data structure corresponding to the target CPU, so that the target parameter data structure which enables the target cache to have consistency can be screened and determined from the first parameter data structure set. And according to the screened target parameter data structure and the preset parameter data structure, testing the consistency of the target cache in the system-on-chip.

The invention belongs to the technical field of cache consistency maintenance, and particularly relates to a directory updating method and device for maintaining cache consistency, a medium and a program product. The directory updating method for maintaining the cache consistency comprises the following steps: in response to a cache consistency maintenance operation initiated by a current processor core, obtaining a target cache block targeted by the cache consistency maintenance operation and first target core information of the current processor core; determining a target directory table item corresponding to the target cache block; obtaining a current recording mode of the target directory table item for shared information; and updating the target directory table item according to the first target kernel information and the current recording mode. Therefore, the cache blocks needing to maintain the cache consistency can be determined by a more efficient method when the cache consistency is executed, and the data sharing and interaction efficiency is greatly improved.

The invention relates to the technical field of electric digital data processing, and discloses an edge computing network collaborative scheduling system for high-speed rail platform end security response sinking, which comprises a processor core used for processing a security task; the data acquisition module acquires a video data stream; the scheduling distribution module calculates a bit rate change parameter and predicts a load, and issues a storage isolation control word containing a task identifier and a spatial index when an emergency condition is met; the memory management module intercepts the addressing request and modifies a page table entry memory attribute bit to configure a private address field; the cache consistency filtering module recognizes the memory access state, the hardware level shields a cache line state sniffing request generated by a consistency protocol, through silent isolation of the physical level, micro-architecture level performance degradation caused by the inter-core consistency protocol is eliminated, and it is ensured that the security algorithm processing time delay can be predicted in the complex interference environment.

The application discloses a kind of dynamic rights allocation method, device and equipment based on user contribution value and medium.The method is captured by front-end system user interaction behavior event, is forwarded to B system event hub after being verified and enhanced by A system, then asynchronously is delivered to message queue and is handled.Consumption end calculates contribution value variation according to dynamically configured rule base table, supports positive and negative adjustment of civilization contribution value and platform contribution value.System uses MySQL and Redis double storage architecture, and guarantees data consistency under high concurrency by atomic operation.Based on formula β (i)=U (i) / (G (t)-G (0)) Real-time calculation user contribution proportion, provide proportion type rights release, ladder type ranking empowerment, threshold type screening incentive Three allocation strategies.Through event-driven architecture and cache consistency algorithm, millisecond-level contribution value update and second-level proportion accounting are realized.The application solves the problems of single contribution measurement mechanism, rights allocation rigidity and calculation performance bottleneck in traditional integral system.

The application relates to the technical field of electric digital data processing, and discloses an edge algorithm network cooperative scheduling system for high-speed rail platform end safety response sinking, which comprises a processor core used for processing a safety task; a data acquisition module used for acquiring a video data stream; a scheduling and distribution module used for calculating a bit rate change parameter and predicting a load, and used for issuing a storage isolation control word containing a task identifier and a space index when a burst condition is met; a memory management module used for intercepting an addressing request and modifying a page table item memory attribute bit to configure a private address domain; and a cache consistency filtering module used for identifying a memory access state, and used for shielding a cache line state sniffing request generated by a consistency protocol at a hardware level; the application eliminates micro-architecture level performance attenuation caused by inter-core consistency protocols through physical layer silence isolation, and ensures the predictability of safety algorithm processing delay in a complex interference environment.

This invention discloses a distributed storage management device and computing device for multi-core systems. The distributed storage management device includes a DVM proxy module, a DVM remote sending module, and a DVM remote receiving module, each deployed in each core. The DVM proxy module receives DVM request messages containing invalidation address information submitted by the core node in its core, and uses a distributed broadcast mechanism to send the DVM request messages to the core nodes and IO nodes of its core and other cores, thereby invalidating the invalidation addresses carried in the DVM request messages to achieve a unified memory view. This invention aims to solve the cache consistency problem of invalidating large areas of address space data in multi-core systems, including broadcasting invalidation information of DVM operations, avoiding deadlocks in DVM synchronization operations between multiple cores, and optimizing the excessively long execution latency of DVM operations in multi-core scenarios.

The invention relates to an MIPS multiprocessor system based on a CXL interface and computer equipment. The system comprises: at least one MIPS processor core; the consistency management module is connected with each MIPS processor core through an MCP bus, and the consistency management module is used for managing the internal cache consistency of each MIPS processor core; and the CXL controller is integrated in the consistency management module and is used for managing the cache consistency between the MIPS multiprocessor system and the external heterogeneous CXL equipment based on a CXL protocol. The consistency management module of the system internally manages the internal cache consistency of each MIPS processor core, and externally realizes the cache consistency between the MIPS multiprocessor system and an external heterogeneous CXL device through the CXL controller, so that a double-level consistency architecture is realized, and the processing performance of a heterogeneous computing unit is improved.

The application discloses a kind of graphic processor, cache data sharing method, equipment, medium and program product, it is related to processor technical field, by setting and computing core one-to-one corresponding first cache, and by interconnection interface unit constructs the two-way communication link of each first cache and central tag buffer, with the global tag table of all first cache data block tag information is recorded, when first cache receives the read data request of connected computing core and local does not store target data block, other first cache where target data block is located can be positioned by central tag buffer, direct data transmission between first cache is realized via interconnection interface unit, without relying on second cache transfer, reduce the access pressure of second cache, solve bandwidth bottleneck problem, shorten data transmission path, reduce data access delay, avoid the complex design brought by traditional cache consistency protocol, improve cache resource utilization, optimize the overall operating performance of graphic processor.

A computer device with a Computer Express Link (CXL) connection between a storage subsystem and a host system, and with memory access queues that are at least partially configured in the storage subsystem. The storage subsystem can attach a portion of its fast random-access storage as a storage device to the host system over the connection. One or more memory access queues can be configured in the storage device. The host system can use a cache-coherent memory access protocol to communicate memory access messages over the connection to the storage subsystem's random-access storage. Optionally, the host system can have storage with secondary memory access queues that can be used to access the storage services of the storage subsystem over the connection using a data storage access protocol.

The invention discloses an authority management system and method for multi-source authority aggregation and dynamic inheritance decoupling, and belongs to the technical field of DevOps, the system comprises an authority storage module for realizing user affiliation judgment of constant time complexity through non-expansion storage and bitmap indexing; the reverse index module is used for asynchronously updating the authority in batches through a secondary hash reverse index and a message queue; the permission aggregation module is used for obtaining an aggregation permission list through union set operation; the source tracing module is used for obtaining directly added permissions through difference set operation; the inheriting and decoupling module is used for realizing dynamic inheriting and decoupling through an inheriting flag bit and a user-defined mask; and the cache synchronization module realizes increment synchronization through three-layer version number and inheritance chain propagation. According to the method, the problems of difficulty in source tracing, low dynamic decoupling efficiency, poor batch change performance and poor cache consistency are solved, and efficient, accurate and extensible multi-source authority management is realized.

The application relates to a multi-core processor WCET analysis method supporting a multi-level consistency protocol and belongs to the technical field of computer application. The method is aimed at a multi-level consistency processor architecture, adopts a hierarchical division idea, divides the multi-level consistency processor into multi-level consistency domains, analyzes data access of the multi-core processor from two levels of domain access and cross-domain access, obtains a state update function of Cache of the multi-level consistency domain, realizes WCET analysis of the multi-core processor with the multi-level consistency protocol, and solves the WCET analysis problem under the nesting condition of the Cache consistency protocol of the multi-core processor.

The invention discloses a high-availability write-back cache method based on a distributed file system, which comprises the following steps of: distributing shared read or exclusive write-in permission through a lease mechanism, and ensuring metadata cache consistency and concurrency control; the client generates an idempotent log and writes the idempotent log into a far-end log server through a single-side RDMA, and the server skips repeated log replay based on a global unique serial number to realize fault recovery; and the server divides the persistent memory into pre-distribution blocks, the client directly writes the distribution blocks during exclusive writing, and the distribution blocks are synchronized to stable storage and recovery after the distribution blocks are fully written or lease is released. Through the technical means of a lease mechanism, idempotent logs and persistent memory pre-distribution blocks, high-availability writing of metadata cache in the distributed file system is achieved.

The invention provides a multi-dimensional resource dynamic management and efficient access method, terminal equipment and a storage medium. The method comprises the following steps: defining a node data structure of a hierarchical tree; constructing a static hierarchical skeleton structure of the hierarchical tree; dynamically adding resource index nodes; establishing a multi-dimensional index mapping table; establishing a node ID index mapping table; realizing a hierarchical caching strategy; batch cache writing is realized; efficient subsequent node traversal is realized; batch traversal operation is realized; and the cache consistency is ensured. According to the method, dynamic construction of hierarchical data, efficient indexing of multi-dimensional resources, differentiated cache management and rapid traversal of batch data can be realized.

The invention relates to a hardware architecture simulation tool oriented to system-level chip interconnection optimization, which is characterized in that a processor core, a cache controller, a memory controller and an on-chip interconnection network model with an accurate period are integrated in a full-system joint simulation framework, and the conversion between a cache consistency message and an interconnection data unit is realized through a network interface controller; network delay is fed back to a system simulation scheduler with cycle-level precision, an interconnection network adopts a router micro-architecture with an accurate cycle for modeling, key stages such as buffering, routing, virtual channel distribution, switch distribution and link traversal are finely depicted, and virtual channel flow control and a point-to-point sorting mechanism are combined, so that the routing efficiency is improved. And a power consumption analysis model based on activity counting is introduced, and the dynamic power consumption and the static leakage power consumption of the interconnection network are accurately evaluated. According to the application, various network topologies, routing strategies and hardware parameter configurations are supported, and the comprehensive influence of the interconnection architecture on the performance and energy efficiency of the chip is accurately evaluated at the system level.

Embodiments of the present disclosure provide a cache consistency processing method, a cache consistency processing device, a system on chip, a computer storage medium and a computer program product. The cache consistency processing method is used for managing cache consistency of processing units corresponding to each node of a network on chip. The cache consistency processing method comprises: unpacking a current monitoring packet received from an upstream routing node to obtain a current merging position of a current destination node set sharing a current routing node, wherein an initial merging position of an initial destination node set is generated by a cache consistency node and sent through an initial routing node; analyzing the current merging position to determine a downstream merging position of a downstream destination node set, wherein the downstream destination node set is at least part of the destination node set sharing a downstream routing node; and packaging the downstream merging position in a downstream monitoring packet and sending the downstream monitoring packet to the downstream routing node.

The invention discloses a multi-core cache consistency debugging method based on multi-view access, and belongs to the field of multi-core processor debugging. According to the method, an interface is debugged through a JTAG (Joint Test Action Group), an upper computer specifies a target address in a main memory, five groups of data of a CPU (Central Processing Unit) view angle, an L1 data caching view angle, an L1 instruction caching view angle, an L2 view angle and a real memory view angle corresponding to the address are sequentially read, whether cache fails or not is judged by comparing data consistency, and inconsistent cache levels are marked. The debugging system comprises a built-in JTAG TAP controller, an enhanced debugging access module, a storage level access arbiter and a data and state collector. According to the method, direct access of the JTAG interface to each level of cache data is realized, hardware modification or cache forbidding is not needed, system operation is not interfered, the cache consistency problem under a multi-core architecture can be quickly positioned, the debugging efficiency and accuracy are improved, and the method is suitable for a debugging scene of a large-scale multi-core processor.

The invention discloses a transaction processing method of a multi-core processor, the multi-core processor and electronic equipment, and relates to the technical field of cache consistency of the multi-core processor. In the method, a combined data packet is sent to a destination end. Compared with a one-by-one data packet transmission mode, the transmission pressure of the on-chip interconnection network is reduced, so that the overhead of cache consistency maintenance is reduced; and secondly, aiming at the read-write transactions of the plurality of continuous cache line addresses, configuring an operation code of the target protocol as a read-write transaction identifier, and configuring an address field of the target protocol as a read-write transaction address, thereby generating a merged data packet. And for the plurality of failure monitoring request transactions, merging the destination node identifiers of the plurality of failure monitoring request transactions in the target protocol to generate a merged data packet. In addition, the read-write operation of the continuous cache line address is realized based on the operation code of the target protocol, and the read and write transaction data packet structure of the existing protocol is kept unchanged.

Systems and methods are provided for implementing data backup and recovery using cache-coherent interconnect node-based non-volatile memory. A cache-coherent interconnect node partitions a memory pool into a plurality of memory regions as well as a backup storage into a plurality of memory portions, and pre-allocates a memory region and a corresponding memory portion to each compute node. When a rack-level power loss occurs, and a battery-based power source is activated, a cache-coherent interconnect controller saves data from each memory region into the corresponding memory portion, and subsequently saves an entry for each memory portion in an index portion of the backup storage. Subsequently, the controller causes a power circuitry to shut down the backup power source. After rack-level power restoration and memory region initialization, the controller restores, for each memory region, the data saved in a corresponding memory portion into that memory region, based on information in a corresponding entry.

The invention discloses a distributed cache consistency control method, a distributed cache consistency control system and a computer readable medium. The distributed cache consistency control method comprises the following steps: S1, registering a plurality of service cache units on a client side; s2, publishing the notification message to a message theme corresponding to the service cache unit; s3, executing idempotent verification and deduplication processing on the global unique message identifier, and if the message is not processed, continuing to execute subsequent steps; s4, continuing to execute the refreshing process only when the version number to be released is greater than the local version number, otherwise, discarding the notification message and recording version backtracking information; s5, when refreshing is interrupted, exponential backoff retry is executed, and a global unique message identifier is reserved; s6, the center side periodically receives the service cache unit state information reported by the client side; and S7, a closed loop of distributed local cache consistency control is completed. According to the method, global consistent convergence of the cross-instance local cache and the back-end database is realized, and the transaction atomicity and the data reliability of the system are improved.

A persistent memory device is disclosed. The persistent memory device may include a cache coherent interconnect interface. The persistent memory device may include a volatile storage and a non-volatile storage. The volatile storage may include at least a first area and a second area. A backup power source may be configured to provide backup power selectively to the second area of the volatile storage. A controller may control the volatile storage and the non-volatile storage. The persistent memory device may use the backup power source while transferring a data from the second area of the volatile storage to the non-volatile storage based at least in part on a loss of a primary power for the persistent memory device.

The embodiment of the invention provides a remote data processing method and device and computing equipment, relates to the technical field of computers, and can improve the remote data processing efficiency. The method is applied to a first device, the first device is in remote communication with a second device, and the method comprises the steps that an operation request, sent by the second device, of to-be-processed data is received, and the operation request comprises a read request or a write request; in response to the operation request, executing an operation indicated by the operation request on the to-be-processed data under the condition that a preset condition is met; the preset condition is used for indicating that the to-be-processed data is in a cache consistency state; in response to the operation request, under the condition that a preset condition is not met, invalidation operation is executed on the to-be-processed data, the invalidation operation is used for invalidating the to-be-processed data in copy equipment, and the copy equipment is equipment caching the to-be-processed data.

The invention relates to the technical field of artificial intelligence, and discloses a cache management method and device, a medium and a program product. The method comprises the following steps: acquiring a first data operation request of cache line granularity sent by a coprocessor, and acquiring a current memory address according to the first data operation request; obtaining a target snoop filter corresponding to the coprocessor from the candidate snoop filters, and obtaining a current address tag corresponding to the current memory address through the target snoop filter; performing comparison detection on the current address tag and the stored address tag through a target snoop filter to obtain a comparison result; and executing data operation according to the comparison result and the first data operation request through a local cache memory and / or a main memory of the main processor so as to realize cache management. According to the method, the query bandwidth and the memory access efficiency can be improved, the access delay can be reduced, and the management efficiency and accuracy of cache consistency can be improved.