108 results about "Cache consistency" patented technology

The invention discloses a cache consistency system, method and device, an electronic device and a storage medium, and relates to the technical field of computers.A request buffer area is arranged between a master node and a slave node, the slave node can monitor the blocking condition of each memory access request in the request buffer area, and the cache consistency is improved. When the request blocking degree of any processor core reaches the preset blocking threshold value, the priority of the memory access request of the processor core is improved in the request buffer area, so that the situation that the slave node does not respond to the memory access request of a certain processor core in time is avoided, and the overall performance of a system is improved.

The invention relates to a final-stage cache design method based on near memory calculation, and belongs to the technical field of near memory calculation. And compared with a near memory processor near a traditional main memory, data access and calculation can be carried out more quickly, and the calculation throughput rate can be improved. According to the near storage calculation, a near storage processor and a last-stage cache storage array are directly designed in an integrated mode, faster memory access is achieved through an internal bus interconnection mode, and the problem of a storage wall between the calculation speed and the memory access speed and the problem of a power consumption wall of data handling are relieved to a certain degree. The last-stage cache controller cooperates with the embedded processor, and can dynamically coordinate between a standard cache function and a calculation mode. Through a synchronization mechanism in a last-stage cache controller, a memory access request from a host CPU and a calculation task executed by an embedded processor in a last-stage cache are transparently balanced, so that efficient near-memory calculation under cache consistency is realized.

Disclosed in the present application are a data processing system and method, and a device, a medium and a computer program product in the technical field of computers. The data processing system comprises: at least one processor device and at least one target device connected to the at least one processor device, wherein the processor device and the target device each comprise a consistency function processing device and at least one consistency interface. In the same device, the consistency function processing device is in communication connection with the at least one consistency interface; and two consistency interfaces in different processor devices are in communication connection with each other, two consistency interfaces in different target devices are in communication connection with each other, or two consistency interfaces in any processor device and any target device are in communication connection with each other, such that the cache consistency between different processor devices, the cache consistency between different target devices, or the cache consistency between any processor device and any target device is realized.

Provided in the embodiments of the present application are a server system, a resource scheduling method for a server system, and a chip and a chiplet. The server system comprises: a multivariate computing resource pool, a data storage resource pool, a switching module and a control module, wherein the multivariate computing resource pool comprises a general computing resource pool and a heterogeneous computing resource pool, the general computing resource pool comprising a group of general computing units, and the heterogeneous computing resource pool comprising a group of heterogeneous computing units, and the multivariate computing resource pool is connected to the data storage resource pool via the switching module by means of a cache consistency bus inside the server system; the data storage resource pool comprises data storage resources allowed to be shared by multivariate computing resources in the multivariate computing resource pool; and the control module is configured to perform computing power scheduling on the multivariate computing resources in the multivariate computing resource pool, and dynamically allocate the data storage resources in the data storage resource pool to the multivariate computing resources in the multivariate computing resource pool.

The invention discloses a consistency interconnection control device and method, an electronic device, a product and a computing system, and relates to the technical field of computers, the consistency interconnection control device is provided and comprises a consistency interconnection network, a first controller and a first connector, the consistency interconnection network comprises a plurality of interconnected consistency interconnection nodes, the consistency interconnection node is connected with the first card slot for installing the acceleration card through the first connector, and the first controller manages the state of the cache line of the acceleration card and controls the consistency interconnection network to execute the consistency interconnection read-write task between different acceleration cards, so that the consistency interconnection system for the acceleration computing cluster is realized. By implementing the cache consistency between the acceleration cards, when the acceleration computing cluster executes distributed computing, the cache can be hit firstly, so that access to a local memory and memories of other acceleration cards is reduced, the problem of high time consumption of communication between different accelerators of the acceleration computing cluster is solved, and the efficiency of distributed computing is improved.

The embodiment of the invention relates to the technical field of processors, in particular to an active maintenance method and device for cache consistency, electronic equipment and a storage medium, and the method comprises the following steps: in response to the maintenance of the cache consistency, implementing invalidation operation on a copy of a first cache block of a target processor core, checking the consistency maintenance mode of the copy of the first cache block; under the condition that the consistency maintenance mode is an active maintenance mode, after invalidation operation is completed, an updating command is initiated to update the copy of the first cache block to the latest data content; after updating of the copy of the first cache block is completed, the copy of the first cache block is recovered to be in an effective state. According to the method, convenient and selective use of the active maintenance method is realized, and the hardware overhead of the active maintenance method is reduced by fully utilizing an existing hardware mechanism for consistent passive maintenance of the cache on the CPU.

The invention provides a distributed cache consistency system, method and device, a storage medium and a product, and is applied to a CXL switch, and a connection physical device comprises a first cache device and a CXL memory protocol-based memory extension device comprising a second cache device and a memory device. The system is composed of a virtualization aggregation layer and a cache consistency control module, the virtualization aggregation layer aggregates physical equipment as logic equipment, and the cache consistency control module intercepts operation requests, performs protocol conversion and queries directories to determine cache line states and equipment where the cache line states are located and feeds back target data. According to the scheme, the problems of delay, expansibility, communication efficiency and resource waste of the existing centralized architecture are solved. A distributed system is deployed on a CXL switch, so that processing skips and steps are reduced, and delay is reduced; a distributed architecture is adopted to avoid resource bottlenecks and improve expansibility; inter-device communication intermediate links are reduced, and the communication efficiency is improved; intermediate nodes of a data transmission path are reduced, transmission overhead is reduced, resource utilization rate is improved, and resource waste is reduced.

The invention discloses a data transmission method and device, an industrial control system, a storage medium and a computer program product, and the method comprises the steps: initializing a continuous physical memory, dividing the continuous physical memory into memory blocks with a fixed size, recording the initial address, size, idle or occupied state of the memory blocks through a red-black tree, and forming a dynamic address pool; the dynamic address pool can realize on-demand allocation of memory blocks and merging and dynamic expansion of adjacent free blocks; the method comprises the following steps: acquiring a load index in real time through an FPGA (Field Programmable Gate Array), triggering interruption based on load grading and predicting a memory demand in combination with a machine learning model, and pre-fetching a memory block from a dynamic address pool to a user mode mapping region before a real-time task initiates a memory allocation request; a user mode atomic operation annular queue is designed, direct data interaction between the X86 and the FPGA is achieved through memory mapping, and a Burst transmission and cache consistency protocol of a hardware bus is combined. According to the scheme, the problem of memory fragmentation is solved, the data transmission delay is reduced, and the CPU occupancy rate is greatly reduced.

The invention discloses a cache maintenance system of a heterogeneous computing system and electronic equipment, and relates to the technical field of data processing, a first directory controller manages the consistency state of a host end, and a second directory controller manages the consistency state of an equipment end. The consistency maintenance operation is firstly efficiently processed by the corresponding directory controller in the storage domain, cross-device frequent coordination communication is reduced, and when cross-domain data access occurs, the two directory controllers cooperate through an established communication coupling mechanism and execute global consistency maintenance as required. The method not only can adapt to a high-burst and high-parallel access mode of a device end, but also can avoid direct conflicts with a cache management mechanism of a host end, and realizes global consistency through distributed collaboration. The technical problem of performance bottleneck of cache consistency in the heterogeneous system is solved, and the technical effect that the overall data access efficiency of the heterogeneous system is improved while the correctness is maintained is achieved.

The invention discloses a spin lock optimization method and electronic equipment, and the method comprises the steps: creating and initializing a spin lock structural body which comprises a lock holder pointer; when each thread obtains the spin lock, creating a corresponding request node structure body to form a waiting queue; in the waiting queue, determining spin lock holders in the plurality of threads based on the lock holder pointers; and after the processor core corresponding to the spin lock holder executes the critical zone code of the corresponding thread, traversing the waiting queue, reading the critical zone function pointer of each waiting node, and sequentially executing the critical zone code in each request node structure body on the current processor core based on the critical zone function pointer. According to the method, the performance bottleneck of a traditional spin lock in a multi-core environment is broken through, all-around optimization of cache consistency overhead, queue delay, energy efficiency ratio and multi-core expansibility is achieved, and the performance of the spin lock in the multi-core processor environment is remarkably improved.

The invention relates to the technical field of integrated circuits, and discloses a data transmission method and device for interconnection between core particles, the core particles and a processing system.The method is applied to a first core particle and comprises the steps that a protocol layer of the first core particle receives to-be-transmitted data sent by a processor of the first core particle; a protocol layer carries out protocol layer overall packing on data to be transmitted to obtain a protocol layer packet, the protocol layer packet comprises a packet header field and a load area, the packet header field is used for identifying a channel type and a channel signal field of the load area, the channel type comprises at least one monitoring channel used for monitoring cache consistency between core particles, and the monitoring channel is used for monitoring cache consistency between the core particles. The packet header field is used for identifying a channel type and a channel signal field of the load area; and the protocol layer sends the to-be-transmitted data to the second core grain through the link layer and the physical layer of the first core grain based on the protocol layer packet. The problem of cache access consistency of processors among core particles is effectively solved.

The invention discloses a request processing method of a multi-core processor, the multi-core processor, a product and a server, and relates to the technical field of multi-core processors. In the method, a main node queries a directory according to a request and obtains a query result, and based on the query result, different request response strategies are adopted to respond to the request. According to the method, the consistency of the shared caches in the non-inclusion relation is maintained in a directory mode, the utilization rate of the shared caches is increased, and the chip area occupied by the caches is reduced under the condition that the cache capacity is fixed; secondly, based on the shared cache architecture of the non-inclusion relationship, the data is allowed to be stored in the private cache and the shared cache at the same time, so that the problem of excessive data exchange caused by cache position exchange in an exclusive architecture can be avoided, meanwhile, the private cache is allowed to reserve the data which does not exist in the shared cache, and the problem of reverse failure in an inclusion mode is avoided. According to the method, the utilization rate of the shared cache is improved, and the data exchange amount and the maintenance cost of cache consistency are reduced.

The invention discloses an ICS-oriented efficient multi-source data interaction method and system, and relates to the technical field of intelligent power plant ICS data communication. According to the method, interaction variables are limited through a backboard bus agent, and the data interaction security is improved in combination with a dual-access security control mechanism; a multi-link communication architecture fusing optical fiber, 5G and industrial Ethernet is constructed, transmission tasks are dynamically allocated by using an intelligent scheduling algorithm, and a communication procedure and a coding strategy are adaptively adjusted, so that the data transmission efficiency and reliability in different network environments are improved; a distributed cache unit is deployed at each server node, and the data access delay is reduced in combination with a cache consistency regulation and an intelligent scheduling and prefetching mechanism; through an omnibearing fault perception and parallel rapid switching algorithm, rapid takeover under a fault condition is realized, and service continuity is ensured in cooperation with data consistency; the method can be widely applied to industrial control systems with high requirements on data interaction safety, real-time performance and reliability, such as intelligent power plants.

The invention discloses a data processing system, method and device, a medium and a program product in the technical field of computers. In the application, the host and the acceleration device realize cache synchronization and corresponding message notification through the cache coherence protocol, and an interrupt message does not need to be transmitted, so that the data transmission delay between the host and the acceleration device can be reduced, and the data transmission efficiency between the host and the acceleration device can be improved; and meanwhile, by combining a memory direct reading technology, the transmission of data between the host and the acceleration equipment and the data transmission between the host and the third party are accelerated.

The invention provides a multi-core processor chip and a storage access method and device of the multi-core processor chip, and relates to the technical field of computer processors, the multi-core processor chip comprises at least one processor core, the processor core comprises a general processor core, a first address space mapping module and a first core interconnection interface, the universal processor core supports high-speed cache consistency; at least one input / output core grain, wherein the input / output core grain comprises a memory interface, a directory, a second address space mapping module and a second core grain interconnection interface; both the first address space mapping module and the second address space mapping module store an address space mapping table, and the address space mapping table stores a mapping relationship between a memory address accessed by a processor core grain and a memory interface of an input / output core grain; the directory stores cache consistency information of the cache blocks corresponding to the memory interfaces of the input / output core grain and other input / output core grains corresponding to the directory.

The invention discloses a graph database query acceleration method and system. The method comprises the following steps: constructing panoramic query observation data through non-intrusive log interception and structured processing; the query statement is analyzed into an abstract syntax tree, semantic normalization processing is carried out, and a unique hash value is generated; predicting a hotspot query template and high-frequency parameters thereof based on a popularity value score model, and asynchronously preloading a result to a cache; dynamically calculating adaptive survival time for each cache item according to the data change frequency and the access popularity; and constructing a multi-level cache architecture comprising a local cache, a distributed cache and a database built-in cache, and performing intelligent routing and collaborative backfilling based on a hash value. According to the method, intelligent and transparent acceleration of graph database query is realized, the query performance is remarkably improved, the database load is reduced, and the problems of redundancy, high cold start delay and difficulty in balancing cache consistency caused by grammar difference in traditional cache are solved.

The invention provides a method for verifying cache consistency of a multi-core processor, electronic equipment and a storage medium, and the method comprises the steps: generating a model compiled by a target language according to an obtained first conversion rule between any two states of a cache line of the multi-core processor, analyzing the model, and verifying the cache consistency of the multi-core processor; therefore, at least one path of state transition of the cache line is obtained. By generating the excitation corresponding to the at least one path, the excitation is compiled into an executable file, so that the cache consistency of the multi-core processor is verified by running the executable file. Therefore, the generated model written by the target language can automatically generate the incentives for verifying the cache consistency, so that more incentives can be generated, more test scenes can be covered as much as possible, and the cache consistency verification of the multi-core processor is more comprehensive.

The invention discloses a data exchange architecture, system and method capable of realizing cache consistency. The data exchange architecture comprises a data exchange device and a plurality of devices electrically connected with the data exchange device, the data exchange device comprises a shared storage space, a cache state array list and a management module, wherein the shared storage space comprises memory units in one-to-one correspondence with device IDs, the cache state array list comprises the device IDs in one-to-one correspondence with the device IDs and cache state arrays, and the cache state arrays comprise cache states in one-to-one correspondence with the device IDs. The memory unit of which the cache state is exclusively written cannot be written or read by other equipment except the write-in equipment; the memory unit which is in an exclusive writing state in a non-cache state can be written or read by any equipment; other equipment cannot cache the data of the memory unit through the equipment corresponding to the data failure / non-cache; other devices may cache the data of the memory unit for the shared read device through the cache state. According to the invention, the consistency of caches among multiple devices can be realized.

The invention discloses a data processing system, method and equipment, a medium and a program product in the technical field of computers. In the invention, a cache coherence root port of a computing device is connected with a cache coherence sub-port of a memory processing device through a cache coherence protocol, so that the computing device is used for synchronizing a query matrix of a model processing task and a first result output in a key value matrix calculation stage to the memory processing device through the cache coherence protocol; meanwhile, the memory processing device can synchronize the second result to the computing device through the cache coherence protocol, so that rapid data transmission between the computing device and the memory processing device is realized, the memory space of the computing device is saved, the overhead of a host processor in the execution process of the model processing task is reduced, and the performance of the model processing task is improved. And the task processing efficiency of the hardware computing equipment can be improved to a certain extent.

The invention provides a cache consistency processing method and device, equipment and a storage medium, and the method comprises the steps: when a write operation or an atomic operation is carried out on a first copy in any first last-stage cache, forwarding the write operation or the atomic operation to a second last-stage cache, discarding the first copy in the first last-stage cache of the first copy, and storing the first copy in the second last-stage cache of the first copy; and performing write operation or atomic operation on the second copy in the second last-stage cache to obtain a processed second copy. In the technical scheme, write operations or atomic operations in other last-stage caches are all forwarded to the last-stage caches corresponding to the corresponding high-bandwidth memories, so that the last-stage caches are subjected to unilateral operations or atomic operations, tedious consistency steps in the prior art are avoided, the protocol and hardware implementation complexity is greatly simplified, and the implementation efficiency is improved. Therefore, the performance optimization is realized.

The invention provides a multi-core cache consistency maintenance method and device, electronic equipment and a storage medium, and is applied to a multi-core system comprising a plurality of nodes, the nodes comprise at least two cores, each core comprises a first-level cache, and the plurality of cores of the same node share a second-level cache comprising a directory for recording cache line states; the method comprises the steps that a request core sends a first request to a first target core; the request core and the first target core are the same or different cores in the same node; when the first-level cache of the first target core is hit and the cache line state meets the target request requirement, the request core is responded, and the original state of the cache line is maintained; when the first-level cache of the first target core is not hit or the first-level cache is hit but the cache line state does not meet the request requirement, the request core sends a second request to other cores of the same node or a second-level cache of the node; and according to a request result, responding to a request core, and adjusting cache line states in a first-level cache and a second-level cache in the node.

The disclosed method generates a base listen filter (SFT) entry for a coherency particle (cogram) in a proxy cache. The method comprises the following steps: determining the number of agents for storing copies of cogran; comparing a number of agents that store a copy of the cogran with a number of a plurality of agent IDs tracked in a trace information field of the base SFT entry; and in response to determining that the number of agents holding the copy of the cogram is greater than the number of the plurality of agent IDs tracked in the trace information field of the base SFT entry, selecting a second SFT entry as an additional SFT entry configured to store part of a trace vector, where each bit of the trace vector indicates a cache validity state of the cogram of the related agent.

The application relates to the chip technical field and discloses a partition unit, a partition, a chip, a network-on-chip implementation method and a medium. The partition unit comprises the following steps: obtaining an operation type and an access address corresponding to a memory access request through a secondary cache, and forwarding the memory access request to a control module of a directory corresponding to the access address when the operation type is a partial write operation; writing request data corresponding to the memory access request into a small-capacity cache through the control module, reading a target partition unit corresponding to the partition unit from a state recording module, generating a listening request according to the memory access request and sending the listening request to the target partition unit, receiving listening data fed back by the target partition unit, merging the listening data and the request data to generate complete data, and writing the complete data into a memory controller. Hardware support for cache consistency can be provided in an artificial intelligence chip with a multi-core architecture, and a network-on-chip implementation scheme supporting cache consistency is provided.

This application provides a verification system, verification method, apparatus, and related devices. The verification system includes two cache consistency slave device verification units, each configured with a main address region and a mirror address region. The mirror data in the mirror address region of one cache consistency slave device verification unit is the data in the main address region of the other cache consistency slave device verification unit. When a mirroring operation is triggered between the two cache consistency slave device verification units, the correctness of the mirror data in the mirror address region is verified. The verification is determined by comparing the data in the main address region of one cache consistency slave device verification unit with the mirror data in the mirror address region of the other cache consistency slave device verification unit. This application avoids the complex processes of traditional verification, comprehensively reduces verification overhead, and thus improves the verification efficiency of memory address mirroring functionality.

The application discloses a multi-core cache consistency debugging method based on multi-view access and belongs to the field of multi-core processor debugging. The method is characterized in that a target address is specified in a main memory by a host computer through a JTAG debugging interface, five groups of data of CPU view, L1 data cache view, L1 instruction cache view, L2 view and real memory view corresponding to the address are read in turn, whether cache is invalid is judged by comparing data consistency, and a cache level inconsistent is marked. The debugging system comprises a built-in JTAG TAP controller, an enhanced debugging access module, a storage level access arbitrator and a data and state collector. The application realizes direct access of the JTAG interface to data of each level of cache, does not need to modify hardware or disable cache, does not interfere with system operation, can quickly locate cache consistency problems under a multi-core architecture, improves debugging efficiency and accuracy, and is suitable for debugging scenes of large-scale multi-core processors.

The application relates to the technical field of storage systems in computer architecture, and relates to a cache consistency control method and system based on a static memory and electronic equipment. Through a hardware-level cache tag synchronization mechanism, the cache consistency is efficiently maintained, the cache update delay is reduced, the overall data processing speed and performance of the system are improved, protocol parameters are dynamically adjusted through an adaptive optimization strategy, the system can maintain high operation efficiency under different workloads, and the adaptability of the protocol and the system performance are enhanced.

The invention provides a cache consistency test method and device, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps that a target CPU in the system-on-chip is restored to an original environment without consistency maintenance, and a first preset test value is written into a preset memory in the original environment; according to a plurality of consistency maintenance functions corresponding to the target CPU, determining a first parameter data structure set corresponding to the target CPU, executing each first parameter data structure, and obtaining a target value at a preset memory; and determining a consistency maintenance result of the target cache according to the plurality of target values, the first preset test value and the preset parameter data structure corresponding to the target CPU, so that the target parameter data structure which enables the target cache to have consistency can be screened and determined from the first parameter data structure set. And according to the screened target parameter data structure and the preset parameter data structure, testing the consistency of the target cache in the system-on-chip.

The invention provides a distributed cache management method based on a dynamic strategy engine, and relates to the technical field of computer software, and the method comprises the steps: configuring a cache strategy for each tenant through an intelligent cache strategy configuration center, the cache strategy comprises a cache granularity, a cache updating opportunity, a cache life cycle, a cache replacement strategy, a cache updating mode and a cache medium; receiving a cache strategy configuration change through a cache strategy dynamic engine, and performing hot update of the cache strategy based on the tenant identifier; generating cache strategy recommendation based on system runtime indexes and a machine learning algorithm through an intelligent strategy recommendation system; caching strategy gray release is carried out through a multi-dimensional gray release manager based on the user ID range, the regional distribution, the equipment type, the access time and the multi-dimensional configuration of the service module; and the final consistency of the cache and the database is realized based on the message queue through the cache consistency guarantee module.

The application provides a cache consistency test method and device, electronic equipment and a computer readable storage medium, including: obtaining a test sequence of a multi-core cache system; the multi-core cache system includes at least two processor cores and a multi-level cache; the test sequence includes operation instructions for each processor core; inputting the test sequence into a simulation model, processing the test sequence in turn through the multi-level cache of the simulation model according to a cache consistency protocol, and outputting a state checkpoint of the multi-core cache system; the state checkpoint is used to represent the current cache state of each processor core in the multi-core cache system; testing the cache consistency of the multi-core cache system according to the state checkpoint, and obtaining a test result. The embodiment of the application can improve the reliability and comprehensiveness of the cache consistency test.