76 results about "Cache consistency" patented technology

The invention relates to a final-stage cache design method based on near memory calculation, and belongs to the technical field of near memory calculation. And compared with a near memory processor near a traditional main memory, data access and calculation can be carried out more quickly, and the calculation throughput rate can be improved. According to the near storage calculation, a near storage processor and a last-stage cache storage array are directly designed in an integrated mode, faster memory access is achieved through an internal bus interconnection mode, and the problem of a storage wall between the calculation speed and the memory access speed and the problem of a power consumption wall of data handling are relieved to a certain degree. The last-stage cache controller cooperates with the embedded processor, and can dynamically coordinate between a standard cache function and a calculation mode. Through a synchronization mechanism in a last-stage cache controller, a memory access request from a host CPU and a calculation task executed by an embedded processor in a last-stage cache are transparently balanced, so that efficient near-memory calculation under cache consistency is realized.

Disclosed in the present application are a data processing system and method, and a device, a medium and a computer program product in the technical field of computers. The data processing system comprises: at least one processor device and at least one target device connected to the at least one processor device, wherein the processor device and the target device each comprise a consistency function processing device and at least one consistency interface. In the same device, the consistency function processing device is in communication connection with the at least one consistency interface; and two consistency interfaces in different processor devices are in communication connection with each other, two consistency interfaces in different target devices are in communication connection with each other, or two consistency interfaces in any processor device and any target device are in communication connection with each other, such that the cache consistency between different processor devices, the cache consistency between different target devices, or the cache consistency between any processor device and any target device is realized.

Provided in the embodiments of the present application are a server system, a resource scheduling method for a server system, and a chip and a chiplet. The server system comprises: a multivariate computing resource pool, a data storage resource pool, a switching module and a control module, wherein the multivariate computing resource pool comprises a general computing resource pool and a heterogeneous computing resource pool, the general computing resource pool comprising a group of general computing units, and the heterogeneous computing resource pool comprising a group of heterogeneous computing units, and the multivariate computing resource pool is connected to the data storage resource pool via the switching module by means of a cache consistency bus inside the server system; the data storage resource pool comprises data storage resources allowed to be shared by multivariate computing resources in the multivariate computing resource pool; and the control module is configured to perform computing power scheduling on the multivariate computing resources in the multivariate computing resource pool, and dynamically allocate the data storage resources in the data storage resource pool to the multivariate computing resources in the multivariate computing resource pool.

The invention discloses a data transmission method and device, an industrial control system, a storage medium and a computer program product, and the method comprises the steps: initializing a continuous physical memory, dividing the continuous physical memory into memory blocks with a fixed size, recording the initial address, size, idle or occupied state of the memory blocks through a red-black tree, and forming a dynamic address pool; the dynamic address pool can realize on-demand allocation of memory blocks and merging and dynamic expansion of adjacent free blocks; the method comprises the following steps: acquiring a load index in real time through an FPGA (Field Programmable Gate Array), triggering interruption based on load grading and predicting a memory demand in combination with a machine learning model, and pre-fetching a memory block from a dynamic address pool to a user mode mapping region before a real-time task initiates a memory allocation request; a user mode atomic operation annular queue is designed, direct data interaction between the X86 and the FPGA is achieved through memory mapping, and a Burst transmission and cache consistency protocol of a hardware bus is combined. According to the scheme, the problem of memory fragmentation is solved, the data transmission delay is reduced, and the CPU occupancy rate is greatly reduced.

The invention discloses a cache maintenance system of a heterogeneous computing system and electronic equipment, and relates to the technical field of data processing, a first directory controller manages the consistency state of a host end, and a second directory controller manages the consistency state of an equipment end. The consistency maintenance operation is firstly efficiently processed by the corresponding directory controller in the storage domain, cross-device frequent coordination communication is reduced, and when cross-domain data access occurs, the two directory controllers cooperate through an established communication coupling mechanism and execute global consistency maintenance as required. The method not only can adapt to a high-burst and high-parallel access mode of a device end, but also can avoid direct conflicts with a cache management mechanism of a host end, and realizes global consistency through distributed collaboration. The technical problem of performance bottleneck of cache consistency in the heterogeneous system is solved, and the technical effect that the overall data access efficiency of the heterogeneous system is improved while the correctness is maintained is achieved.

The invention relates to the technical field of integrated circuits, and discloses a data transmission method and device for interconnection between core particles, the core particles and a processing system.The method is applied to a first core particle and comprises the steps that a protocol layer of the first core particle receives to-be-transmitted data sent by a processor of the first core particle; a protocol layer carries out protocol layer overall packing on data to be transmitted to obtain a protocol layer packet, the protocol layer packet comprises a packet header field and a load area, the packet header field is used for identifying a channel type and a channel signal field of the load area, the channel type comprises at least one monitoring channel used for monitoring cache consistency between core particles, and the monitoring channel is used for monitoring cache consistency between the core particles. The packet header field is used for identifying a channel type and a channel signal field of the load area; and the protocol layer sends the to-be-transmitted data to the second core grain through the link layer and the physical layer of the first core grain based on the protocol layer packet. The problem of cache access consistency of processors among core particles is effectively solved.

The invention discloses an ICS-oriented efficient multi-source data interaction method and system, and relates to the technical field of intelligent power plant ICS data communication. According to the method, interaction variables are limited through a backboard bus agent, and the data interaction security is improved in combination with a dual-access security control mechanism; a multi-link communication architecture fusing optical fiber, 5G and industrial Ethernet is constructed, transmission tasks are dynamically allocated by using an intelligent scheduling algorithm, and a communication procedure and a coding strategy are adaptively adjusted, so that the data transmission efficiency and reliability in different network environments are improved; a distributed cache unit is deployed at each server node, and the data access delay is reduced in combination with a cache consistency regulation and an intelligent scheduling and prefetching mechanism; through an omnibearing fault perception and parallel rapid switching algorithm, rapid takeover under a fault condition is realized, and service continuity is ensured in cooperation with data consistency; the method can be widely applied to industrial control systems with high requirements on data interaction safety, real-time performance and reliability, such as intelligent power plants.

The invention provides a multi-core processor chip and a storage access method and device of the multi-core processor chip, and relates to the technical field of computer processors, the multi-core processor chip comprises at least one processor core, the processor core comprises a general processor core, a first address space mapping module and a first core interconnection interface, the universal processor core supports high-speed cache consistency; at least one input / output core grain, wherein the input / output core grain comprises a memory interface, a directory, a second address space mapping module and a second core grain interconnection interface; both the first address space mapping module and the second address space mapping module store an address space mapping table, and the address space mapping table stores a mapping relationship between a memory address accessed by a processor core grain and a memory interface of an input / output core grain; the directory stores cache consistency information of the cache blocks corresponding to the memory interfaces of the input / output core grain and other input / output core grains corresponding to the directory.

The invention discloses a graph database query acceleration method and system. The method comprises the following steps: constructing panoramic query observation data through non-intrusive log interception and structured processing; the query statement is analyzed into an abstract syntax tree, semantic normalization processing is carried out, and a unique hash value is generated; predicting a hotspot query template and high-frequency parameters thereof based on a popularity value score model, and asynchronously preloading a result to a cache; dynamically calculating adaptive survival time for each cache item according to the data change frequency and the access popularity; and constructing a multi-level cache architecture comprising a local cache, a distributed cache and a database built-in cache, and performing intelligent routing and collaborative backfilling based on a hash value. According to the method, intelligent and transparent acceleration of graph database query is realized, the query performance is remarkably improved, the database load is reduced, and the problems of redundancy, high cold start delay and difficulty in balancing cache consistency caused by grammar difference in traditional cache are solved.

The invention provides a cache consistency processing method and device, equipment and a storage medium, and the method comprises the steps: when a write operation or an atomic operation is carried out on a first copy in any first last-stage cache, forwarding the write operation or the atomic operation to a second last-stage cache, discarding the first copy in the first last-stage cache of the first copy, and storing the first copy in the second last-stage cache of the first copy; and performing write operation or atomic operation on the second copy in the second last-stage cache to obtain a processed second copy. In the technical scheme, write operations or atomic operations in other last-stage caches are all forwarded to the last-stage caches corresponding to the corresponding high-bandwidth memories, so that the last-stage caches are subjected to unilateral operations or atomic operations, tedious consistency steps in the prior art are avoided, the protocol and hardware implementation complexity is greatly simplified, and the implementation efficiency is improved. Therefore, the performance optimization is realized.

The disclosed method generates a base listen filter (SFT) entry for a coherency particle (cogram) in a proxy cache. The method comprises the following steps: determining the number of agents for storing copies of cogran; comparing a number of agents that store a copy of the cogran with a number of a plurality of agent IDs tracked in a trace information field of the base SFT entry; and in response to determining that the number of agents holding the copy of the cogram is greater than the number of the plurality of agent IDs tracked in the trace information field of the base SFT entry, selecting a second SFT entry as an additional SFT entry configured to store part of a trace vector, where each bit of the trace vector indicates a cache validity state of the cogram of the related agent.

The application relates to the chip technical field and discloses a partition unit, a partition, a chip, a network-on-chip implementation method and a medium. The partition unit comprises the following steps: obtaining an operation type and an access address corresponding to a memory access request through a secondary cache, and forwarding the memory access request to a control module of a directory corresponding to the access address when the operation type is a partial write operation; writing request data corresponding to the memory access request into a small-capacity cache through the control module, reading a target partition unit corresponding to the partition unit from a state recording module, generating a listening request according to the memory access request and sending the listening request to the target partition unit, receiving listening data fed back by the target partition unit, merging the listening data and the request data to generate complete data, and writing the complete data into a memory controller. Hardware support for cache consistency can be provided in an artificial intelligence chip with a multi-core architecture, and a network-on-chip implementation scheme supporting cache consistency is provided.

This application provides a verification system, verification method, apparatus, and related devices. The verification system includes two cache consistency slave device verification units, each configured with a main address region and a mirror address region. The mirror data in the mirror address region of one cache consistency slave device verification unit is the data in the main address region of the other cache consistency slave device verification unit. When a mirroring operation is triggered between the two cache consistency slave device verification units, the correctness of the mirror data in the mirror address region is verified. The verification is determined by comparing the data in the main address region of one cache consistency slave device verification unit with the mirror data in the mirror address region of the other cache consistency slave device verification unit. This application avoids the complex processes of traditional verification, comprehensively reduces verification overhead, and thus improves the verification efficiency of memory address mirroring functionality.

The application discloses a multi-core cache consistency debugging method based on multi-view access and belongs to the field of multi-core processor debugging. The method is characterized in that a target address is specified in a main memory by a host computer through a JTAG debugging interface, five groups of data of CPU view, L1 data cache view, L1 instruction cache view, L2 view and real memory view corresponding to the address are read in turn, whether cache is invalid is judged by comparing data consistency, and a cache level inconsistent is marked. The debugging system comprises a built-in JTAG TAP controller, an enhanced debugging access module, a storage level access arbitrator and a data and state collector. The application realizes direct access of the JTAG interface to data of each level of cache, does not need to modify hardware or disable cache, does not interfere with system operation, can quickly locate cache consistency problems under a multi-core architecture, improves debugging efficiency and accuracy, and is suitable for debugging scenes of large-scale multi-core processors.

The application relates to the technical field of storage systems in computer architecture, and relates to a cache consistency control method and system based on a static memory and electronic equipment. Through a hardware-level cache tag synchronization mechanism, the cache consistency is efficiently maintained, the cache update delay is reduced, the overall data processing speed and performance of the system are improved, protocol parameters are dynamically adjusted through an adaptive optimization strategy, the system can maintain high operation efficiency under different workloads, and the adaptability of the protocol and the system performance are enhanced.

The invention provides a cache consistency test method and device, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps that a target CPU in the system-on-chip is restored to an original environment without consistency maintenance, and a first preset test value is written into a preset memory in the original environment; according to a plurality of consistency maintenance functions corresponding to the target CPU, determining a first parameter data structure set corresponding to the target CPU, executing each first parameter data structure, and obtaining a target value at a preset memory; and determining a consistency maintenance result of the target cache according to the plurality of target values, the first preset test value and the preset parameter data structure corresponding to the target CPU, so that the target parameter data structure which enables the target cache to have consistency can be screened and determined from the first parameter data structure set. And according to the screened target parameter data structure and the preset parameter data structure, testing the consistency of the target cache in the system-on-chip.

The invention provides a distributed cache management method based on a dynamic strategy engine, and relates to the technical field of computer software, and the method comprises the steps: configuring a cache strategy for each tenant through an intelligent cache strategy configuration center, the cache strategy comprises a cache granularity, a cache updating opportunity, a cache life cycle, a cache replacement strategy, a cache updating mode and a cache medium; receiving a cache strategy configuration change through a cache strategy dynamic engine, and performing hot update of the cache strategy based on the tenant identifier; generating cache strategy recommendation based on system runtime indexes and a machine learning algorithm through an intelligent strategy recommendation system; caching strategy gray release is carried out through a multi-dimensional gray release manager based on the user ID range, the regional distribution, the equipment type, the access time and the multi-dimensional configuration of the service module; and the final consistency of the cache and the database is realized based on the message queue through the cache consistency guarantee module.

The application provides a cache consistency test method and device, electronic equipment and a computer readable storage medium, including: obtaining a test sequence of a multi-core cache system; the multi-core cache system includes at least two processor cores and a multi-level cache; the test sequence includes operation instructions for each processor core; inputting the test sequence into a simulation model, processing the test sequence in turn through the multi-level cache of the simulation model according to a cache consistency protocol, and outputting a state checkpoint of the multi-core cache system; the state checkpoint is used to represent the current cache state of each processor core in the multi-core cache system; testing the cache consistency of the multi-core cache system according to the state checkpoint, and obtaining a test result. The embodiment of the application can improve the reliability and comprehensiveness of the cache consistency test.

The invention belongs to the technical field of cache consistency maintenance, and particularly relates to a directory updating method and device for maintaining cache consistency, a medium and a program product. The directory updating method for maintaining the cache consistency comprises the following steps: in response to a cache consistency maintenance operation initiated by a current processor core, obtaining a target cache block targeted by the cache consistency maintenance operation and first target core information of the current processor core; determining a target directory table item corresponding to the target cache block; obtaining a current recording mode of the target directory table item for shared information; and updating the target directory table item according to the first target kernel information and the current recording mode. Therefore, the cache blocks needing to maintain the cache consistency can be determined by a more efficient method when the cache consistency is executed, and the data sharing and interaction efficiency is greatly improved.

The invention relates to the technical field of electric digital data processing, and discloses an edge computing network collaborative scheduling system for high-speed rail platform end security response sinking, which comprises a processor core used for processing a security task; the data acquisition module acquires a video data stream; the scheduling distribution module calculates a bit rate change parameter and predicts a load, and issues a storage isolation control word containing a task identifier and a spatial index when an emergency condition is met; the memory management module intercepts the addressing request and modifies a page table entry memory attribute bit to configure a private address field; the cache consistency filtering module recognizes the memory access state, the hardware level shields a cache line state sniffing request generated by a consistency protocol, through silent isolation of the physical level, micro-architecture level performance degradation caused by the inter-core consistency protocol is eliminated, and it is ensured that the security algorithm processing time delay can be predicted in the complex interference environment.

The application discloses a kind of dynamic rights allocation method, device and equipment based on user contribution value and medium.The method is captured by front-end system user interaction behavior event, is forwarded to B system event hub after being verified and enhanced by A system, then asynchronously is delivered to message queue and is handled.Consumption end calculates contribution value variation according to dynamically configured rule base table, supports positive and negative adjustment of civilization contribution value and platform contribution value.System uses MySQL and Redis double storage architecture, and guarantees data consistency under high concurrency by atomic operation.Based on formula β (i)=U (i) / (G (t)-G (0)) Real-time calculation user contribution proportion, provide proportion type rights release, ladder type ranking empowerment, threshold type screening incentive Three allocation strategies.Through event-driven architecture and cache consistency algorithm, millisecond-level contribution value update and second-level proportion accounting are realized.The application solves the problems of single contribution measurement mechanism, rights allocation rigidity and calculation performance bottleneck in traditional integral system.

The application relates to the technical field of electric digital data processing, and discloses an edge algorithm network cooperative scheduling system for high-speed rail platform end safety response sinking, which comprises a processor core used for processing a safety task; a data acquisition module used for acquiring a video data stream; a scheduling and distribution module used for calculating a bit rate change parameter and predicting a load, and used for issuing a storage isolation control word containing a task identifier and a space index when a burst condition is met; a memory management module used for intercepting an addressing request and modifying a page table item memory attribute bit to configure a private address domain; and a cache consistency filtering module used for identifying a memory access state, and used for shielding a cache line state sniffing request generated by a consistency protocol at a hardware level; the application eliminates micro-architecture level performance attenuation caused by inter-core consistency protocols through physical layer silence isolation, and ensures the predictability of safety algorithm processing delay in a complex interference environment.

The application discloses a data processing system, method, device, medium and program product in the computer technical field. In the application, the acceleration device provides a remote direct data access module and an extension memory module of a host computer, so that the host computer creates multiple queue pairs in the extension memory module to solve the problem of insufficient queue pairs and expand the number of queue pairs; when the host computer confirms that the queue pairs corresponding to a target port for communication with a third-party device are insufficient, the target queue pairs are selected from the extension memory module and configured to the target port, so that the on-demand dynamic allocation of the queue pairs is realized; after the target queue pairs are updated, the host computer synchronizes the target queue pairs to the acceleration device by using a cache consistency protocol, so that the acceleration device uses the remote direct data access module and the target queue pairs to improve the data transmission efficiency between the host computer and the acceleration device.

This invention discloses a distributed storage management device and computing device for multi-core systems. The distributed storage management device includes a DVM proxy module, a DVM remote sending module, and a DVM remote receiving module, each deployed in each core. The DVM proxy module receives DVM request messages containing invalidation address information submitted by the core node in its core, and uses a distributed broadcast mechanism to send the DVM request messages to the core nodes and IO nodes of its core and other cores, thereby invalidating the invalidation addresses carried in the DVM request messages to achieve a unified memory view. This invention aims to solve the cache consistency problem of invalidating large areas of address space data in multi-core systems, including broadcasting invalidation information of DVM operations, avoiding deadlocks in DVM synchronization operations between multiple cores, and optimizing the excessively long execution latency of DVM operations in multi-core scenarios.

The invention relates to an MIPS multiprocessor system based on a CXL interface and computer equipment. The system comprises: at least one MIPS processor core; the consistency management module is connected with each MIPS processor core through an MCP bus, and the consistency management module is used for managing the internal cache consistency of each MIPS processor core; and the CXL controller is integrated in the consistency management module and is used for managing the cache consistency between the MIPS multiprocessor system and the external heterogeneous CXL equipment based on a CXL protocol. The consistency management module of the system internally manages the internal cache consistency of each MIPS processor core, and externally realizes the cache consistency between the MIPS multiprocessor system and an external heterogeneous CXL device through the CXL controller, so that a double-level consistency architecture is realized, and the processing performance of a heterogeneous computing unit is improved.

The application discloses a kind of graphic processor, cache data sharing method, equipment, medium and program product, it is related to processor technical field, by setting and computing core one-to-one corresponding first cache, and by interconnection interface unit constructs the two-way communication link of each first cache and central tag buffer, with the global tag table of all first cache data block tag information is recorded, when first cache receives the read data request of connected computing core and local does not store target data block, other first cache where target data block is located can be positioned by central tag buffer, direct data transmission between first cache is realized via interconnection interface unit, without relying on second cache transfer, reduce the access pressure of second cache, solve bandwidth bottleneck problem, shorten data transmission path, reduce data access delay, avoid the complex design brought by traditional cache consistency protocol, improve cache resource utilization, optimize the overall operating performance of graphic processor.

A computer device with a Computer Express Link (CXL) connection between a storage subsystem and a host system, and with memory access queues that are at least partially configured in the storage subsystem. The storage subsystem can attach a portion of its fast random-access storage as a storage device to the host system over the connection. One or more memory access queues can be configured in the storage device. The host system can use a cache-coherent memory access protocol to communicate memory access messages over the connection to the storage subsystem's random-access storage. Optionally, the host system can have storage with secondary memory access queues that can be used to access the storage services of the storage subsystem over the connection using a data storage access protocol.

The invention discloses a formalized verification system for a multi-core processor system. The formalized verification system comprises a state extraction module, a verification attribute extraction module, a functional model construction module and a formalized verification module. According to the method, verification personnel are helped to exclude non-ideal parts in a circuit through an error occurrence point of a counter-example precise positioning system, and model detection has the advantages of high automation degree, capability of generating a counter example and support of full-state space search, so that the method is most suitable for function and safety verification in an integrated circuit design stage and targeted positioning of a necessary state; and carrying out simplified model construction on the functional model. According to the automatic method, the problem of state explosion of a traditional cache consistency verification method is relieved to a great extent, verification attributes are simplified through attribute extraction, and the time overhead of the verification process is effectively reduced.

The invention provides a cache optimization method and device for an RISC-V multi-core processor. The cache optimization method comprises the following steps: identifying a shared variable generated by a transmission side RISC-V processor and read by a receiving side RISC-V processor in a software code; the receiving side RISC-V processor allocates a cache reserved space corresponding to the special address identifier in a local cache according to the configuration information; constructing an address mapping table according to the configuration information and the special address identifier; querying an address mapping table according to the target address; and if the target address is queried to be the special address identifier, transmitting the data from the transmission side register file to the cache reserved space corresponding to the receiving side through a direct cache link. According to the invention, a special direct cache data transmission link is constructed, and a producer-consumer model is adopted on the link to replace a traditional global cache consistency protocol, so that the problem of consistency traffic overload in a multi-core system is greatly relieved, and the overall efficiency of the system is improved.