123results about How to "Shorten the verification cycle" patented technology

The invention discloses a highly automated intelligent contract formal verification system and method. The method includes the following steps: step 001, converting an intelligent contract function requirement description document into an intelligent contract function requirement specification document described in a non-natural language, wherein the content of intelligent contract function requirement specification document includes target contract function specification description and security attribute description; step 002, creating a formal validation rule model library; step 003, automatically modeling the contract source code and/or bytecode by an automated modeling tool; step 004, parsing the abstract syntax tree generated in step 003, and allocating memory addresses for constantsand variables in the code; step 005, performing formal proof. The invention is adapted to program codes written in a plurality of high-level programming languages and also adapted to a plurality of formal languages, and simultaneously provides two automatic modeling modes of source code modeling and bytecode modeling, so that modeling can be carried out according to different modeling requirements of users, and the verification efficiency is further improved.

The invention discloses an automotive suspension test bed, relates to the technical field of fatigue verification for an automotive suspension and provides the automotive suspension test bed which is simple in structure, high in strength and capable of shortening the development and verification period of the automotive suspension and reducing test expenditures. The automotive suspension test bed comprises a plurality of stand columns, wherein a clamp plate with the height and the angle adjustable is installed on each stand column, and a calibrating mark is further arranged on each stand column and used for calibrating the installation position of the corresponding clamp plate. The automotive suspension test bed further comprises a loading mechanism used for being connected with a loading device, the stand columns are assembled with an automotive frame through the clamp plates in a matched and connected mode, the loading mechanism is connected with a brake disc on the frame, and the direction of the loading device is controlled so that the loading mechanism can perform suspension endurance verification under different working conditions. The automotive suspension test bed is mainly used in tests of fatigue verification for the automotive suspension.

The invention provides a correctness verifying method of a cache consistency protocol. After a computer enters an operating system, the complexity of a core and the application of the operating system is higher; the action of a processor is not easy to control accurately; therefore, in order to keep verification correctness, a verifying program for the cache consistency protocol is necessary to embed in a systematic procedure; the program is embedded in a BIOS (basic input/output system) code; after the initialization of a memory subsystem is completed at the initialization initial stage of the system, the verifying program is started to be executed; the verifying program needs to be capable of accurately controlling actions of each processor of the system, supports a user to select a verification item to be particularly executed, and feeds back a verification result to the user; by using the method, the verification of the correctness of the cache consistency protocol is realized at a system level; all application scenes of a real system can be completely covered; the disadvantages that a conventional verifying method based on an analog way is low in efficiency and poor in verification coverage rate are made up; the design period and the verifying period of an inter-domain cache consistency chip of the processor can be shortened; the one-time taping-out mission success rate of the chip can be guaranteed effectively; and therefore, the correctness verifying method has an extremely wide development prospect and an extremely high technical value.

The invention provides an FPGA-based algorithm library simulation and verification platform implementation method. The implementation method comprises the following steps: firstly, according to requirements of nuclear power station safety level control system application, implementing all the algorithm blocks through FPGA basically; secondly, producing a simulation excitation vector of each algorithm block; thirdly, if an algorithm block needs to be added, only adding algorithm block content and a corresponding simulation vector on the verification platform, and then modifying a configuration file; and fourthly, carrying out comparison analysis on a simulation result output by a simulation tool and a result generated by a simulator. The implementation method provided by the invention has the advantages that all the algorithm blocks are unified into the same interface, and the algorithm blocks can be automatically called only by modifying the configuration file once the algorithm block or the simulation vector needs to be added, so that the aim of automatic simulation is achieved.

The invention discloses a method and device for verifying the RS422 bus data of an aircraft landing gear system. The device comprises a normally closed switch, two RS422 bus data receivers and an information processor. The RS422 bus data between two equipment in the landing gear system mainly transmits landing gear positions and the working states and current parameters of the equipment, and whether the responding conditions of the whole system satisfy design requirements or not when the landing gear positions and control unit parameters change can be verified by the receiving, reconstruction and transferring of the RS422 data between two mutual-backup control units. The method and device has the advantages that the bus data between the equipment is collected in real time, and the safety and integrity of system verification are guaranteed.

The invention discloses a flexible joint analog device with adjustable gaps of a space manipulator and relates to a flexible joint analog device. The flexible joint analog device with adjustable gaps of the space manipulator solves the problems that an existing space manipulator flexible joint analog device is difficult in achieving an analog test with large flexible loads and adjustable joint gaps, and a test verification period is long and cost is huge. One end of a driving connection rod is connected with a plate-shaped extending shaft in a rotating mode, and the other end of the driving connection rod is fixedly connected with one end of a flexible shrapnel. The other end of the flexible shrapnel is fixedly connected with the side wall of a load fixed frame, and heavy articles are arranged in the load fixed frame which is fixed on the upper end face of an air floating foot. Two screw fixed seats are symmetrically arranged on the upper end face of a gap adjusting plate with the driving connection rod as a symmetry axis, and each screw fixed seat is provided with a gap adjusting inner hexagon screw. Two force sensors are symmetrically arranged on two side walls of the driving connection rod, and the two force sensors are coaxially arranged with the two gap adjusting inner hexagon screws. The flexible joint analog device with adjustable thee gaps of the space manipulator is used for verifying mechanical properties of the flexible joint analog device.

This invention discloses one new eight bit RISC micro controller frame, which is characterized by the following: the second degree four section streamline structure comprises order process device, data reading device, data computing device, data writing back device and clock generator. The technique achievements are ad following: making each clock non-crossing coupling to ensure the stable clock; each device relies on each other and to pre-process data to improve the structure to realize the high productivity.

The invention discloses a GPDSP (General-Purpose Digital Signal Processor) framework-oriented multi-kernel directory consistency apparatus. The apparatus comprises kernels, an on-chip last-level Cache, an off-chip memory DDR and an on-chip interconnection network. Each kernel comprises DMA and L1D, wherein L1D is a first-level data Cache; the DMA is used for finishing transfer of data between a peripheral and the kernel; the L1D comprises two parallel processing units of Normal Deal and Monitor Deal; the Normal Deal processing unit finishes processing of load and store instructions; and the Monitor Deal processing unit is used for making a response to a monitoring request arrived at any moment, and the processing process is not influenced by the Normal Deal processing unit. The on-chip last-level Cache is connected to the on-chip interconnection network in a distributed way. Data in the off-chip memory DDR is cached in the L1D and the on-chip last-level Cache. The on-chip interconnection network is used for receiving a network request, performing decoding processing first to obtain a destination node and a destination device after receiving the network request, and sending the request to a corresponding position. The apparatus has the advantages of simple principle, convenient operation, high flexibility, wide application range and the like.

The invention discloses a method for extracting a clock tree based on a comprehensive netlist in chip design and application, and relates to the technical field of integrated circuit design. The method comprises the following steps: in a logic synthesis step, obtaining logic synthesis netlist information of a chip top layer and a sub-module, and module information and clock constraint file information of chip segmentation; splicing a clock structure of the whole chip according to the obtained information, and obtaining a clock source from a clock constraint file; based on full-chip clock structure information, performing tracking backwards step by step from a clock source by adopting a recursive algorithm to form a full-chip clock tree network; in the tracking process, determining starting points and ending points of the top-layer clock tree and the sub-module clock tree according to the clock tree tracking path; and after the tracking is finished, classifying the clock structures of the top layer and the sub-modules to form a clock tree implementation guidance file. According to the method, the clock tree verification period is shortened, and the efficiency and correctness of clock tree implementation work are improved.

The invention discloses a derating inspection method, which comprises opening a circuit layout design gear, screening at least one target part number belonging to the target class from a plurality of part numbers (parts number) used in the circuit layout design gear, obtaining the rated voltage value according to the target part number, obtaining the element number of at least one element using the target part number in the circuit layout design gear according to the target part number, obtaining a first connection name (net name) and a second connection name respectively connected with the two ends of the element according to the element name, and judging whether the derating voltage of the element fits for the rated voltage value according to the first connection name and the second connection name.

The invention discloses a high-precision virtual reality intelligent driving simulator group for universal vehicle types and driving scenes, wherein the simulator group comprises a main vehicle simulator single unit, a plurality of traffic vehicle simulator single units, a controller assembly, a sensor in-ring assembly and an actuator in-ring assembly, the main vehicle simulator single unit and the traffic vehicle simulator single unit have the same mechanical structures and are fixedly connected with the ground infrastructure through a lower motion platform assembly, the plurality of trafficvehicle simulator single units are arranged around the main vehicle simulator single unit, the main vehicle simulator single unit and the plurality of traffic vehicle simulator single units are tangent to each other in an enveloping space formed in the space motion limit of the part above the ground infrastructure, the controller assembly is electrically connected with the main vehicle simulator single unit, the plurality of traffic vehicle simulator single units, the sensor in-ring assembly and the actuator in-ring assembly respectively, and the simulator group has the advantages that the corresponding materials of the parts are reasonably selected, and the service life is higher; the test and verification period based on large-scale road tests is shortened.

The invention provides an LED display screen control device and control method capable of carrying out pixel random arrangement, and the device comprises a decoding chip which is used for decoding a video source signal into a TTL video signal; a coding chip which is used for coding the VESA standard signal into a differential signal; a SRAM array which is used for storing TTL video signals; a SPIFLASH which is used for storing an address table; a SDRAM which is used for transferring the address table; an FPGA module which is used for randomly reading the video pixel data stored in the SRAM array according to the address table; and a MCU which is used for configuring and monitoring the coding chip, the decoding chip and the FPGA module. According to the method, the high-bandwidth characteristic of the SDRAM during continuous access and the high-bandwidth characteristic of the SRAM during random access are fully combined, the output picture is changed in the mode that the address table is issued through software, and the display requirement of multi-scene change is met.

The invention discloses LoRa gateway equipment. The gateway equipment comprises a gateway module, wherein the gateway module is wirelessly connected with LoRa terminal nodes through adoption of a starnetwork structure, and receives user data from the LoRa terminal nodes; a LoRa network management server module, wherein the LoRa network management server module provides a UI interface, configuresthe gateway module, and carries out connectivity management, authentication management and grouping management on the LoRa terminal nodes; and a data application server module, wherein the data application server module provides data push service and message subscription and release service for a third party application platform. Through utilization of the gateway equipment, a user does not need to care about a specific establishment process of a LoRa/LoRaWAN wireless network and can rapidly generate own wireless application solution only through call of a standard interface provided by a LoRaad-hoc network, so user product development time and verification period are greatly reduced, and user experience is improved.

The invention provides a system-level verification method of a chip. The system-level verification method comprises the steps of receiving a verification request; confirming a module path and a module name of a to-be-verified module according to the verification request; wherein the to-be-verified module comprises a to-be-rejected module and a to-be-replaced module; analyzing the to-be-verified module by utilizing a rejection script to execute a hollowing operation to obtain a port signal, and generating a hollowing file in combination with the module path and the module name; assigning a value to a port signal in the hollowed-out file to obtain a hollowed-out module; and replacing the to-be-verified module with the hollow module, and adding the to-be-verified module to a simulation script for system-level verification. The verification influence on other modules can be reduced when the to-be-verified module is not completed, and the verification period is shortened. The invention further provides a system-level verification system of the chip, a computer readable storage medium and electronic equipment, which have the above beneficial effects.

The invention discloses gateway equipment for a LoRa self-organized network. The gateway equipment comprises a first class of gateway module for receiving data in parallel through eight LoRa uplink channel multi-spreading factors; at least one second class of gateway module for sending data in parallel through a LoRa downlink channel; a 4G module and an Ethernet interface for connecting the internet and connecting the NS/AS server of the cloud side through a wire way and a wireless way. Through the gateway equipment provided by the invention, a user can quickly generate the own wireless application solution by only calling a standard interface provided by the LoRa self-organized network without concerning the specific construction process of the LoRa/LoRaWAN wireless network, the user product development time and the verification cycle are greatly shortened, and the user experience is improved.

A design method of a contact type card verification system based on an FPGA (field programmable gate array) belongs to the technical field of verification of integrated circuit chips, aims to solve problems of high complexity of verification operation, slow simulation speed of software, insufficient reliability and the like of verification of integrated circuits in the prior art, and is applied to integrated circuit design. The verification system based on the FPGA adopts the design of a contact type card as a verification object, and has the advantages of high reliability, fast simulation speed, high portability and reconfigurability and the like, problems of high test complexity, slow simulation speed, insufficient reliability, complication in modification and the like in traditional verification of the integrated circuits are solved, and a new solution can be provided for verification technology of the integrated circuit design.