Verification platform and verification method of system-on-chip

Abstract

The invention discloses a verification platform and a verification method of a system-on-chip. The method comprises the following steps: establishing a simulation verification environment of the system-on-chip; creating a bus function model unit, and binding the bus function model unit to the same interface, connected with the bus, of the central processing unit; creating a general verification methodology test instance, and executing the general verification methodology test instance through the bus function model unit to realize the test of the system-on-chip; creating a plurality of software test examples; and compiling the plurality of software test instances, and executing the plurality of compiled software test instances by the central processing unit to realize the test of the system-on-chip.

Description

Technical field [0001] The present invention generally relates to the field of simulation verification, and in particular, to a verification platform and a verification method of a system-level chip. Background technique [0002] SOC (System On Chip, System-level chip) technology refers to integrating central processor unit (CPU) and input / output (I / O) peripherals, memory, and other functional peripherals to a piece of chip. SOC technology can effectively reduce product area, improve product performance, reduce product power consumption, and improve product reliability, so a wide range of applications. However, due to the cost of the chip, in order to ensure the functionality and performance of the SOC chip, there is a need for a large amount of adequate verification before the chip flow. [0003] The verification of the SOC chip in the prior art has two ways. One is to perform test modes through the CPU, which must be compiled, loaded (boot), etc. in the verification platfor...

AI Technical Summary

Problems solved by technology

Moreover, the development of processes such as compiling and loading software codes takes a certain amount of time, which delays the start of verification

It is very time-consuming for the CPU to execute software codes, and each software code must run the same loading program before entering the test program, which affects the verification progress

The other is to execute the test mode through UVM case (Universal Verification Methodology case, universal verification methodology test case), which cannot reuse the software test program

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