254results about How to "Reduce verification time" patented technology

The simulation consists of a front-end simulation and a back-end simulation. The front-end simulation can use an equivalent model at different abstraction level, or a simulation model for the back-end simulation. The back-end simulation uses the simulation result of front-end simulation so that it can run one or more simulation runs sequentially or in parallel. Alternatively, models at lower level of abstraction are simulated together with a model at higher level of abstraction in parallel using two or more simulators.

The invention discloses a highly automated intelligent contract formal verification system and method. The method includes the following steps: step 001, converting an intelligent contract function requirement description document into an intelligent contract function requirement specification document described in a non-natural language, wherein the content of intelligent contract function requirement specification document includes target contract function specification description and security attribute description; step 002, creating a formal validation rule model library; step 003, automatically modeling the contract source code and/or bytecode by an automated modeling tool; step 004, parsing the abstract syntax tree generated in step 003, and allocating memory addresses for constantsand variables in the code; step 005, performing formal proof. The invention is adapted to program codes written in a plurality of high-level programming languages and also adapted to a plurality of formal languages, and simultaneously provides two automatic modeling modes of source code modeling and bytecode modeling, so that modeling can be carried out according to different modeling requirements of users, and the verification efficiency is further improved.

A magneto-resistive read/write tape head is provided for reading and writing to tape media along a tape head face. The tape head comprises a plurality of modules, each module comprising a read element and a write element spaced apart and terminating at the tape head face and formed over a substrate. The read element comprises a soft film bias layer and a hard film bias layer butted against the SFB layer. The write element comprises two pole tips spaced apart by a gap. The tape head further includes a plurality of activating conducting coil turns operatively associated with the write element and covered by a cross-linked photoresist and positioned between the gap and one of the pole tips and set back from the tape head face. The tape head has at least one of the following elements: (a) a wear shield between the read element and the write element for limiting wear of the gap between the two pole tips, the wear shield being grounded for decoupling read and write functions of the tape head, for allowing same module read/servo/write functions simultaneously, and for grounding static charge from the tape media; (b) a layer of electrically conductive and corrosion-resis tant material, such as rhodium, under the hard film bias layer to reduce its resistance; and (c) a non-activating dummy coil turn closer to the pole tips than the activating coil turns for defining a forward termination of the cross-linked photoresist between the activating coil turns and the tape head face to thereby provide improved ease of processability.

The invention provides a universal platform of verifying compatibility between an intellectual property (IP) core and an advanced microcontroller bus architecture (AMBA) bus interface, which comprises a functional simulation tool, an AMBA bus infrastructure, a third-party verification IP core, a controller, a driver, a stimulus, a checker, an advanced peripheral bus (APB) bridge, an advanced high-performance bus (AHB) master interface, an AHB slave interface and an APB slave interface, wherein all the modules are connected to form an integrated coordinating verification environment by adopting a verification component and hierarchical packaging and interconnections ways provided by a SystemVerilog language and advanced verification methodology (AVM). The platform can verify the compatibility of different types of IP core interfaces, and the development time and cost of the verification platform and a verification method are reduced. The invention also provides the universal method for verifying the compatibility between the IP core and the AMBA bus interface. In the method, excitation is produced more normatively, scientifically and accurately, unnecessary iteration is reduced and the verification time is shortened.

The invention relates to a semi-physical simulation testing table of a network control system of a high-speed motor train unit train. The semi-physical simulation testing table comprises a model management unit, a real device and a model unit, wherein the real device and the model unit communicate with the model management unit. The semi-physical simulation testing table has the following obvious advantages in train control algorithm and control logic verification and optimization: lowering the research and development cost: by the establishment of the semi-physical simulation testing table of a high-speed trainset control and management system (TCMS), the research and development period is shortened, the research and development cost is lowered; shortening the development and manufacturing period: the establishment of the semi-physical simulation testing table of the high-speed TCMS contributes to the shortening of the debugging time on the train.

Methods of verifying a program state may be provided for a non-volatile memory device including a multi-bit memory cell transistor providing more than two different program states. More particularly, the multi-bit memory cell transistor may be programmed from a first program state to a second program state, and a reference memory cell corresponding to the second program state may be selected. After programming the multi-bit memory cell transistor to the second program state and after selecting the reference memory cell corresponding to the second program state, a current flowing through the multi-bit memory cell transistor programmed to the second memory state and a current flowing through the reference memory cell may be compared. Programming the multi-bit memory cell transistor to the second program state may then be verified responsive to comparing the currents flowing through the multi-bit memory cell and the reference memory cell.

The invention provides a bio-feature verification method and an electronic device. By utilizing environment information of an acquisition environment during bio-feature information acquisition, a proper verification template is selected for verifying the acquired bio-feature information so as to improve the effectiveness of verification processing. The bio-feature verification method comprises the steps of obtaining the bio-feature information of an operation body in an acquisition region of a bio-feature acquisition module; obtaining the environment information of the acquisition environment in which the acquisition region of the bio-feature acquisition module is located; based on the environment information, determining a verification template corresponding to the environment information; and based on the verification template corresponding to the environment information, verifying the bio-feature information.

The invention discloses an automatic chip validation method based on a parameterized IP test case set. The automatic chip validation method is achieved by adding test stimulus of IP test cases to the traditional validation method. The automatic chip validation method includes the following steps: designing the test case set of each IP constituting a chip; setting the parameter of each IP constituting the chip; setting the corresponding test case set according to the parameter definition of each IP during design; testing each IP in the chip on the basis of the set test case set to verify the correctness of the design. The automatic chip validation method can be achieved simply, greatly reduces expenses for re-writing of the test cases for the same IP, and improves the IP-based chip validation efficiency.

The invention discloses a data collection method in a smart power grid based on user privacy protection. The method comprises the following steps that: firstly, a system is initialized; secondly, a smart electric meter sends a plurality of kinds of electricity consumption information of users to a local aggregator; thirdly, the smart electric meter signs the user information and sends the user information to the local aggregator; fourthly, the local aggregator determines the user information and signatures; fifthly, the local aggregator verifies the signatures in batch; sixthly, the local aggregator aggregates total electricity consumption information of all users; seventhly, the local aggregator searches for invalid signatures; eighthly, electric meter fault conditions are processed; and ninthly, user joining and exiting conditions are processed. According to the invention, the collection of plurality of kinds of electricity consumption information is realized, external attackers are resisted, internal attackers can also be resisted, and unforgeability of information is realized, so that the electricity consumption privacy of the users is protected.

Pin placement legality is verified in real-time in a background to reduce a number of input/output assignment analysis runs during a physical design of a programmable logic device. Edited pin properties are checked quickly in the background against certain rules, and results displayed to a user usually before a new pin is edited. Available and legal positions are found and displayed for a selected pin to reduce errors.

The invention provides a distributed public key infrastructure construction method based on an editable blockchain, and belongs to the technical field of public key infrastructure, and the method comprises the following steps: S1, initializing a system; S2, deploying an smart contract; S3, signing and issuing a certificate; S4, updating the certificate; S5, revoking the certificate; and S6, verifying the certificate. Compared with an existing PKI system based on a blockchain, an editable blockchain framework is creatively adopted, a new block does not need to be uploaded during certificate updating and revocation, the storage pressure of a blockchain network can be reduced, the certificate verification time can be shortened, a threshold ring is used for signing and issuing a certificate, and an authentication mechanism is composed of multiple CA nodes; the CA independently audits the operation request for the certificate, and the certificate can be operated only after the CA exceedingthe threshold number passes the auditing, so that the tolerance of the system to a Byzantine node is improved, and the security is relatively high.

A hierarchical power verification system and method creates abstract models of power behavior of modules that it successfully verifies. The abstract models simplify the module definition by omitting internal module details but provide sufficient information for power verification of higher level modules that incorporate this abstracted module. Design blocks are replaced with these abstract power models, resulting in reduced run-time and memory requirements. The power models can include power switches inside the block, related supplies of logic ports, supply power states, system power states, power management devices such as isolation logic and level shifters, feed-through and floating ports. The power model may be expressed either in UPF or as a combination of liberty model and UPF. After replacing modules with abstracted models the HPVS can quickly verify an entire SoC with a small memory footprint. When a user modifies a module, the HPVS need only verify the changed module and related modules at higher levels of module hierarchy.

The invention discloses a method for realizing a microprogrammed control unit (MCU) verification platform based on the verification methodology of a verification methodology manual (VMM). The method comprises the following steps of: inputting all usable application program codes or generating a constraint random instruction by using the platform; realizing a model C of an MCU and providing values of all memory units and special function registers, and calling through a direct program interface (DPI); automatically performing self-checking according to a memory unit model serving as a reference; and describing various functional coverage models and providing a functional coverage result. By the method, a portable, reusable, extensible and fully automatic check MCU verification platform with a hierarchical structure can be established.

The invention discloses an Internet of Things protocol security automatic analysis method and system based on formal verification, and the method comprises the steps: building a security attribute needing to be satisfied by a protocol based on an Internet of Things protocol state machine, and automatically achieving the formal description of an Internet of Things protocol and the security attribute needing to be satisfied by the Internet of Things protocol; modeling attacker ability by applying two attack scenes, and formal verification being realized based on a dynamic priority strategy. According to the Internet of Things protocol security automatic analysis method based on formal verification, protocol state machines, deployed on a plurality of Internet of Things platforms, of MQTT, CoAP and AMQP protocols can be efficiently converted into formal languages, and automatic and systematic security analysis is carried out.

The invention relates to a block chain, which provides a block-chain-based automatic test method and apparatus, , a computer device and a storage medium. The method comprises the following steps: executing a new resource script in an interface script, sequentially calling corresponding resources to create new interfaces, and creating first block chain network resources corresponding to each resource to create new interfaces; determining a corresponding block chain resource creation result according to the returned creation result data; executing a node start script, starting a corresponding block chain node according to the node start script, and accessing the started block chain node into a corresponding channel; executing a running resource script in the interface script, sequentially calling corresponding resource running interfaces, and sequentially running corresponding second block chain network resources; according to the running result data returned by each resource running interface, determining the block chain resource running result is determined, and obtaining the block chain test result according to the block chain resource building result and the block chain resourcerunning result, which can quickly verify the functional usability of the block chain system.