451 results about "Parallel simulation" patented technology

An integrated system is described in which digital image data of a patient, obtained from a variety of image sources, including CT scanner, X-Ray, 2D or 3D scanners and color photographs, are combined into a common coordinate system to create a virtual three-dimensional patient model. Software tools are provided for manipulating the virtual patient model to simulation changes in position or orientation of craniofacial structures (e.g., jaw or teeth) and simulate their affect on the appearance of the patient. The simulation (which may be pure simulations or may be so-called “morphing” type simulations) enables a comprehensive approach to planning treatment for the patient. In one embodiment, the treatment may encompass orthodontic treatment. Similarly, surgical treatment plans can be created. Data is extracted from the virtual patient model or simulations thereof for purposes of manufacture of customized therapeutic devices for any component of the craniofacial structures, e.g., orthodontic appliances.

A method of accessing files located in a computer system, by selecting a plurality of embedded links (such as hypertext links) from one or more pages displayed in a browser window, and processing the plurality of embedded links concurrently. The embedded links may include at least two embedded links from a single page displayed in the browser window, or may include at least one embedded link from a first page and at least one other embedded link from a second page. In one implementation, a pop-up menu is displayed once the links have all been selected, wherein the pop-up menu has a plurality of menu items associated with different types of link processing. The types of link processing include: concurrently displaying pages associated with the plurality of embedded links in a plurality of respective browser windows on the display; concurrently printing pages associated with the plurality of embedded links using a printing device of the computer system; or concurrently downloading pages associated with the plurality of embedded links, to a storage device of the computer system. Selection of the links may be facilitated by allowing the user to switch to a multi-link selection mode.

Provided is a parallel multi-core FPGA digital image real-time zooming processing method and device. The method comprises the steps that original video image data to be processed are acquired firstly. The original video image data are inputted to an FPGA chip and the number of zooming cores is confirmed, and the original video image data are divided into image sub-blocks having the same number with that of the zooming cores. Then the divided data are stored in a buffer, the data in the buffer are returned to the FPGA and parallel zooming processing is performed on each image sub-block via one zooming core respectively so that zooming is completed. All the image sub-blocks after zooming are displayed after splicing processing. The method has certain guiding effect on high throughput and high real-time application of digital video images.

The invention discloses a concurrent multiprocessor virtual machine system supporting CPU simultaneous execution, which comprises a virtual machine and an operating system running on the virtual machine. The virtual machine system can simulate not less than one virtual processor, which comprises a processor concurrent simulation module, a memory management module, an interrupt controlling simulation module and a peripheral simulation module; the machine instruction of the operating system is transferred to the processor simulation module through the memory management module of the virtual machine; the processor simulation module can simulate multiple virtual processors used for executing the operating system instruction translated by an instruction translation module and make the processors concurrently execute; the invention also provides a synchronous and access control algorithm in the concurrent execution process; and the peripheral simulation module and the processor simulation module are coordinated by the interrupt controlling simulation module. The invention has the advantages of suitability for simulating a concurrent execution environment of complete simulating hardware on an SMP server or a multi-core server.

Method and apparatus for simulating a MMC system in an electronic simulator uses a computing unit and a connected input/output interface. The electronic simulator comprises a simulation model of a modular multilevel converter (MMC) system including at least one MMC valve, each MMC valve including a plurality of connected converter-submodules (SMs), each SM preferably comprising at least two controlled switches, a capacitor and auxiliary switches. The inventive approach replaces each MMC valve by an equivalent circuit whereby each SM in the valves may be solved separately. Multiple computing units are used to simulate those SMs in parallel, thus achieving fast or real-time simulation speed. The computing unit may comprise multiple computing means using CPU cores, FPGA or GPU cores and combinations thereof. The present inventive method keeps the model-detail including its precision, and enables a real time simulator to achieve fast or real-time speed for very large MMC system-simulations.

Analog computational arrays for matrix-vector multiplication offer very large integration density and throughput as, for instance, needed for real-time signal processing in video. Despite the success of adaptive algorithms and architectures in reducing the effect of analog component mismatch and noise on system performance, the precision and repeatability of analog VLSI computation under process and environmental variations is inadequate for some applications. Digital implementation offers absolute precision limited only by wordlength, but at the cost of significantly larger silicon area and power dissipation compared with dedicated, fine-grain parallel analog implementation. The present invention comprises a hybrid analog and digital technology for fast and accurate computing of a product of a long vector (thousands of dimensions) with a large matrix (thousands of rows and columns). At the core of the externally digital architecture is a high-density, low-power analog array performing binary-binary partial matrix-vector multiplication. Digital multiplication of variable resolution is obtained with bit-serial inputs and bit-parallel storage of matrix elements, by combining quantized outputs from one or more rows of cells over time. Full digital resolution is maintained even with low-resolution analog-to-digital conversion, owing to random statistics in the analog summation of binary products. A random modulation scheme produces near-Bernoulli statistics even for highly correlated inputs. The approach has been validated by electronic prototypes achieving computational efficiency (number of computations per unit time using unit power) and integration density (number of computations per unit time on a unit chip area) each a factor of 100 to 10,000 higher than that of existing signal processors making the invention highly suitable for inexpensive micropower implementations of high-data-rate real-time signal processors.

Disclosed is a multi-task-based discrete event parallel simulation and time synchronization method. The method comprises: setting a plurality of event managers, wherein each group corresponds to an event manager; synchronizing a plurality of entities in the plurality of event managers by using the only time manager; sending, by each event manager, a time synchronization request to the time manager; traversing, by the time manager, the event managers to select an event manager having a minimum execution time and a highest priority as a global push standard, actively pushing the current simulation time to the time, and notifying the corresponding event manager to be ready to execute the event; and upon completion of event execution, sending, by the event manager, a time synchronization request to the time manager again. According to the present application, a plurality of parallel threads run, thereby preventing the case where the single thread simulation fails to fully use the hardware resources, improving the simulation running efficiency, ensuring that the time management and the synchronization overheads are function calling-level overheads, avoiding cross-progress communication overhead, and improving the time management efficiency in simulation.

In a media server for processing data packets, media server functions are implemented by a plurality of modules categorized by real-time response requirements.

A method and apparatus for digital video capturing and compression supports multi-viewpoint interactive video applications. Multiple (typically hundreds of) video cameras centripetally placed in a three dimensional space acquire real-time visual pictures of the same 3D scene from multiple viewpoints at the rate of 20˜30 frames per second (fps). Parallel Multi-Viewpoint Video Capturing and Compression (PMVCC) supports the operation of the apparatus. In an exemplary realization, a Multi-DSP Array (MDA) architecture uses hundreds of high-performance digital signal processors (DSPs) working in parallel to obtain a sustained computation power of hundreds of GIPS (Giga Instructions Per Second).

The invention discloses a chip multi-core processor clock precision parallel simulation system and a method thereof. The system comprises a management thread of an initialization simulation system; the management thread establishes a core thread according to a core number of a simulation object system or parameters given by a user; and the system is characterized in that: the management thread receives access data events sent by the core thread and a suspended barrier acting on the core thread is set; and when the core thread of the maximum local lock does not receive data when reaching a preset clock period, the core thread moves the suspended barrier to synchronously advance to form a sliding simulation time window. Simulation experiments prove that the system greatly improves the accuracy and simulation performance of the multi-core processor parallel simulation.

The invention discloses a multi-core parallel simulation engine system supporting joint operations. The system solves the problem that the real-time performance of a traditional joint operation system is easily influenced when step length is used to forward logic time. The system includes a model scheduling management module, a thread management module, an external interface management module and a high-level architecture (HLA) management module. According to the system, target nodes are assigned for simulation entities to enable total computation amounts of models on each node to be equivalent; then through the model scheduling management module, a scheduling schedule of each node is generated based on a principle of load balancing, the simulation step length is assigned for the models, and during a simulation process, the scheduling schedule is adjusted and the simulation step length of the destroyed entities and generated new entities is adjusted. The system can autonomously divide the scheduling schedule according to operating cycles of the models and the system step length, allow the entities to use the different physical models or the behavior models according to needs for simulation, and support real-time scheduling of large-scale simulation and the high-fidelity operation models.

The disclosed technology is called VCD on demand. In a typical system, the EDA tool incorporating the VCD on-demand technology has the following high level attributes: (1) RCC-based parallel simulation history compression and recording, (2) RCC-based parallel simulation history decompression and VCD file generation, and (3) On-demand software regeneration for a selected simulation target range and design review without simulation rerun. Each of these attributes will be discussed in greater detail below. When the user selects a simulation session range, the RCC System records a highly compressed version of the primary inputs from the test bench process. The user then selects a narrower region, called the simulation target range, within the simulation session range for a more focused analysis. The RCC System dumps the hardware state information (i.e., primary outputs) of the hardware model into a VCD file. The RCC System then allows the user to proceed directly to view the VCD file from the beginning of the simulation target range without having to rerun the entire simulations from the very beginning of the simulation session range.

The invention discloses a parallel method for simulating and optimizing the computer architecture scheme based on a cluster system, and aims to provide a parallel method for simulating and optimizing the design scheme of the computer architecture. The technical scheme is that a parallel computer system which consists of a main control node and simulation nodes and is provided with a remote command execution environment is firstly built, and a global configuration program, a simulated configuration file generating program, a task dispatching program and a result analyzing program are arranged on the main control node, wherein, the global configuration program is used for arranging global configuration; the simulated configuration file generating program is used for generating all simulated configuration files; the task dispatching program distributes simulation evaluation tasks to each node, controls each simulation node and performs simulation evaluation; and the result analyzing program searches simulation result files sent from the simulation nodes for statistics, screens out optimal configuration parameter values, and outputs a report. By adopting the invention, the time for evaluation and optimization can be reduced, and the selection accuracy is improved.

The invention discloses a refrigerant control method of a parallel multi-split air-conditioner. The method comprises the steps of S1, in a heating mode, comparing the degree of superheat of each outdoor unit with the average degree of superheat of a plurality of outdoor units, S2, when the degree of superheat of the current outdoor unit is overhigh in contrast with the average degree of superheat, increasing the amount of the refrigerant going into the current outdoor unit, and S3, when the degree of superheat of the current outdoor unit is overlow in contrast with the average degree of superheat, reducing the amount of the refrigerant going into the current outdoor unit. In this way, the amount of the refrigerant going into each outdoor unit is decided by comparing the degree of superheat of the current outdoor unit and the average degree of superheat (system); the amount of the refrigerant going into each outdoor unit is adjusted from the overall aspect of the system so that the compressor can be enabled to be within an excellent running range, and therefore, the problems caused by overhigh or insufficient superheat of the compressor can be avoided and the reliability of the multi-split air-conditioner during operation is improved.

Embodiments of the present invention are directed to a method and computer program product for performing physics simulations and graphics processing on at least one graphics processor unit (GPU). Such a method for performing physics simulations and graphics processing on at least one GPU includes the following steps. First, physics simulations are executed on a first device embodied in the at least one GPU. Then, graphics are processed on a second device embodied in the at least one GPU responsive to the physics simulations executed on the first device. In an embodiment, the first device and second device are embodied on a single GPU. In another embodiment, the first device is embodied on a first GPU and the second device is embodied on a second GPU.

The invention discloses a device and method for supporting the parallel simulation and the physical simulation of a wireless sensor network. The device comprises a plurality of sensor nodes, a simulation decluster sensor network, a parallel event scheduler and a data processing platform, wherein the multiple sensor nodes are used to transmit working parameters, map the working parameters into virtual nodes, realize online debugging and integrate to the simulation decluster sensor network; the simulation decluster sensor network is used to establish a model, support the network management, integrate a wireless sensor network which can simulate specific applications in simulation, support online software debugging of the sensor nodes and support actual performance analysis of a simulation actual sensor network; the parallel event scheduler is connected with the communication of the simulation decluster sensor network and is used to complete multithreaded programming, execute the simulation events in parallel and maintain a global event queue; and the data processing platform is in communicating junction with the simulation decluster sensor network and is used to receive, store, analyze and display data. By the device, the wireless sensor network performance and node debugging information in different modeling complexities can be accurately described.

The invention relates to a parallel multi-mode matching method and a system. The system comprises a generation module and a matching module, wherein, the generation module is used for reading a rule set including matching rules; matching rules comprising asterisk wildcards in the rule set are divided into sub rules of the matching rules from the asterisk wildcards; the sub rules exclude the asterisk wildcards; matching rules excluding asterisk wildcards in the rule set are the sub rules of the matching rules; all sub rules are generated into an AC automaton according to AC algorithms and output from the AC automaton; the matching module is used for reading a search object and the AC automaton which is applied to searching according to the AC algorithms; whether the search object matches all sub rules of the matching rules according to the sequence of the sub rules in the matching rules is judged; if so, the search object matches the matching rules, and matching results are output, thereby not only retaining the high efficiency of the AC algorithms, but also matching indefinite rules comprising the asterisk wildcards.

The invention relates to an embedded system simulate platform based on bus model, which leads in the embedded system flexible bus design theory, to realize the uniformity of various embedded system bottom structure, and use a system model language SystemC to build a processor host simulate model and an expansion interface board simulate model. The processor host simulate model comprises an embedded processor function model, an interface bus mission model or a SOC (on-chip system) function model, and an on-chip mission model. The invention uses software/hardware cooperate design and simulation integrated environment to realize the development of embedded system simulation model, and uses a real-time parallel simulation console to realize the parallel execution and detection of embedded system simulation model.

The invention discloses an LXI-based parallel multi-channel reconfigurable instrument, comprising a substrate, an instrument function board, a field programmable gate array (FPGA) logical circuit, a test program set and a Web server, wherein the substrate and the instrument function board are the main components of the reconfigurable instrument and arranged in an instrument case together; the substrate is mainly used for realizing a software function and a hardware logical circuit of the system; and the instrument function board is mainly used for realizing the conversion between analog signals and digital signals. Based on the LXI standard design, the instrument is convenient for secondary development; the instrument has a multi-channel parallel test capacity, and each channel can flexibly change the function of the instrument; and the instrument can be used without installing software and can be operated and configured on line only by a browser.

The invention relates to the computer field, which discloses a parallel simulator and the related method. The parallel simulator and method integrate functions of synchronization, communication and scheduling, etc. in the parallel simulator, so as to form a framework; simultaneously, the invention provides a basic application programming interface API for user, the function of the parallel simulator can be realized when user calls the basic application programming interface API under the precondition that only the framework constraint is satisfied.

A method for predicting seismic safety for extremely large engineering project includes using finite element (FE) preprocessing software to set up FE module, inputting parameters required by active time histories of seism for obtaining mathematical module, transmitting the model and time step length to supercomputer to carry out transient response analysis and model analysis for parallel calculation, sending data back to FE analysis software for following calculation and carry out visual processing by using FE post processing software to read in calculation result .

A system and method for magnetic resonance imaging is disclosed, the MRI apparatus comprising a computer programmed to acquire a plurality of 3D MR data sets, each 3D MR data set acquired using a central transmit frequency and a central receive frequency set to an offset frequency value that is distinct for each 3D MR data set, wherein at least a portion of each 3D MR data set is accelerated k-space data, and wherein at least one of the plurality of 3D MR data sets comprises fully-sampled calibration k-space data lines. The computer is also programmed to determine reconstruction weights from the fully-sampled calibration k-space data lines, reconstruct an image for each 3D MR data set using the reconstruction weights from the fully-sampled calibration k-space data lines to synthesize unacquired data, and generate a composite image from the reconstructed images based on the plurality of 3D MR data sets.

The invention provides a GPU-based Cache simulator and a spatial parallel acceleration method thereof. The Cache simulator comprises a Cache initialization module, a Trace preprocessing module, a Trace radix sorting module, a Cache simulation module and a Cache simulation result summarization and display module. The invention adopts powerful parallel processing resources of the GPU to preprocess memory access sequences, and utilizes the relevance of Cache configuration files to parallel sort the memory access sequences through a radix sorting algorithm operating on the GPU, thereby obtaining continuous memory access sequences mapped in each group and achieving inter-group parallel Cache simulation. Moreover, due to the parallel simulation algorithm with different levels and different grain sizes, the invention effectively reduces the Cache simulation time, improves the Cache simulation efficiency and realizes the accurate simulation of behaviors of the Cache. Moreover, the invention has the advantages of simple development environment and easy implementation.