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76 results about "Giga-" patented technology

Giga (/ˈɡɪɡə/ or /ˈdʒɪɡə/) is a unit prefix in the metric system denoting a factor of a (short-form) billion (10⁹ or 1000000000). It has the symbol G. Giga is derived from the Greek word γίγας, meaning "giant." The Oxford English Dictionary reports the earliest written use of giga in this sense to be in the Reports of the IUPAC 14th Conference in 1947: "The following prefixes to abbreviations for the names of units should be used: G giga 10⁹×."

High speed and efficient matrix multiplication hardware module

A matrix multiplication module and matrix multiplication method are provided that use a variable number of multiplier-accumulator units based on the amount of data elements of the matrices are available or needed for processing at a particular point or stage in the computation process. As more data elements become available or are needed, more multiplier-accumulator units are used to perform the necessary multiplication and addition operations. To multiply an N×M matrix by an M×N matrix, the total (maximum) number of used MAC units is “2*N−1”. The number of MAC units used starts with one (1) and increases by two at each computation stage, that is, at the beginning of reading of data elements for each new row of the first matrix. The sequence of the number of MAC units is {1, 3, 5, . . . , 2*N−1} for computation stages each of which corresponds to reading of data elements for each new row of the left hand matrix, also called the first matrix. For the multiplication of two 8×8 matrices, the performance is 16 floating point operations per clock cycle. For an FPGA running at 100 MHz, the performance is 1.6 Giga floating point operations per second. The performance increases with the increase of the clock frequency and the use of larger matrices when FPGA resources permit. Very large matrices are partitioned into smaller blocks to fit in the FPGA resources. Results from the multiplication of sub-matrices are combined to form the final result of the large matrices.
Owner:HARRIS CORP

Dedicated private network service method having backup and loads-balancing functions

InactiveUS20010047414A1Reduce line costsSecures their privacyDigital data processing detailsDigital computer detailsTraffic capacityPrivate IP
The present invention relates to a service method for a construction of networks having automatic backup and load-balancing upon failures to networks and systems, and more particularly to a dedicated private network service method having a load-balancing function wherein the network backup is available since a bypass path is made to normally operating IDC centers upon failures to a specific IDC of the IDCs dispersed in plural places in a public IP networks by GLB servers, and load-balancing as to entire servers is available by constructing network equipment changeable into a private IP network in case of connecting to the IDC centers, connecting the network equipment by Giga lines, and using dispersed IDCs as a network constructed in one place. Further, the present invention, in a dedicated private network, comprises steps of (1) performing a bypass connection to an IDC normally operated upon a failure of a specific IDC by connecting a user by IDC center in a public IP network by a GLB server upon a user's connection; (2) changing a public IP address to a private IP address upon a connection to the dedicated private network; (3) load-balancing traffic to plural IDC centers after interactively connecting the respective IDC centers by constructing a ring-shape network with the IDC centers of private IP networks connected by Giga lines; and (4) performing the load balancing of servers by identifying server states at SLB servers in the respective IDC centers.
Owner:NITGEN TECH

High Speed and Efficient Matrix Multiplication Hardware Module

A matrix multiplication module and matrix multiplication method are provided that use a variable number of multiplier-accumulator units based on the amount of data elements of the matrices are available or needed for processing at a particular point or stage in the computation process. As more data elements become available or are needed, more multiplier-accumulator units are used to perform the necessary multiplication and addition operations. To multiply an N×M matrix by an M×N matrix, the total (maximum) number of used MAC units is “2*N−1”. The number of MAC units used starts with one (1) and increases by two at each computation stage, that is, at the beginning of reading of data elements for each new row of the first matrix. The sequence of the number of MAC units is {1, 3, 5, . . . , 2*N−1} for computation stages each of which corresponds to reading of data elements for each new row of the left hand matrix, also called the first matrix. For the multiplication of two 8×8 matrices, the performance is 16 floating point operations per clock cycle. For an FPGA running at 100 MHz, the performance is 1.6 Giga floating point operations per second. The performance increases with the increase of the clock frequency and the use of larger matrices when FPGA resources permit. Very large matrices are partitioned into smaller blocks to fit in the FPGA resources. Results from the multiplication of sub-matrices are combined to form the final result of the large matrices.
Owner:HARRIS CORP

Parallel computation management-based autonomous navigation simulation and scheduling management system

The invention discloses a parallel computation management-based autonomous navigation simulation and scheduling management system, which consists of a hardware system and a software system, wherein the hardware system consists of a master control computer, a real-time scheduling computer, a simulation computing node, a real-time communication network and a clock card; the real-time communication network consists of a giga Ethernet network and an infiniband high-performance real-time network; and the software system consists of a supporting operating system, master control end software and real-time scheduling control software. The parallel computation management-based autonomous navigation simulation and scheduling management system ensures the real-time property of a simulation system due to the adoption of the infiniband high-performance real-time network and an REDHAWK real-time operating system, ensures the possibility that the system realizes parallel computations in terms of hardware due to the adoption of a computing server and a blade server, realizes the parallel computations among simulation system models based on a data driving asynchronous pipeline parallel real-time scheduling algorithm, and in combination with the hardware, greatly speeds up the computation of the simulation system and ensures the parallelism and the real-time property of the complex simulation system.
Owner:BEIJING INST OF SPACECRAFT SYST ENG

Method and device for analyzing communication channels and designing wireless networks, in consideration of information relating to real environments

The present disclosure relates to a communication technique for fusing, with an IoT technology, a 5G communication system for supporting a higher data transmission rate than a 4G system, and a system therefor. The present disclosure may be applied to intelligent services, such as smart homes, smart buildings, smart cities, smart cars or connected cars, health care, digital education, retail businesses, and security and safety related services, on the basis of 5G communication technologies and I-T-related technologies. A method for analyzing signal transmission properties in a wireless communication system, according to one embodiment of the present specification, comprises: obtaining first information comprising three-dimensional map information; obtaining second information comprising real environment information from image information relating to the three-dimensional map information; determining locations of a plurality of transmitter candidates on the basis of at least one of the first information and the second information; and performing a ray tracing simulation on the basis of the first information and the second information. The preset research was carried out with the support of the “Cross-ministry Giga Korea Project” of the Ministry of Science, ICT and Future Planning, of the Republic of Korea.
Owner:SAMSUNG ELECTRONICS CO LTD

Timing device and method for automatically capturing 10G EPON (10 Giga Ethernet Passive Optical Network) message

The invention discloses a timing device and method for automatically capturing a 10G EPON (10 Giga Ethernet Passive Optical Network) message and relates to the field of communication. The timing method comprises the following steps: after starting the automatic capturing, counting for a preset time by an absolute clock subjected to time correction of a user/OLT (Optical Line Terminal)/ONU (Optical Network Unit) under an absolute timing capturing mode; starting the 10G EPON message capturing and writing into a capturing cache according to screening conditions; under a relative timing capturing mode, detecting a frame content and a frame state captured by specific starting; starting to count by a timing clock till reaching the time preset by the user; and starting a packet grabbing process and writing into the capturing cache according to screening conditions. According to the timing method provided by the invention, the 10G EPON message can be automatically and accurately captured and analyzed; the space for storing the captured message is reduced by designing accurate timing and filtering conditions; the performance and the use efficiency of a remote dispatcher are promoted; and the intercommunication capacity of different equipment factories is enhanced.
Owner:FENGHUO COMM SCI & TECH CO LTD +1

Capturing circuit and writing control method of 10G EPON (10 Giga Ethernet Passive Optical Network) message

The invention discloses a capturing circuit and a writing control method of 10G EPON (10 Giga Ethernet Passive Optical Network) messages. The writing control method comprises the following steps: receiving EPON messages interacting among 10G EPON OLT (Optical Line Terminal) and ONU (Optical Network Unit) through an optical module and a 10G SERDES (Serializer/Deserializer); combining and triggering message capturing according to set conditions after the decoding at a PCS (Physical Coding Sub-layer); writing the captured message into capturing cache, wherein the steps and formats for storing the capturing frames are as follows: writing 128bit frame data at an even number clock period while a frame envelope is valid; and writing the frame head byte number, the frame end byte number, the reaching time, the frame error indication, CRC (Cyclic Redundancy Check) verification error indication and frame boundary symbol of the frame within a clock period at the frame end. With the adoption of the capturing circuit and the writing control method, continuous EPON messages of 10 G can be captured and analyzed rapidly and precisely; the storage space of the captured message is reduced through specific triggering and screening conditions; the performance and the use efficiency of the remote scheduling are improved; and the inter-compatibility of factories of different equipment is enhanced.
Owner:FENGHUO COMM SCI & TECH CO LTD +1

Implementation method of high-precision time service timing system based on giga AFDX network

The present invention provides an implementation method of high-precision time service timing system based on a giga-AFDX network. The method comprises the steps of: taking the sum of delay parametersas real delay of a RTC frame from a time service terminal to a time served terminal to compensate the clock of the time service through recording of dispatching delay of the RTC frame at a main clocksource device, forward delay of a path switch and technical delay received and processed from the clock device, adding a main timestamp value in the RTC frame extraction frame of time service received by the time served terminal to the calculated and obtained actual delay value transmitted by the RTC frame, and writing the main timestamp value and the actual delay value into a local clock timer,wherein the difference of the main clock timer and the slave clock timer value cannot exceed 100ns in an implementation mode, namely, the synchronous time service precision can reach submicrosecond precision. The implementation method of high-precision time service timing system based on the giga-AFDX network can change the forwarding output mode of the switch of the RTC system in the network system, can change the frame load content at the forwarding port and can recalculate CRC so as to achieve the high-precision performance.
Owner:CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST
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