39 results about "Large matrices" patented technology

The invention relates to the technical field of optical computing, in particular to a large-scale reconfigurable photon large matrix model and architecture. Wherein the model comprises a mixed light calculation sub-model; the large-scale reconfigurable photon large matrix model comprises an acquisition module, a parallel input module and an integration module, and the acquisition module is used for acquiring a first large matrix and an input vector which need to be calculated; the parallel input module is used for inputting the first large matrix and the input vector into the mixed light calculation sub-model of each parallel channel in parallel based on the determined number of the parallel channels to obtain an output vector of each parallel channel; and the integration module is used for integrating the output vectors of the parallel channels to obtain a target output vector. According to the scheme, under the condition that high calculation precision and high data flux are considered, a large-scale general optical matrix operation new normal form is achieved, and therefore a complex optical general calculation task is supported.

The invention relates to the technical field of large-model lightweight fine tuning, and discloses a parallel optimization method of a low-rank adapter and a task awareness scheduling system.The parallel optimization method comprises the steps that an increment matrix of the low-rank adapter is fragmented to a tensor parallel group according to rows, the tensor parallel group comprises a plurality of computing devices, and the computing devices are used for computing the increment matrix of the low-rank adapter; the fragmentation granularity is dynamically determined according to the equipment hardware capability and the dimension of the increment matrix; dynamically scheduling the tasks with strong conflicts to different task parallel groups based on the calculated inter-task gradient conflict coefficient; and for a plurality of tasks scheduled to the same task parallel group, adapter calculation is merged into unified large matrix operation by adopting a micro-batch processing technology, and LayerNorm and adapter projection calculation are merged into a single calculation kernel by adopting a kernel fusion technology. According to the method, communication redundancy and synchronization overhead in distributed training are reduced, task interference during multi-task parallel is effectively eliminated, and the problem of computing resource fragmentation is solved.

The present disclosure relates to the field of optical computing technologies, and particularly to a large-scale reconfigurable diffractive optical computing chip system and architecture. Among them, the system includes: an acquisition module for acquiring a first large matrix and a second large matrix that need to be calculated; a calculation decomposition module for performing calculation decomposition on the first large matrix and the second large matrix to obtain a plurality of decomposed matrices; and a calculation module for performing matrix calculation through a diffractive calculation array based on the plurality of decomposed matrices to obtain a target output result. The present disclosure realizes flexible adjustment of the computing network architecture by flexibly adjusting the diffractive calculation array, so as to break through the computing scale limitation of a single reconfigurable diffractive computing core, and further greatly improve the computing scale, and can be flexibly applied in various large and complex application scenarios.

The invention relates to the technical field of data processing, and discloses a large matrix characteristic decomposition method, system, storage medium and device, the method carries out matrix decomposition based on House holder transformation and Givens transformation, and the problems of low efficiency and the like in the prior art are solved.

The application belongs to the technical field of power systems, and discloses an EIGD time-delay power system stability analysis method and device, wherein the method comprises the following steps: a linear model of the time-delay power system is established, and the differential equation in the model is converted into an abstract Cauchy problem by using an infinitesimal generator; a group of discrete points is selected for each time-delay interval of the time-delay power system, a discrete function space is established according to the discrete points, and the time-delay variable is discretized to generate a low-order partial infinitesimal generator discretization matrix; displacement and inverse transformation are performed on the discretization matrix to obtain an inverse matrix, and the characteristic value of the system is obtained according to the inverse matrix; the characteristic value is checked by using the Newton method to obtain the accurate characteristic value and the characteristic vector, and the stability of the time-delay power system is analyzed and judged. The method solves the problem of large matrix LU decomposition calculation amount in the existing EIGD time-delay power system characteristic value sparse calculation method based on the DDAE model.

A method, device, equipment and medium for optimizing the self-attention of a large model provided by the present invention relate to the field of artificial intelligence technology. The present invention obtains a large KQ matrix obtained after the input sequence passes through the self-attention structure of the large model, and divides the large KQ matrix into several small KQ matrices; performs local attention calculation on each small KQ matrix, and performs a descending order sorting of similarities with other small KQ matrices to obtain a sorted list; for each element in the input sequence, according to the calculated sorted list, selects the local attention corresponding to the top r small KQ matrices in terms of similarity for weighted calculation, as the attention representation of the current element, until all elements of the input sequence are completed, and obtains the optimized attention result of the input sequence. The present invention not only reduces the computational complexity of the model, but also can capture long-distance context information and improve the accuracy of the model.

The invention discloses a linear approximation attention operator acceleration method based on NPU, and the method combines linear approximation attention with an Ascend C programming language, and achieves an Ascend C operator for calculating the linear approximation attention. According to hardware characteristics of the mercuration NPU, optimization of vector calculation is carried out, the number of instructions used for line-by-line summation and division is reduced, and time consumption is reduced; according to hardware characteristics of the mercuric chloride NPU, pipeline parallel optimization is carried out, large matrix multiplication is decomposed into multiple small matrix multiplication and asynchronous matrix multiplication, execution of matrix multiplication and vector calculation tasks can be coordinated more efficiently, and the utilization rate of hardware resources is maximized; cache occupation is optimized according to hardware characteristics of the mercuric chloride NPU, and the number of blocks of matrixes such as Q, K, P, Z and the like can be reduced under some input scales, so that the number of cycles of calculation and carrying is reduced, and the operation time of operators is shortened.

The invention discloses a multi-thread redundancy acceleration method and system based on matrix operator splitting, and belongs to the technical field of high-performance computing and fault-tolerant computing, and the method comprises the steps: for a target large matrix operator, splitting the target large matrix operator into a plurality of sub-matrix blocks with uniform sizes by adopting a partitioning strategy, determining an operation dependency relationship and a data interaction rule of each sub-matrix block; constructing a weighted index method based on output sensitivity and error influence, and realizing quantitative evaluation of the criticality of the sub-matrix blocks; distributing redundant thread pairs for the high-criticality sub-matrix blocks, distributing single-thread execution for the low-criticality sub-matrix blocks, and realizing selective redundancy; after all the threads are executed, the calculation result of each sub-matrix block is recovered, and finally, the results of all the sub-matrix blocks after verification are integrated to obtain the final calculation result of the target matrix operator. According to the method, selective redundancy can be realized, the redundancy calculation overhead is reduced while the calculation reliability is guaranteed, and the overall calculation efficiency is improved.

The invention discloses a multi-quantum gate Kirschner product operation accelerator and method supporting mixing precision, and the method comprises the steps: storing A, B and C quantum gates which need to be operated in a memory in a matrix form; respectively reading data of the matrix A and the matrix B, performing Kirschner product, and storing an operation result in a memory; the Kirschner product operation result is divided into a operation matrixes, Kirschner product of each operation matrix and the matrix C is carried out, a operation results are obtained, and a is the number of data of the matrix A; and rearranging the a operation results to obtain a Kirschner product operation result. According to the method, complex operation required by Kirschner product operation between quantum gates can be better matched, meanwhile, mixing precision is achieved through the multiplication and addition process of the complex operation, cascade connection is supported for a plurality of operation cores, therefore, a large matrix is partitioned, and operation time and resources are reduced.

Fast simultaneous feasibility testing (SFT) for management of an electrical power grid is achieved through various innovations. The computation problem relates to evaluation of candidate solutions for external power flows into a power grid, with respect to predetermined constraints and contingencies. A perturbation approach with precomputation is extended to encompass grid states (e.g. time periods) in addition to contingencies. Advantages derive from: fewer factorizations or inversions of large matrices; decoupling of state-dependent and contingency-dependent perturbations, leaving relatively few perturbations jointly dependent on both state and contingency; or making approximations by discarding small jointly dependent terms. Significant computation reductions allow a single workstation to perform SFT for 36 hours of a day-ahead cycle.

The present invention discloses a method and system for solving the low-rank update of the power system network equation, which relates to the technical field of power systems. By obtaining the node operation data of the power system, the node operation data is used to construct the power system network equation to generate the power system network equation; the nodal admittance matrix in the power system network equation is subjected to hierarchical non-diagonal block low-rank decomposition to construct a left low-rank basis large matrix; based on the left low-rank basis large matrix, the nodal admittance matrix is decomposed to construct a target nodal admittance large matrix; based on the target nodal admittance large matrix, the low-rank solution of the power system network equation is performed to generate the solution data of the power system. The present invention performs low-rank update and solution on the power system network equation based on the hierarchical non-diagonal low-rank structure, and can only update the changed part instead of recalculating the entire system when the parameters or structure of the power system change, and can quickly adapt and reduce the consumption of computing resources, thereby significantly improving the computing efficiency.

This invention relates to the field of traffic safety technology, specifically to an efficient simulation method for quantum systems based on parallel order reduction. The method includes the following steps: receiving the physical parameters of the quantum system and simulation requirements, whereby the physical parameters include electron mass, potential well size, and initial wave packet parameters; and the simulation requirements include simulation physical time and accuracy requirements. Based on the physical parameters, a time-dependent Schrödinger equation describing the dynamic behavior of the quantum system is established, and the Schrödinger equation is rearranged into matrix form using the Kronecker product. This invention utilizes Arnoldi to reduce the order of the matrix-form Schrödinger equation. By reducing the order, the large matrix in the original space is projected into a relatively small subspace, improving the efficiency of the simulation solution. The reduced-order Schrödinger equation is solved using a time-parallel algorithm. This approach overcomes the time step limitation imposed by the CFL condition, ensuring that a stable solution can be obtained with fewer time steps.

The invention belongs to the technical field of deep learning, and provides a large model optimization method and system based on an attention mechanism for solving the problems of large calculation resource consumption, high memory occupation, poor interpretability and the like of a large model. According to the method, K and V parameter matrixes are combined into a large KV matrix, and dimension reduction is carried out by using dynamic adaptive tensor decomposition; adding an interpretation layer mark processing process in each data processing step; an implicit expert collaboration model is adopted, and weight decomposition intermediate calculation is generated through a gating network. Wherein tensor decomposition predicts an optimal rank through an NLP model and a topology model and expands the optimal rank into a third-order tensor; the implicit expert collaboration model shares the basic parameter matrix, and the sub-networks are combined by using gating coefficients and implicit sparsity is realized. Experiments prove that the method can shorten calculation time, reduce memory usage, improve calculation speed, enhance model interpretability and adaptability, and effectively optimize large model performance.

The present invention implements a high-performance batch parallel LU decomposition method based on GPU for small and medium-sized dense matrices of a simulation system. The method includes: S1, calculating the Jacobian matrix of the model unit of the simulation system at each time step, and taking these matrices as sub-matrices, and splicing them into a large matrix H; S2, dividing the internal blocks of each sub-matrix, and allocating a GPU thread group to each sub-matrix according to the size of the blocks; S3, the GPU thread group sequentially completes the selection of the main element of all columns in each diagonal block, the update of the right block of the row where the diagonal block is located, the exchange of the internal column of the diagonal block with the main element column, and the update of all the block data below and below the column where the diagonal block is located in a diagonal order from the upper left to the lower right, thereby completing the LU decomposition of all sub-matrices in the large matrix H. The present invention can increase the performance in an approximately linear trend as the batch number increases, and can accelerate the solution speed when implicitly solving a model containing a large batch of small ordinary differential equations, and effectively shorten the simulation time.

A method for iteratively generating a matrix of base elements that includes forming at least one base matrix, applying modification operators iteratively, which are able to transform the base matrix or any matrix arising therefrom into a modified matrix, applying expansion operators iteratively, which form a larger matrix from a plurality of optionally modified smaller matrices from the preceding iteration by copying, rotation or reflection by virtue of parts of the larger matrix being filled with the optionally modified smaller matrices, performing virtual experiments within the scope of which the properties of a created matrix are examined by systematic creation of values deliberately containing errors from which an error signal is derivable, and in order to create a complex matrix, forming all permutations of next larger matrices by applying expansion operators and then evaluating by means of virtual experiments, the next larger matrices selected with the smallest error signals, and then forming the next larger matrices successively therefrom by applying expansion operators and evaluating by means of virtual experiments until the error signal drops below a given limit.

Techniques for computing matrix operations for arbitrarily large matrices on a limited size hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a limited size hybrid analog-digital matrix processor are described that enable the system to achieve higher energy efficiency, greater physical density, and improved numerical accuracy. In some embodiments, these techniques maximize the prediction accuracy of GEMM-based convolutional neural networks using low-precision data representations.

Modem deep neural network (DNN) models have many layers with a single layer potentially involving large matrix multiplications. Such heavy calculation brings challenges to deploy such DNN models on a single edge device, which has relatively limited computation resources. Therefore, multiple and even heterogeneous edge devices may be required for applications with stringent latency requirements. Disclosed in the present patent documents are embodiments of a model scheduling framework that schedules multiple models on a heterogeneous platform. Two different approaches, model first scheduling (MFS) and hardware first scheduling (HFS), are presented to allocate a group of models for a service into corresponding heterogeneous edge devices, including CPU, VPU and GPU. Experimental results prove the effectiveness of the MFS and HFS methods for improving the inference speed of single and multiple AI-based services.

Embodiments of the present application provide systems and methods for performing matrix-based computations in computing devices, such as an edge computing device, which includes a MAC unit for matrix multiplication, a VEC unit for Softmax operations, and shared on-chip cache memory. The method involves parallel processing of matrix multiplication and Softmax operations to produce intermediate and final result tiles, which may improve memory usage and computational efficiency. Memory constraints are managed using selective overwriting strategies, allowing improved pipelined execution by dynamically reallocating on-chip memory. These techniques may enable reduced latency, improved throughput, and efficient handling of large matrices in machine learning applications, such as attention mechanisms. The method may further employ tiling and adaptive optimization routines to ensure computations fit within on-chip memory, which may reduce the need for off-chip memory access. Embodiments may be useful for AI or machine learning applications in resource-constrained environments.

To provide a method and apparatus for quantization matrix design for transmitting different quantization matrices corresponding to different block sizes, color components and prediction modes.SOLUTION: To more efficiently signal the coefficients of the quantization matrices, in one implementation, a unified matrix identifier matrix Id is used, based on a size identifier (sizeId) that relates to CU size with larger sizes listed first, and a matrix type (matrixTypeId) with luma QM listed first. This single identifier allows referring to any previously transmitted matrix when using prediction (copy), and transmitting larger matrices first to avoid interpolation in the prediction process. When a block uses the Intra Block Copy prediction mode, QM identifier may be derived as if the block uses the INTER prediction mode.SELECTED DRAWING: Figure 11

This invention introduces a parallel matrix multiplication algorithm achieving O(n²) time complexity through: 1. Binary Fusion Technique: Multi-layer bitwise data representation. Vectorized counting-logical operations (AND + popcount). Kronecker-based weighted reconstruction. 2. Key Advantages: Eliminates floating-point rounding errors. Reduces memory bandwidth requirements. Hardware-agnostic design (GPU / FPGA / ASIC compatible). 3. Applications: Machine learning acceleration. Cryptographic systems optimization. Large-scale scientific computing. The algorithm transforms numerical operations into parallel bitwise processes while maintaining full precision. Compared to conventional methods (e.g. Strassen), it demonstrates superior scalability for large matrices without recursive decomposition.

The invention belongs to the technical field related to artificial intelligence, and discloses a rapid decoding method and decoding circuit of a Transform decoder. The fast decoding method comprises the following steps: selecting a plurality of spaced decoding layers as an exit judgment layer, performing reasoning calculation on a token coding vector through the decoding layers in sequence to obtain a reasoning vector, if the token coding vector reaches the exit judgment layer, performing early-quit judgment after the reasoning calculation of the exit judgment layer is completed, using an early-quit matrix for early-quit judgment, and using an early-quit matrix for early-quit judgment; the quit judgment layer judges whether the quit judgment layer can execute quit or not by judging the norm value of the difference between the reasoning vector of the quit judgment layer and the reasoning vector of the previous layer of the quit judgment layer relative to the premature exit matrix, if the premature exit condition is met, reasoning is ended, and otherwise, the quit judgment layer does not execute quit. And continuing to enter the next decoding layer. According to the method, fast and lightweight early-backward judgment in the decoding stage can be realized, and the decoding generation speed of the large model is remarkably improved.

Systems and methods are provided for reducing the computational complexity and all-to-all (A2A) communication within virtual sub-arrays (VSAs) while enabling distributed parallel edge processing. This can help solve the beamforming problem described by The United States Defense Advanced Research Projects Agency (DARPA) state of the art array processor (SOAP) unclassified program. The use of all-digital transmit / receive antenna apertures for adaptive beamforming algorithms necessitate inversion of large matrices. The matrix inversions become intractably difficult for emerging all-digital apertures. This complexity problem associated with large all-digital aperture arrays can be solved with a two-level approach.

This invention introduces a parallel matrix multiplication algorithm achieving O(n²) time complexity through: 1. Binary Fusion Technique: Multi-layer bitwise data representation. Vectorized counting-logical operations (AND + popcount). Kronecker-based weighted reconstruction. 2. Key Advantages: Eliminates floating-point rounding errors. Reduces memory bandwidth requirements. Hardware-agnostic design (GPU / FPGA / ASIC compatible). 3. Applications: Machine learning acceleration. Cryptographic systems optimization. Large-scale scientific computing. The algorithm transforms numerical operations into parallel bitwise processes while maintaining full precision. Compared to conventional methods (e.g. Strassen), it demonstrates superior scalability for large matrices without recursive decomposition.

The invention relates to a method for generating a matrix from basic elements (sensors, antennas, electronics). According to the invention, a base matrix is first formed, which contains at least all base elements once, modification operators, such as rotation and mirroring, are applied iteratively, by means of which the base matrix or a matrix derived from the base matrix can be converted into a modified matrix, expansion operators are applied iteratively, and the modified matrix is converted into a modified matrix, such as rotation and mirroring, by means of which expansion operators, such as rotation and mirroring, by means of rotation and mirroring, by means of rotation and mirroring. The expansion operator forms a larger matrix from a plurality of optionally modified matrices of previous iterations by copying, rotating or mirroring by filling portions of the larger matrix with optionally modified smaller matrices, performing a virtual experiment, and performing a virtual experiment. Wherein the properties of the generated matrix are researched by systematically generating pertinently erroneous values from which error signals can be derived, in order to generate a complex matrix, first all permutations of the next larger matrix are formed by an extension operator and evaluated by a virtual experiment, and then all permutations of the next larger matrix are evaluated by a virtual experiment. Subsequently, a next larger matrix with the minimum error signal is selected, and then the next larger matrix is gradually formed from these matrices by an expansion operator and evaluated by a virtual experiment until the error signal does not exceed a predetermined limit.

The invention relates to a single index quantization matrix design for video encoding and decoding, in particular to different quantization matrices that can be transmitted corresponding to different block sizes, color components, and prediction modes. In order to more effectively signal the coefficients of the quantization matrix, in one implementation, a uniform matrix identifier matrixId is used based on a size identifier (sizeId) related to a first listed larger-sized CU size and a first listed matrix type (matrixTypeId) of the luma QM. For example, a unified identifier is derived as: matrixId = N * sizeId + matrixTypeId, where N is the number of possible type identifiers, e.g., N = 6. This single identifier allows any previously transmitted matrices to be referenced when prediction (replication) is used, and first transmission of the larger matrices avoids interpolation in the prediction process. When a block uses an intra block copy prediction mode, a QM identifier may be obtained as if the block uses an inter prediction mode.

The application discloses a three-dimensional ISAR imaging method based on multi-observation tensor sparse representation, and belongs to the field of inverse synthetic aperture radar imaging. In view of the fact that the existing ISAR imaging technology has low imaging resolution when data is insufficient and low imaging quality when noise is large, the application adopts a multi-observation method, utilizes the correlation between signals of multiple channels, and improves the inclusiveness of data. Compared with a traditional algorithm, the reconstruction effect is better under a small signal-to-noise ratio, the resolution of ISAR imaging is improved, a tensorization method is adopted to directly process three-dimensional data, an inverse matrix of an unfolded large matrix is not needed, the efficiency of the algorithm is improved, the three-dimensional structure information of the reconstructed signal is considered, the imaging accuracy is further improved, and the precision and quality of three-dimensional ISAR imaging are improved. The application realizes three-dimensional ISAR imaging based on multi-observation tensor sparse representation, is suitable for the field of inverse synthetic aperture radar imaging, and improves the imaging precision and imaging quality under a low signal-to-noise ratio.

The invention relates to the technical field of artificial intelligence, in particular to a time series data processing method, an autocorrelation coefficient matrix is a matrix with a larger scale, the scales of the matrix are different along with different values of tau, for example, when tau is equal to 1, a sub-sequence Y1 is equal to x1, x2,..., xL, a sub-sequence Y2 is equal to x2, x3,..., xL + 1, and from the perspective of an original sequence X, the sub-sequence Y1 is equal to x1, x2,..., xL + 1; the difference between the positions of only initial elements of the two subsequences Y1 and Y2 is 1, and so on, when tau is taken as other values, the difference between the initial positions of the subsequences relative to the original sequence X is tau, autocorrelation coefficients among all the subsequences form an autocorrelation coefficient matrix, the autocorrelation coefficients are calculated by taking the autocorrelation coefficients as the core, and the difference between the initial positions of all the subsequences is 1; according to the method, future time sequence data can be predicted according to historical time sequence data, prediction can be performed by integrating multiple time spans, meanwhile, the relationship between the time sequence and historical small sequences of multiple time spans is considered, the minimum unit of a problem is considered to be a small sequence, and the historical small sequences of large time spans can be processed.

The application discloses a signal delay estimation method based on block processing, comprising the following steps: acquiring CSI data and preprocessing (validity test, noise filtering, selecting valid index); obtaining overlapping data blocks by block processing according to a preset block quantity and overlapping ratio; building Hankel matrix and enhancement matrix for each block, and obtaining delay estimation value through singular value decomposition, subspace separation and characteristic polynomial solving; assigning weight to each estimation value in combination with signal quality evaluation; and determining the final result based on the delay estimation value and weight information. In the application, a large matrix is disassembled through block overlapping, the singular value decomposition complexity and storage occupation are reduced, and lightweight hardware is adapted; the processing time consumption is shortened, the real-time demand in multiple scenes is met, the application can be run on ordinary equipment, and positioning deviation caused by delay is avoided.

The application provides a CUDA acceleration-based thin-plate spline deformation parameter matrix calculation and linear interpolation method, which processes three-dimensional to-be-registered feature points and template feature points through three-dimensional affine transformation; the to-be-registered feature points and the template feature points processed by the affine transformation matrix are used to calculate a thin-plate spline deformation parameter matrix based on functions in cublas and cusolver in the CUDA architecture; the to-be-registered three-dimensional image coordinates are inversely transformed by the obtained thin-plate spline deformation parameter matrix, and three-linear interpolation is performed. Through parallelization of large matrix algebra operation and linear interpolation by using the parallel architecture of the GPU, fast calculation of thin-plate spline transformation deformation parameter matrix calculation and linear interpolation is realized, and the running efficiency of the image registration algorithm is effectively improved.

The application discloses an OTA differential method and system based on size matrix cutting and a computer readable storage medium, and the method comprises the following steps: cutting source files and target files by using small matrices to obtain corresponding matrix data blocks, and the file data reading window size of the small matrix is a first window value; eigenvalues of the matrix data blocks of the source files and the target files are calculated respectively, source data feature tables and target data feature tables are constructed, the same matrix small blocks in the target files and the source files are filtered out by comparing the two feature tables; the positions of blank matrices in the target files and the matrix small blocks are marked respectively; the marked target files and the source files are rearranged, and the differential data is differentiated by using a large matrix, and the file data reading window size of the large matrix is a second window value. The application improves the differential data precision and can adapt to diversified upgrade data packets.