49 results about "Large matrices" patented technology

A post-processing-based quantum random number extraction method, apparatus and device, and a computer readable storage medium, the method comprising: converting an analog signal output by a quantum entropy source into a digital signal through a preset high-speed ADC to obtain an original random number; calculating a minimum entropy according to the obtained original random number; updating a preset Toeplitz large matrix by taking the original random number as a seed so as to obtain a first random number sequence and a first extraction proportion output by the updated preset Toeplitz large matrix; according to the minimum entropy and the first extraction proportion, quantum random numbers are extracted from the first random number sequence, the technical problem that in the related technology, a Toeplitz matrix is usually generated through a pseudo-random number generator or cyclically calls stored seeds, and consequently the safety of the extracted random numbers is poor is solved, and the safety of the extracted random numbers is improved. The random number seed of the Toeplitz matrix is updated in real time by using the post-processed random number, the possibility that a random number generator is controlled and cracked by an attacker is avoided, and the security of the random number is guaranteed.

The invention relates to the technical field of optical computing, in particular to a large-scale reconfigurable photon large matrix model and architecture. Wherein the model comprises a mixed light calculation sub-model; the large-scale reconfigurable photon large matrix model comprises an acquisition module, a parallel input module and an integration module, and the acquisition module is used for acquiring a first large matrix and an input vector which need to be calculated; the parallel input module is used for inputting the first large matrix and the input vector into the mixed light calculation sub-model of each parallel channel in parallel based on the determined number of the parallel channels to obtain an output vector of each parallel channel; and the integration module is used for integrating the output vectors of the parallel channels to obtain a target output vector. According to the scheme, under the condition that high calculation precision and high data flux are considered, a large-scale general optical matrix operation new normal form is achieved, and therefore a complex optical general calculation task is supported.

The invention relates to the technical field of large-model lightweight fine tuning, and discloses a parallel optimization method of a low-rank adapter and a task awareness scheduling system.The parallel optimization method comprises the steps that an increment matrix of the low-rank adapter is fragmented to a tensor parallel group according to rows, the tensor parallel group comprises a plurality of computing devices, and the computing devices are used for computing the increment matrix of the low-rank adapter; the fragmentation granularity is dynamically determined according to the equipment hardware capability and the dimension of the increment matrix; dynamically scheduling the tasks with strong conflicts to different task parallel groups based on the calculated inter-task gradient conflict coefficient; and for a plurality of tasks scheduled to the same task parallel group, adapter calculation is merged into unified large matrix operation by adopting a micro-batch processing technology, and LayerNorm and adapter projection calculation are merged into a single calculation kernel by adopting a kernel fusion technology. According to the method, communication redundancy and synchronization overhead in distributed training are reduced, task interference during multi-task parallel is effectively eliminated, and the problem of computing resource fragmentation is solved.

Different quantization matrices may be transmitted corresponding to different block sizes, color components and prediction modes. To more efficiently signal the coefficients of the quantization matrices, in one implementation, a unified matrix identifier matrixId is used, based on a size identifier (sizeId) that relates to CU size with larger sizes listed first, and a matrix type (matrixTypeId) with luma QMs listed first. For example, the unified identifier is derived as: matrixId=N*sizeId+matrixTypeId, where N is the number of possible type identifiers, e.g., N=6. This single identifier allows referring to any previously transmitted matrix when using prediction (copy), and transmitting larger matrices first avoids interpolation in the prediction process. When a block uses the Intra Block Copy prediction mode, QM identifier may be derived as if the block uses the INTER prediction mode.

The invention provides a large model self-attention optimization method and device, equipment and a medium, and relates to the technical field of artificial intelligence. The method comprises the following steps: obtaining a KQ large matrix obtained after an input sequence passes through a large model self-attention structure, and dividing the KQ large matrix into a plurality of KQ small matrixes; carrying out local attention calculation on each KQ small matrix, and carrying out similarity descending sorting on the KQ small matrixes and other KQ small matrixes to obtain a sorting list; and for each element in the input sequence, according to the calculated sorting list, selecting the local attention corresponding to the KQ small matrix with the similarity ranking in the first r to carry out weighted calculation, and taking the local attention as the attention representation of the current element until all the elements of the input sequence are completed, so as to obtain an attention result after the input sequence is optimized. According to the method, the calculation complexity of the model is reduced, remote context information can be captured, and the accuracy of the model is improved.

The present disclosure relates to the field of optical computing technologies, and particularly to a large-scale reconfigurable diffractive optical computing chip system and architecture. Among them, the system includes: an acquisition module for acquiring a first large matrix and a second large matrix that need to be calculated; a calculation decomposition module for performing calculation decomposition on the first large matrix and the second large matrix to obtain a plurality of decomposed matrices; and a calculation module for performing matrix calculation through a diffractive calculation array based on the plurality of decomposed matrices to obtain a target output result. The present disclosure realizes flexible adjustment of the computing network architecture by flexibly adjusting the diffractive calculation array, so as to break through the computing scale limitation of a single reconfigurable diffractive computing core, and further greatly improve the computing scale, and can be flexibly applied in various large and complex application scenarios.

The invention relates to integrated circuit design, in particular to a method for improving large matrix multiplication calculation efficiency by using an on-chip second-level cache, which comprises the following steps of: loading K slices which are not calculated in a matrix to a second-level cache L2buffer; one slice, which is not calculated, in the other matrix is loaded to a first-level cache L1buffer; one slice in the K slices in the second-level cache L2buffer is loaded to the first-level cache L1buffer according to the sequence; matrix multiplication calculation is carried out on the two slices in the first-level cache L1buffer; according to the technical scheme provided by the invention, the transmission frequency of another matrix between the deep learning acceleration core and the external memory is reduced by utilizing the characteristic that the data transmission speed between the first-level cache and the second-level cache in the deep learning acceleration core is far greater than the data transmission speed between the deep learning acceleration core and the external memory; and the calculation efficiency of large matrix multiplication in the deep learning acceleration kernel is improved.

The invention discloses a data processing method, a chip and computing equipment. The chip can automatically detect whether the matrix operation of the two matrixes belongs to the small matrix operation or the large matrix operation without active setting of a user, so that the calculation efficiency of the chip is improved. According to the invention, the chip can dynamically select one computing unit suitable for matrix operation of the two matrixes, so that the chip is prevented from operating various computing units at the same time, and the computing units of different types cannot be in the optimal working frequency at the same moment. Besides, the chip selects the calculation unit with the bit width suitable for the matrix operation of the two matrixes, so that the filling rate of the calculation unit is relatively high, and the calculation efficiency of the processing unit can be improved.

The invention relates to the technical field of data processing, and discloses a large matrix characteristic decomposition method, system, storage medium and device, the method carries out matrix decomposition based on House holder transformation and Givens transformation, and the problems of low efficiency and the like in the prior art are solved.

The application belongs to the technical field of power systems, and discloses an EIGD time-delay power system stability analysis method and device, wherein the method comprises the following steps: a linear model of the time-delay power system is established, and the differential equation in the model is converted into an abstract Cauchy problem by using an infinitesimal generator; a group of discrete points is selected for each time-delay interval of the time-delay power system, a discrete function space is established according to the discrete points, and the time-delay variable is discretized to generate a low-order partial infinitesimal generator discretization matrix; displacement and inverse transformation are performed on the discretization matrix to obtain an inverse matrix, and the characteristic value of the system is obtained according to the inverse matrix; the characteristic value is checked by using the Newton method to obtain the accurate characteristic value and the characteristic vector, and the stability of the time-delay power system is analyzed and judged. The method solves the problem of large matrix LU decomposition calculation amount in the existing EIGD time-delay power system characteristic value sparse calculation method based on the DDAE model.

A method, device, equipment and medium for optimizing the self-attention of a large model provided by the present invention relate to the field of artificial intelligence technology. The present invention obtains a large KQ matrix obtained after the input sequence passes through the self-attention structure of the large model, and divides the large KQ matrix into several small KQ matrices; performs local attention calculation on each small KQ matrix, and performs a descending order sorting of similarities with other small KQ matrices to obtain a sorted list; for each element in the input sequence, according to the calculated sorted list, selects the local attention corresponding to the top r small KQ matrices in terms of similarity for weighted calculation, as the attention representation of the current element, until all elements of the input sequence are completed, and obtains the optimized attention result of the input sequence. The present invention not only reduces the computational complexity of the model, but also can capture long-distance context information and improve the accuracy of the model.

The invention discloses a linear approximation attention operator acceleration method based on NPU, and the method combines linear approximation attention with an Ascend C programming language, and achieves an Ascend C operator for calculating the linear approximation attention. According to hardware characteristics of the mercuration NPU, optimization of vector calculation is carried out, the number of instructions used for line-by-line summation and division is reduced, and time consumption is reduced; according to hardware characteristics of the mercuric chloride NPU, pipeline parallel optimization is carried out, large matrix multiplication is decomposed into multiple small matrix multiplication and asynchronous matrix multiplication, execution of matrix multiplication and vector calculation tasks can be coordinated more efficiently, and the utilization rate of hardware resources is maximized; cache occupation is optimized according to hardware characteristics of the mercuric chloride NPU, and the number of blocks of matrixes such as Q, K, P, Z and the like can be reduced under some input scales, so that the number of cycles of calculation and carrying is reduced, and the operation time of operators is shortened.

The invention discloses a multi-thread redundancy acceleration method and system based on matrix operator splitting, and belongs to the technical field of high-performance computing and fault-tolerant computing, and the method comprises the steps: for a target large matrix operator, splitting the target large matrix operator into a plurality of sub-matrix blocks with uniform sizes by adopting a partitioning strategy, determining an operation dependency relationship and a data interaction rule of each sub-matrix block; constructing a weighted index method based on output sensitivity and error influence, and realizing quantitative evaluation of the criticality of the sub-matrix blocks; distributing redundant thread pairs for the high-criticality sub-matrix blocks, distributing single-thread execution for the low-criticality sub-matrix blocks, and realizing selective redundancy; after all the threads are executed, the calculation result of each sub-matrix block is recovered, and finally, the results of all the sub-matrix blocks after verification are integrated to obtain the final calculation result of the target matrix operator. According to the method, selective redundancy can be realized, the redundancy calculation overhead is reduced while the calculation reliability is guaranteed, and the overall calculation efficiency is improved.

The invention discloses a multi-quantum gate Kirschner product operation accelerator and method supporting mixing precision, and the method comprises the steps: storing A, B and C quantum gates which need to be operated in a memory in a matrix form; respectively reading data of the matrix A and the matrix B, performing Kirschner product, and storing an operation result in a memory; the Kirschner product operation result is divided into a operation matrixes, Kirschner product of each operation matrix and the matrix C is carried out, a operation results are obtained, and a is the number of data of the matrix A; and rearranging the a operation results to obtain a Kirschner product operation result. According to the method, complex operation required by Kirschner product operation between quantum gates can be better matched, meanwhile, mixing precision is achieved through the multiplication and addition process of the complex operation, cascade connection is supported for a plurality of operation cores, therefore, a large matrix is partitioned, and operation time and resources are reduced.

Fast simultaneous feasibility testing (SFT) for management of an electrical power grid is achieved through various innovations. The computation problem relates to evaluation of candidate solutions for external power flows into a power grid, with respect to predetermined constraints and contingencies. A perturbation approach with precomputation is extended to encompass grid states (e.g. time periods) in addition to contingencies. Advantages derive from: fewer factorizations or inversions of large matrices; decoupling of state-dependent and contingency-dependent perturbations, leaving relatively few perturbations jointly dependent on both state and contingency; or making approximations by discarding small jointly dependent terms. Significant computation reductions allow a single workstation to perform SFT for 36 hours of a day-ahead cycle.

The present invention discloses a method and system for solving the low-rank update of the power system network equation, which relates to the technical field of power systems. By obtaining the node operation data of the power system, the node operation data is used to construct the power system network equation to generate the power system network equation; the nodal admittance matrix in the power system network equation is subjected to hierarchical non-diagonal block low-rank decomposition to construct a left low-rank basis large matrix; based on the left low-rank basis large matrix, the nodal admittance matrix is decomposed to construct a target nodal admittance large matrix; based on the target nodal admittance large matrix, the low-rank solution of the power system network equation is performed to generate the solution data of the power system. The present invention performs low-rank update and solution on the power system network equation based on the hierarchical non-diagonal low-rank structure, and can only update the changed part instead of recalculating the entire system when the parameters or structure of the power system change, and can quickly adapt and reduce the consumption of computing resources, thereby significantly improving the computing efficiency.

Different quantization matrices may be transmitted corresponding to different block sizes, color components, and prediction modes. In order to more efficiently signal the coefficients of the quantization matrix, in one implementation, a unified matrix identifier matrixId is used based on the size identifier (sizeId) associated with the CU size of the larger size listed first and the matrix type (matrixTypeId) of the luma QM listed first. For example, the unified identifier is derived as: matrixId=N*sizeId+matrixTypeId, where N is the number of possible type identifiers, for example, N=6. This single identifier allows reference to any previously transmitted matrix when prediction (copying) is used, and transmitting larger matrices first avoids interpolation during the prediction process. When a block uses intra-block copy prediction mode, a QM identifier can be obtained, just as if the block uses inter-prediction mode.

This invention relates to the field of traffic safety technology, specifically to an efficient simulation method for quantum systems based on parallel order reduction. The method includes the following steps: receiving the physical parameters of the quantum system and simulation requirements, whereby the physical parameters include electron mass, potential well size, and initial wave packet parameters; and the simulation requirements include simulation physical time and accuracy requirements. Based on the physical parameters, a time-dependent Schrödinger equation describing the dynamic behavior of the quantum system is established, and the Schrödinger equation is rearranged into matrix form using the Kronecker product. This invention utilizes Arnoldi to reduce the order of the matrix-form Schrödinger equation. By reducing the order, the large matrix in the original space is projected into a relatively small subspace, improving the efficiency of the simulation solution. The reduced-order Schrödinger equation is solved using a time-parallel algorithm. This approach overcomes the time step limitation imposed by the CFL condition, ensuring that a stable solution can be obtained with fewer time steps.

The invention belongs to the technical field of deep learning, and provides a large model optimization method and system based on an attention mechanism for solving the problems of large calculation resource consumption, high memory occupation, poor interpretability and the like of a large model. According to the method, K and V parameter matrixes are combined into a large KV matrix, and dimension reduction is carried out by using dynamic adaptive tensor decomposition; adding an interpretation layer mark processing process in each data processing step; an implicit expert collaboration model is adopted, and weight decomposition intermediate calculation is generated through a gating network. Wherein tensor decomposition predicts an optimal rank through an NLP model and a topology model and expands the optimal rank into a third-order tensor; the implicit expert collaboration model shares the basic parameter matrix, and the sub-networks are combined by using gating coefficients and implicit sparsity is realized. Experiments prove that the method can shorten calculation time, reduce memory usage, improve calculation speed, enhance model interpretability and adaptability, and effectively optimize large model performance.

The present invention implements a high-performance batch parallel LU decomposition method based on GPU for small and medium-sized dense matrices of a simulation system. The method includes: S1, calculating the Jacobian matrix of the model unit of the simulation system at each time step, and taking these matrices as sub-matrices, and splicing them into a large matrix H; S2, dividing the internal blocks of each sub-matrix, and allocating a GPU thread group to each sub-matrix according to the size of the blocks; S3, the GPU thread group sequentially completes the selection of the main element of all columns in each diagonal block, the update of the right block of the row where the diagonal block is located, the exchange of the internal column of the diagonal block with the main element column, and the update of all the block data below and below the column where the diagonal block is located in a diagonal order from the upper left to the lower right, thereby completing the LU decomposition of all sub-matrices in the large matrix H. The present invention can increase the performance in an approximately linear trend as the batch number increases, and can accelerate the solution speed when implicitly solving a model containing a large batch of small ordinary differential equations, and effectively shorten the simulation time.

A method for iteratively generating a matrix of base elements that includes forming at least one base matrix, applying modification operators iteratively, which are able to transform the base matrix or any matrix arising therefrom into a modified matrix, applying expansion operators iteratively, which form a larger matrix from a plurality of optionally modified smaller matrices from the preceding iteration by copying, rotation or reflection by virtue of parts of the larger matrix being filled with the optionally modified smaller matrices, performing virtual experiments within the scope of which the properties of a created matrix are examined by systematic creation of values deliberately containing errors from which an error signal is derivable, and in order to create a complex matrix, forming all permutations of next larger matrices by applying expansion operators and then evaluating by means of virtual experiments, the next larger matrices selected with the smallest error signals, and then forming the next larger matrices successively therefrom by applying expansion operators and evaluating by means of virtual experiments until the error signal drops below a given limit.

Techniques for computing matrix operations for arbitrarily large matrices on a limited size hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a limited size hybrid analog-digital matrix processor are described that enable the system to achieve higher energy efficiency, greater physical density, and improved numerical accuracy. In some embodiments, these techniques maximize the prediction accuracy of GEMM-based convolutional neural networks using low-precision data representations.

Different quantization matrices may be transmitted corresponding to different block sizes, color components and prediction modes. To more efficiently signal the coefficients of the quantization matrices, in one implementation, a unified matrix identifier matrixId is used, based on a size identifier (sizeId) that relates to CU size with larger sizes listed first, and a matrix type (matrixTypeId) with luma QMs listed first. For example, the unified identifier is derived as: matrixId=N*sizeId+matrixTypeId, where N is the number of possible type identifiers, e.g., N=6. This single identifier allows referring to any previously transmitted matrix when using prediction (copy), and transmitting larger matrices first avoids interpolation in the prediction process. When a block uses the Intra Block Copy prediction mode, QM identifier may be derived as if the block uses the INTER prediction mode.

A data processing method, a chip, and a computing device. The chip can automatically detect whether a matrix operation of two matrices is a small matrix operation or a large matrix operation, without requiring active setting performed by a user, such that the computing efficiency of the chip is improved. The chip can dynamically select one type of computing units suitable for a matrix operation of two matrices, thereby avoiding the situation where different types of computing units cannot operate at an optimal operation frequency at the same moment due to a chip simultaneously running multiple types of computing units. In addition, the chip selects a computing unit suitable for a bit width of the matrix operation of the two matrices, such that the filling rate of the computing unit is high, thereby improving the computing efficiency of a processing unit.

The present invention discloses a large-scale MIMO-OFDM cross-subcarrier precoding design method. The present invention designs a transform domain precoding vector, and the precoding vectors on different subcarriers are obtained by transforming the transform domain precoding vector. The number of transform domain precoding vectors to be designed is less than the number of subcarriers, so that the number of parameters required for the precoding design is significantly reduced. Based on the a posteriori beam domain statistical channel model, the transform domain precoding vector is optimized and designed by maximizing the traversal and rate upper bounds. First, a stable solution is obtained by using the traversal and rate minimization function and the minimum and maximum algorithm. Then, the block coordinate descent BCD method and the low-complexity algorithm of power allocation are used to reduce the problem of too large matrix inversion dimension in the stable solution. Compared with the traditional precoding design scheme, the large-scale MIMO-OFDM cross-subcarrier precoding design method proposed by the present invention reduces the computational complexity while maintaining performance close to the optimal sum rate.

Modem deep neural network (DNN) models have many layers with a single layer potentially involving large matrix multiplications. Such heavy calculation brings challenges to deploy such DNN models on a single edge device, which has relatively limited computation resources. Therefore, multiple and even heterogeneous edge devices may be required for applications with stringent latency requirements. Disclosed in the present patent documents are embodiments of a model scheduling framework that schedules multiple models on a heterogeneous platform. Two different approaches, model first scheduling (MFS) and hardware first scheduling (HFS), are presented to allocate a group of models for a service into corresponding heterogeneous edge devices, including CPU, VPU and GPU. Experimental results prove the effectiveness of the MFS and HFS methods for improving the inference speed of single and multiple AI-based services.

Embodiments of the present application provide systems and methods for performing matrix-based computations in computing devices, such as an edge computing device, which includes a MAC unit for matrix multiplication, a VEC unit for Softmax operations, and shared on-chip cache memory. The method involves parallel processing of matrix multiplication and Softmax operations to produce intermediate and final result tiles, which may improve memory usage and computational efficiency. Memory constraints are managed using selective overwriting strategies, allowing improved pipelined execution by dynamically reallocating on-chip memory. These techniques may enable reduced latency, improved throughput, and efficient handling of large matrices in machine learning applications, such as attention mechanisms. The method may further employ tiling and adaptive optimization routines to ensure computations fit within on-chip memory, which may reduce the need for off-chip memory access. Embodiments may be useful for AI or machine learning applications in resource-constrained environments.

To provide a method and apparatus for quantization matrix design for transmitting different quantization matrices corresponding to different block sizes, color components and prediction modes.SOLUTION: To more efficiently signal the coefficients of the quantization matrices, in one implementation, a unified matrix identifier matrix Id is used, based on a size identifier (sizeId) that relates to CU size with larger sizes listed first, and a matrix type (matrixTypeId) with luma QM listed first. This single identifier allows referring to any previously transmitted matrix when using prediction (copy), and transmitting larger matrices first to avoid interpolation in the prediction process. When a block uses the Intra Block Copy prediction mode, QM identifier may be derived as if the block uses the INTER prediction mode.SELECTED DRAWING: Figure 11

This invention introduces a parallel matrix multiplication algorithm achieving O(n²) time complexity through: 1. Binary Fusion Technique: Multi-layer bitwise data representation. Vectorized counting-logical operations (AND + popcount). Kronecker-based weighted reconstruction. 2. Key Advantages: Eliminates floating-point rounding errors. Reduces memory bandwidth requirements. Hardware-agnostic design (GPU / FPGA / ASIC compatible). 3. Applications: Machine learning acceleration. Cryptographic systems optimization. Large-scale scientific computing. The algorithm transforms numerical operations into parallel bitwise processes while maintaining full precision. Compared to conventional methods (e.g. Strassen), it demonstrates superior scalability for large matrices without recursive decomposition.

The invention belongs to the technical field related to artificial intelligence, and discloses a rapid decoding method and decoding circuit of a Transform decoder. The fast decoding method comprises the following steps: selecting a plurality of spaced decoding layers as an exit judgment layer, performing reasoning calculation on a token coding vector through the decoding layers in sequence to obtain a reasoning vector, if the token coding vector reaches the exit judgment layer, performing early-quit judgment after the reasoning calculation of the exit judgment layer is completed, using an early-quit matrix for early-quit judgment, and using an early-quit matrix for early-quit judgment; the quit judgment layer judges whether the quit judgment layer can execute quit or not by judging the norm value of the difference between the reasoning vector of the quit judgment layer and the reasoning vector of the previous layer of the quit judgment layer relative to the premature exit matrix, if the premature exit condition is met, reasoning is ended, and otherwise, the quit judgment layer does not execute quit. And continuing to enter the next decoding layer. According to the method, fast and lightweight early-backward judgment in the decoding stage can be realized, and the decoding generation speed of the large model is remarkably improved.