104 results about "Vector processor" patented technology

A processor may gather raw data comprising a plurality of characteristic data samples of a target user group. The processor may categorize the characteristic data samples into a plurality of user-related classes and triggers. The processor may build an input property graph for each characteristic data sample. The processor may augment the input property graph by a concept of hierarchies. The processor may determine a modification vector from the augmented input property graph. The processor may train an encoder / decoder combination machine-learning system. An embedding vector and a modification vector are used as input for the decoder to build a trained machine-learning generative model.

The invention provides a vector processor, a high-performance processor and electronic equipment. The vector processor comprises a vector program control unit, a plurality of functional units, a matrix register file and a scalar register, wherein the vector program control unit is used for fetching instructions and transmitting the instructions; the vector program control unit interacts with the scalar register; the function unit is used for performing function processing according to the instruction; the matrix register file is used for returning data after receiving the read-write request; rearranging the data and then returning the data; performing read-write interaction with the functional unit; and configuring a configuration register of the vector program control unit through data in the matrix register file. The vector processor provided by the invention can efficiently process the vector data.

The invention discloses an instruction speculation execution method and device of a vector processor and a storage medium. The method comprises the following steps: in response to a vector configuration instruction identified at the front end of a vector processor pipeline, querying a vector prediction configuration table based on instruction information of the vector configuration instruction, and determining a prediction vector configuration parameter; updating a speculative vector state of a back end of the vector processor pipeline based on the predictive vector configuration parameter; performing a speculative process on a vector instruction following the vector configuration instruction based on the speculative vector state; when an actual execution result of the vector configuration instruction is obtained, determining an actual vector configuration parameter; comparing the actual vector configuration parameters with the prediction vector configuration parameters, and when the actual vector configuration parameters are consistent with the prediction vector configuration parameters, determining that speculation processing is effective and updating confidence information in the vector prediction configuration table; and if not, performing a flushing operation on the vector processor assembly line, and updating the vector prediction configuration table by using the actual vector configuration parameters. The processing efficiency of the vector processor assembly line can be improved.

The invention discloses an in-memory computing accelerator, system and method based on a self-adaptive utilization rate. The in-memory computing accelerator based on the self-adaptive utilization rate comprises an in-memory computing processor, a global buffer area, a vector processor, a control module and a configuration register file, the control module and the configuration register file are respectively connected with the in-memory computing processor, the global buffer area and the vector processor, the in-memory computing processor is connected with the global buffer area, and the global buffer area is connected with the vector processor; the in-memory computing processor comprises a plurality of in-memory computing cores, and the plurality of in-memory computing cores form a dynamic parallel structure. According to the method and the device, at least one neural network reasoning calculation process can be executed on the input data aiming at the input data of a certain neural network, and relatively high space utilization rate and time utilization rate can be obtained when facing calculation requirements of different operators, so that efficient acceleration of a diversified neural network model is realized.

The invention relates to the technical field of communication and computer instruction execution and processing, in particular to a polar code encoding and decoding algorithm-oriented special instruction set processor and an implementation method, and a vector processor has efficient parallel computing capability. A coding and decoding algorithm of a polar code relates to parallel computing of a large number of log-likelihood ratios, a vector processor of a special instruction set can process a plurality of LLR values at the same time through a parallel processing unit, and the throughput rate is remarkably improved; special instructions such as polarization shuffling and vector G operation instructions are designed for polarization code encoding and decoding and are used for accelerating algorithm operation. The method can achieve the balance among the performance, the energy efficiency and the flexibility, can adapt to the continuous iteration upgrading of the algorithm due to the programmable and reusable characteristics, and has a good application prospect.

The invention relates to the technical field of processor hardware design, and discloses an ultra-wide RISC-V long vector processor, which comprises a 64-bit scalar RISC-V core and a plurality of vector clusters, wherein each vector cluster comprises an instruction dispatcher and an instruction scheduler, the instruction dispatcher receives vector instructions sent from the scalar core and distributes the instructions to idle processing channels, and the instruction scheduler controls the execution sequence of the instructions in time; each channel is connected with the mask unit, the sliding unit and the vector read-write unit through the full-interconnection crossbar switch, and the full-interconnection crossbar switch and the mask unit carry out conditional execution on elements in a vector instruction based on the mask register. According to the method, the long vector can be quickly and efficiently calculated, the expandability problem of a full interconnection structure is solved by adopting a special layered pipeline interconnection structure, and then long vector support can be carried out on an extended vector processor architecture.

The technical solutions provide ML-based generation of queries and responses for operational frameworks of entities. A processor can identify queries of a processing frameworks for an entity and construct embeddings for the queries. Each embedding can correspond to a vector of a query of the plurality of queries that form a plurality of clusters in a vector space. The processor can generate, for each cluster, using API calls to ML models, a cluster query and a cluster response for the cluster query and store, in a storage, a mapping of each cluster query to each cluster response. The processor can receive, from a client, a request and select, using the mapping, the cluster response based on a relation between the cluster query and the request. The processor can provide, to the client, the selected cluster response responsive to the request.

The invention provides a floating point data parallel computing method and device based on a vector processor and the vector processor, and the method comprises the steps: carrying out vectorization and parallel absolute value calculation on a plurality of pieces of input floating point data, and dividing each piece of data into different computing intervals according to the calculated absolute value; for data located in different calculation intervals, calculating branches in different intervals are combined, branch differences are uniformly represented through symbol transformation variables, and fitting intermediate variables corresponding to all the data are obtained through uniform vector operation instruction parallel calculation; and performing parallel calculation on the basis of the intermediate variable for fitting to obtain a preliminary result corresponding to each data, and correcting the preliminary result according to a symbol of original input data to output a final calculation result in a vector form. According to the method, the problems of low hardware resource utilization rate and poor calculation efficiency of high-precision floating point function calculation realized by adopting a scalar serial processing mode in the prior art are solved.

The vector processor and the data processing method provided by the application add a systolic array acceleration unit in a processor channel to realize the calculation between vectors. The storage unit on the original architecture is fully utilized, the data throughput is increased, the calculation between more vector data is realized, the acceleration effect of the systolic array accelerator is fully utilized, and the utilization rate of the calculation is greatly improved. The systolic array accelerator can support multi-precision and ultra-low bit quantization calculation, improve the efficiency of vector calculation, and the parallelism and scalability of the vector processor can greatly improve the data calculation density, thereby effectively improving the computing power.

A computing system including a hardware accelerator configured to receive vector processing instructions from a processor. The vector processing instructions include an initial read address, an input increment size, and a vector processing operation. During vector processing iterations performed at vector processor tiles included in a vector processor tile array, the hardware accelerator reads vector elements into respective vector processor tiles in an input stream. The vector elements are read into the vector processor tiles from locations in memory that start at the initial read address and advance by the input increment size at successive vector processing iterations. At each of the vector processor tiles, the hardware accelerator computes a vector processing result at least in part by performing the vector processing operation on the vector element read into the vector processor tile. The hardware accelerator outputs the vector processing results from the vector processor tiles in an output stream.

This disclosure relates to a method for generating simulated communication data. A processor trains a model on historical communication data. The model comprises a probability distribution to model time, sender, and recipients and a parameter vector that jointly encodes information from the input event sequence of time value, the sender and the recipients. The probability distribution is based on the parameter vector. The processor generates a collection of simulated communication messages by sampling from the probability distribution to determine a time value, a sender, and recipients of the simulated communication message, wherein the recipients are dependent on the sender of the simulated message. The processor generates a simulated natural language text for the message, which is part of a simulated conversation between the sender and the recipients.

Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus includes a Vector Processor Unit (VPU) comprising: first vector lane circuitry including first matrix multiplier circuitry; second vector lane circuitry including second matrix multiplier circuitry; and interconnect circuitry to connect the first vector lane circuitry and the second vector lane circuitry in a ring structure.

A The present invention relates to a technique for controlling input / output operation of a vector processor, which is designed to optimize vector operation in a mixed precision environment, and to a technique for maximizing data processing performance while minimizing waste of operation resources by improving the data conversion process between the memory and the vector processor.

This invention relates to the field of vector instruction processing technology, specifically to a method and apparatus for processing vector memory access instructions. It includes an instruction issuance step, an address authentication step, whereby if all elements pass authentication, the vector processor sends a commit permission instruction to the scalar pipeline; if any element fails authentication, address authentication is immediately stopped, the location information of the failed element is recorded in an exception location register, and an exception signal is sent to the scalar pipeline, followed by a vector execution step. This invention avoids the blocking problem caused by vector memory access instructions occupying the pipeline for a long time, significantly improves the utilization rate of the scalar pipeline, effectively hides authentication latency, and allows for rapid instruction commit after all elements pass authentication, with the remaining elements then executed without obstruction. Overall memory access latency is significantly reduced, authentication throughput is improved, and the release speed of the scalar pipeline is accelerated.

The invention discloses a database acceleration system and a database acceleration method, and relates to the technical field of data processing, the database acceleration system comprises a central processing unit, an internal bus, a vector processor and a plurality of preset execution units; the central processing unit receives an operation request sent by a user side; analyzing the operation request into an operation plan; calling corresponding target data from a database according to the operation plan; sending the operation plan and the target data to an internal bus; the internal bus is used for sending the operation plan and the target data to the vector processor; the vector processor is used for controlling one or more preset execution units to process the target data according to the operation plan so as to obtain a processing result corresponding to the operation plan; a processing result is returned to the central processing unit; and the central processing unit outputs the processing result to the user side, and through instruction expansion of each preset execution unit, the situation that the specificity of the instruction field is insufficient is avoided, and the operation efficiency of the database is improved.

The application relates to a QR decomposition-based matrix-vector multiplication implementation method based on a vector processor, and the QR decomposition algorithm is a vsip_cqrd_f function in a VSIP library, the VSIP library is a vector, signal and image processing library launched by a GE intelligent platform, and is an open standard application programming interface specially provided for developers who need to use intensive signal and image processing. The technical scheme of the application mainly comprises the following steps: step one, judging whether input matrix C needs transposition conjugate processing and whether the matrix C is on the left or right in matrix multiplication, so as to enter different branch processing; step two, pre-processing the A matrix; step three, adopting different processing schemes according to the quantity size to realize matrix-vector multiplication operation. The application is designed and realized for the QR decomposition-based matrix-vector multiplication in the light of the advantages of the vector processor, such as large storage space, on-chip cache and efficient and fast data transmission, and can play a great advantage in complex matrix operation.

A vector processor includes a mask register configured to hold mask values, an instruction decoder configured to set dependency information included in instruction execution information when a decoded instruction is a subsequent instruction having data dependency with one or more previous instructions, and to set all-set information included in instruction execution information when a decoded instruction sets all of the mask values, a vector processing unit configured to execute vector arithmetic operations based on the instruction execution information, and to store in the data register a result of an arithmetic operation of a vector element corresponding to each mask value that is in a set state, and a dependency reset unit configured to reset the dependency information corresponding to a destination operand of the subsequent instruction and the mask register, when the all-set information is set for the mask register and the mask register is designated by the subsequent instruction.

A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.

A computing system including a hardware accelerator configured to receive vector processing instructions from a processor. The vector processing instructions include an initial read address, an input increment size, and a vector processing operation. During vector processing iterations performed at vector processor tiles included in a vector processor tile array, the hardware accelerator reads vector elements into respective vector processor tiles in an input stream. The vector elements are read into the vector processor tiles from locations in memory that start at the initial read address and advance by the input increment size at successive vector processing iterations. At each of the vector processor tiles, the hardware accelerator computes a vector processing result at least in part by performing the vector processing operation on the vector element read into the vector processor tile. The hardware accelerator outputs the vector processing results from the vector processor tiles in an output stream.

A system for automated, middleware-based intelligent data mapping between heterogeneous enterprise resource planning (ERP) systems and cloud platforms, the system comprising the following: an ERP data acquisition unit with a variety of physical communication ports, selected from Ethernet and serial ports, a network interface controller physically connected to the communication ports, and a DMA (Direct Memory Access) controller configured to transfer raw ERP data packets into a volatile buffer memory without processor intervention; a Semantic Mapping Unit consisting of a Field Programmable Gate Array (FPGA) configured as a lexical analyzer to analyze ERP schema definitions and extract entity descriptors, and a Tensor Processing Unit (TPU) configured to evaluate the semantic similarity between heterogeneous schema elements based on ontological models stored in a non-volatile memory repository; a transformation logic unit comprising a parallelized vector processor configured to perform matrix-based transformations, field normalizations and structural reorganization of ERP data into a harmonized format, and a rule application circuit configured to perform compliance-based anonymization, unit conversions and value scaling prior to cloud distribution; a cloud interface unit comprising a protocol adapter bank with encoders, translators, and message queue writers, wherein the cloud interface unit is coupled with a cryptographic controller configured with a hardware public key infrastructure (PKI) circuit to generate digital signatures and verify integrity codes for all outgoing payloads; and a Feedback Learning Control Unit implemented in the firmware, wherein the engine is electrically coupled to the Semantic Mapping Unit and the Transformation Logic Unit and is configured to monitor error logs, success rates and acknowledgment codes received from the cloud platforms and to update the semantic and transformation rules stored in the non-volatile memory repository accordingly.

The application discloses a vector extension method and a vector processor, defines an interrupt identifier, a vector identifier and a vector state table; initializes the vector identifier to be the same as the interrupt identifier; when the vector processor receives an interrupt entering or exiting instruction, updates the interrupt identifier and the vector state table; according to the interrupt identifier, the vector identifier and the vector state table, judges whether it is necessary to stack or de-stack, when it is judged that it is necessary to stack or de-stack, after receiving a vector instruction, firstly sends the stacking or de-stacking instruction to a later stage pipeline, until the contents needing to be stacked or de-stacked are completely output, then sends the vector instruction to the later stage pipeline, and synchronizes the vector identifier to the interrupt identifier; when it is judged that it is not necessary to stack or de-stack, after receiving the vector instruction, directly sends the vector instruction to the later stage pipeline. The application has simple structure, fast response, lower power consumption, can consider high-efficiency calculation and fast interrupt response, and improves the processor performance.

This application provides a vector mask processing method, apparatus, electronic device, and medium, relating to the field of vector processor technology. The method includes: configuring at least one cache register and a status flag unit for each mask processing thread; responding to a vector mask generation instruction, updating the status flag bit of a target cache register in at least one cache register based on the mask readiness time of the vector mask generation instruction, so as to cache the generated vector mask in the target cache register according to the status flag bit and the mask caching time; responding to a vector mask read instruction, determining whether the target cache register is valid based on the status flag bit, so as to read the vector mask from the target cache register at the mask caching time if the target cache register is valid. This enables read instructions to directly read the vector mask from the cache register without waiting for write instructions to complete the write-back operation of the vector mask, thereby eliminating pipeline stalls caused by write-read dependency conflicts.

Methods and apparatus for interfering with malware using displaced display elements are disclosed. In an example, a processor is configured to change a location of a displayed pointer by a first offset vector from a hidden true pointer. The processor is also configured to change a location of at least one application display element, such as a website “Submit” button, by a second offset vector from a hidden true application element. The first offset vector may have a similar magnitude as the second offset vector but an opposite direction. Changing a location of a pointer and the application element by the offsets enables a user to interact with the application normally. However, the offsets prevent malware or a malicious application from interacting with the application.

The application discloses a kind of semi-precision sparse matrix multiplication multicore parallel method and device for vector processor.There are three kinds of multicore parallel modes according to the dimension of matrix and the number of computing core, suitable for a variety of computing scenarios, make full use of the multicore architecture of vector processor.At the same time, it reduces the calculation redundancy under part of matrix dimension specification, improves the parallelism of sparse matrix multiplication calculation, helps to play the computing performance of vector processor.Each multicore parallel mode is to parallel multiple computing cores in the dimension of weight matrix and dense input matrix, and to realize sparse matrix multiplication in different dimensions.The theoretical calculation efficiency of sparse matrix multiplication calculation in each multicore parallel mode is obtained based on the dimension specification of two matrices.Then the multicore parallel mode with the maximum theoretical calculation efficiency is selected for sparse matrix multiplication calculation.This can automatically adapt the optimal mode to perform calculation, with high versatility and improved calculation efficiency.

This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

This invention discloses a method, apparatus, and medium for implementing a general-purpose fixed-point matrix multiplier based on a high-performance computing architecture in an FPGA. The method includes: designing matrix partitioning strategies at different levels based on the parallelism of the AI ​​engine array resources on the Versal ACAP platform; data scheduling and multiplexing based on the data packet stream and data packet exchange of the AI ​​engine and AXI stream, accelerating the kernel through matrix partitioned multiplication, and designing data scheduling and multiplexing strategies; and implementing a high-throughput vectorized matrix multiplication pipeline on the AI ​​engine vector processor. This invention achieves multi-level partitioning of matrix multiplication based on the AXI stream transport protocol and AI engine array on the Versal ACAP platform, enabling efficient utilization of hardware resources, effectively improving data reuse rate, and achieving high parallelism, while achieving high computational speed under the high-speed clock of the AI ​​engine. This invention can be widely applied in the field of high-performance computing.

Systems and methods for error location and error correction includes receiving, at a processor circuit, an input. The processor circuit generates a set of syndrome coefficients based on the input. The processor circuit generates a parity vector for the input based on the set of syndrome coefficients. The processor circuit determines a number of errors present in the input. Responsive to determining the number of errors present in the input, the processor circuit corrects the number of errors.

This invention discloses a method and system for verifying the functionality of a vector processor. The method unifies matrix, vector, and scalar data formats into a matrix type using a reference model. Multi-input interface data is stored in corresponding data queues in the form of address plus data. The required computational data is extracted according to the current instruction, and unused data is stored back to the original queue. Expected output data at the clock cycle level is generated and compared with the actual output data of the vector processor to determine functional correctness. The system includes an instruction generator module, a controller module, a data generation module, a reference model module, a data collection module, and a data comparator module. This invention can improve the accuracy of vector processor fault location, simplify verification logic, and improve overall verification efficiency.

The invention discloses a hierarchical bypass forwarding method and system for a vector processor, belongs to the technical field of vector processors, and aims to solve the technical problem of how to overcome the defect of low efficiency caused by read-after-write (RAW) data risk in vector operation of the vector processor, effectively reduce pause caused by VRF access delay and improve the reliability of the vector processor. According to the technical scheme, in each vector processing channel of the vector processor, before a front instruction result is written back to a local vector register file of each vector processing channel, a two-stage data forwarding architecture comprising an in-channel bypass unit and a cross-channel bypass network is established by adopting a layered result forwarding network; a front instruction result can be directly transmitted to a subsequent instruction through a two-stage data forwarding architecture comprising an in-channel bypass unit and a cross-channel bypass network; wherein each vector processing channel is internally provided with an in-channel bypass unit.

The embodiment of the invention discloses an inter-particle short-range acting force cooperative calculation method and device, equipment and a medium. The method comprises the following steps: for any reference particle, storing reference particle information and to-be-screened particle information in a memory in the form of a data block; the hardware filter obtains the data blocks from the memory, and screens out screened particles from the to-be-screened particles according to the data blocks and a preset distance range when each data block is obtained; the hardware filter stores the particle information of the reference particles and the screened particles into a target address of a memory, and sends a calculation instruction to a vector processor based on the storage content in the address; and the vector processor determines the short-range acting force between the reference particle and each screened particle according to the calculation instruction and the acting force calculation microcode. On the basis, particle screening and acting force calculation are decoupled, screening while calculation is achieved through a memory, the calculation efficiency is improved, the number of particle pairs obtained after screening and calculation is reduced, the calculation efficiency is further improved, and consumption of calculation resources is reduced.