10 results about "Vector processor" patented technology

This invention relates to the field of vector instruction processing technology, specifically to a method and apparatus for processing vector memory access instructions. It includes an instruction issuance step, an address authentication step, whereby if all elements pass authentication, the vector processor sends a commit permission instruction to the scalar pipeline; if any element fails authentication, address authentication is immediately stopped, the location information of the failed element is recorded in an exception location register, and an exception signal is sent to the scalar pipeline, followed by a vector execution step. This invention avoids the blocking problem caused by vector memory access instructions occupying the pipeline for a long time, significantly improves the utilization rate of the scalar pipeline, effectively hides authentication latency, and allows for rapid instruction commit after all elements pass authentication, with the remaining elements then executed without obstruction. Overall memory access latency is significantly reduced, authentication throughput is improved, and the release speed of the scalar pipeline is accelerated.

The application discloses a vector extension method and a vector processor, defines an interrupt identifier, a vector identifier and a vector state table; initializes the vector identifier to be the same as the interrupt identifier; when the vector processor receives an interrupt entering or exiting instruction, updates the interrupt identifier and the vector state table; according to the interrupt identifier, the vector identifier and the vector state table, judges whether it is necessary to stack or de-stack, when it is judged that it is necessary to stack or de-stack, after receiving a vector instruction, firstly sends the stacking or de-stacking instruction to a later stage pipeline, until the contents needing to be stacked or de-stacked are completely output, then sends the vector instruction to the later stage pipeline, and synchronizes the vector identifier to the interrupt identifier; when it is judged that it is not necessary to stack or de-stack, after receiving the vector instruction, directly sends the vector instruction to the later stage pipeline. The application has simple structure, fast response, lower power consumption, can consider high-efficiency calculation and fast interrupt response, and improves the processor performance.

This invention discloses a method and system for verifying the functionality of a vector processor. The method unifies matrix, vector, and scalar data formats into a matrix type using a reference model. Multi-input interface data is stored in corresponding data queues in the form of address plus data. The required computational data is extracted according to the current instruction, and unused data is stored back to the original queue. Expected output data at the clock cycle level is generated and compared with the actual output data of the vector processor to determine functional correctness. The system includes an instruction generator module, a controller module, a data generation module, a reference model module, a data collection module, and a data comparator module. This invention can improve the accuracy of vector processor fault location, simplify verification logic, and improve overall verification efficiency.

Embodiments of the present application disclose a kind of based on vector processor's multi-matrix double randomization method, device and electronic equipment, comprising: obtaining each to-be-processed matrix in regular floating point tensor, and each vector register in target vector processor;Wherein, the matrix size of each to-be-processed matrix is equal, and the register width of each vector register is equal;When matrix size is less than register width, and the difference between register width and matrix size is greater than the preset difference threshold value, determine the multiple to-be-processed matrices corresponding to each vector register respectively;Each to-be-processed matrix is loaded to corresponding vector register, and each to-be-processed matrix in each vector register is respectively subjected to multi-round double randomization processing, and the target double random matrix corresponding to each to-be-processed matrix is obtained, can make full use of the hardware computing power of vector processor, improve multi-matrix double randomization processing efficiency, reduce multi-matrix double randomization processing overhead.

The application discloses a matrix multiplication processing method and device for a digital signal processor and a medium, and relates to the field of vector processors. In the method, before a matrix multiplication operation is performed, a first matrix is stored in an array memory, and a second matrix and a third matrix are stored in a global shared storage, so that the first matrix is read only once when the matrix multiplication operation is performed, and the second matrix and the third matrix are shared by multiple cores, so that the memory access amount of the digital signal processor is low, and the bandwidth pressure of a double-rate synchronous dynamic random access memory is reduced. In addition, the application further provides a matrix multiplication processing device for a digital signal processor and a computer readable storage medium, which have the same or corresponding technical features and effects as the above-mentioned matrix multiplication processing method for a digital signal processor.

Disclosed herein are vector index registers for storing or loading indexes of true and / or false results of comparison operations in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors.

The application discloses a dynamic reconfigurable vector unit, a vector processor, a chip and an electronic device, and relates to the technical field of reconfigurable computing circuits.The dynamic reconfigurable vector unit comprises a vector register file circuit, a physical total bit length of which is PLEN; a plurality of vector processing channel circuits, which are coupled with the vector register file circuit; a cross-channel switching network circuit, which is connected with the plurality of vector processing channel circuits; and a control logic circuit, which is used for performing the following operations: according to a received configuration value of a block length BLEN, dynamically dividing the plurality of vector processing channel circuits into one or more vector calculation blocks, a bit length of each vector calculation block being equal to BLEN, and a number of vector calculation blocks being equal to PLEN / BLEN; and according to the BLEN value and a calculation instruction, configuring a switching topology of the cross-channel switching network circuit.

This application discloses a data loading method for a RISC-V vector processor, comprising: executing a data preloading instruction to load target data from a first memory to a second memory; wherein the data preloading instruction runs in parallel with ordinary instructions running before the data loading instruction; and executing the data loading instruction to load the target data from the second memory into the RISC-V vector processor. This method can improve the data processing speed and performance of the RISC-V vector processor. This application also discloses a data loading device, apparatus, and computer-readable storage medium for a RISC-V vector processor, all of which have the above-mentioned technical effects.

The application provides a vector reduction instruction execution system, a method and a storage medium, the vector reduction instruction execution system comprises a front-end module and a vector reduction execution module, the vector reduction execution module is used for executing the reduction unit micro-instruction, and the vector reduction execution module comprises a fast reduction tree unit, a multiplexing unit and a binary operation unit. The system considers that different types of binary operation units have different delays, different execution processes of the vector reduction operation are designed for the binary operation units under different delay conditions, operation acceleration is realized based on the hardware of the vector processor, the execution delay of the vector reduction instruction is reduced, and the parallel execution performance of the processor instruction is improved.

Systems and methods for error location and error correction includes receiving, at a processor circuit, an input. The processor circuit generates a set of syndrome coefficients based on the input. The processor circuit generates a parity vector for the input based on the set of syndrome coefficients. The processor circuit determines a number of errors present in the input. Responsive to determining the number of errors present in the input, the processor circuit corrects the number of errors.