Method for performing random read access to a block of data using parallel lut read instruction in vector processors

a vector processor and random read technology, applied in the field of digital data processing, can solve the problems of insufficient vector load instructions to perform parallel, the performance of the concerned algorithm drops drastically, and the random read access within the block of data is difficult to paralleliz

Inactive Publication Date: 2016-05-05
TEXAS INSTR INC
View PDF0 Cites 48 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0005]This invention deals with the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD p

Problems solved by technology

Random read accesses within a block of data is difficult to parallelize for vector SIMD operations because data needs to be fetched from non-sequential locations.
When access is completely random, vector load instructions are insufficient to perform parallel data fetch.
If it is not possible to parallelize co

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for performing random read access to a block of data using parallel lut read instruction in vector processors
  • Method for performing random read access to a block of data using parallel lut read instruction in vector processors
  • Method for performing random read access to a block of data using parallel lut read instruction in vector processors

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0038]FIG. 1 illustrates a dual scalar / vector datapath processor according to a preferred embodiment of this invention. Processor 100 includes separate level one instruction cache (L1I) 121 and level one data cache (L1D) 123. Processor 100 includes a level two combined instruction / data cache (L2) 130 that holds both instructions and data. FIG. 1 illustrates connection between level one instruction cache 121 and level two combined instruction / data cache 130 (bus 142). FIG. 1 illustrates connection between level one data cache 123 and level two combined instruction / data cache 130 (bus 145). In the preferred embodiment of processor 100 level two combined instruction / data cache 130 stores both instructions to back up level one instruction cache 121 and data to back up level one data cache 123. In the preferred embodiment level two combined instruction / data cache 130 is further connected to higher level cache and / or main memory in a manner not illustrated in FIG. 1. In the preferred embo...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

This invention deals with the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

Description

CLAIM OF PRIORITY[0001]This application claims priority under 35 U.S.C. 119(A) to Indian Provisional Application No. 5509 / CHE / 2014 filed Nov. 3, 2014.TECHNICAL FIELD OF THE INVENTION[0002]The technical field of this invention is digital data processing and more specifically data operand fetching.BACKGROUND OF THE INVENTION[0003]Random read accesses within a block of data is difficult to parallelize for vector SIMD operations because data needs to be fetched from non-sequential locations. Vector Load instructions can typically fetch only sequential data locations and in some cases certain predictable patterns for non-sequential data. When access is completely random, vector load instructions are insufficient to perform parallel data fetch.[0004]The strength of vector SIMD engines lies in its ability to parallelize computations over multiple data points simultaneously. If it is not possible to parallelize computations over multiple data points for a given algorithm, performance of the...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F3/06G06F12/08
CPCG06F3/0604G06F3/0647G06F3/0673G06F2212/452G06F12/0875G06F2212/454G06F12/0895G06F9/30036G06F9/3004G06F9/30043G06F9/383
Inventor SANKARANARAYANAN, JAYASREEMANDAL, DIPAN KUMAR
Owner TEXAS INSTR INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap