Method for performing random read access to a block of data using parallel lut read instruction in vector processors

Abstract

This invention deals with the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

Description

CLAIM OF PRIORITY[0001]This application claims priority under 35 U.S.C. 119(A) to Indian Provisional Application No. 5509 / CHE / 2014 filed Nov. 3, 2014.TECHNICAL FIELD OF THE INVENTION[0002]The technical field of this invention is digital data processing and more specifically data operand fetching.BACKGROUND OF THE INVENTION[0003]Random read accesses within a block of data is difficult to parallelize for vector SIMD operations because data needs to be fetched from non-sequential locations. Vector Load instructions can typically fetch only sequential data locations and in some cases certain predictable patterns for non-sequential data. When access is completely random, vector load instructions are insufficient to perform parallel data fetch.[0004]The strength of vector SIMD engines lies in its ability to parallelize computations over multiple data points simultaneously. If it is not possible to parallelize computations over multiple data points for a given algorithm, performance of the...

AI Technical Summary

Benefits of technology

The invention is about optimizing the processing of data within a vector SIMD processor. It focuses on the issue of accessing data in parallel within a reasonably sized block. By using plural parallel look up tables and a look up table read instruction, data can be processed more efficiently. A level one memory is used for both a data cache and directly addressable memory, with the look up table memory stored in the directly addressable memory. The technical effect of this invention is improved speed and efficiency of data processing within a vector SIMD processor.

Problems solved by technology

Random read accesses within a block of data is difficult to parallelize for vector SIMD operations because data needs to be fetched from non-sequential locations.

When access is completely random, vector load instructions are insufficient to perform parallel data fetch.

If it is not possible to parallelize computations over multiple data points for a given algorithm, performance of the concerned algorithm drops drastically and it offers no advantage over a scalar CPU core.

Random read access within a block of data located in memory is one such problem where lack of parallelization causes a performance bottleneck.

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