609 results about "Data cache" patented technology

The invention provides a cache architecture and method of an AXI interconnection module, electronic equipment and a storage medium, and relates to the technical field of storage, the cache architecture comprises an index cache region, a shared cache region and a shared cache access controller, the index cache region comprises an index entry list, and the shared cache region comprises an instruction cache region and a data cache region; each index cache region corresponds to one main device, the shared cache region corresponds to all the main devices, and the index entry list is used for recording index information of access transactions of the corresponding main devices; each index entry in the index entry list corresponds to one access transaction; and the shared cache access controller is used for storing instruction information corresponding to the access transaction in the instruction cache region based on the index information and storing data information corresponding to the access transaction in the data cache region. By applying the scheme of the invention, the utilization efficiency of on-chip resources can be improved on the basis of ensuring the transaction processing performance.

The invention relates to the technical field of audio control, and discloses a low-delay audio input switching method and system, a storage medium and equipment, and the method comprises the steps: carrying out the parallel pre-initialization of a plurality of pieces of audio input equipment, and building an independent parallel audio data cache for each piece of equipment; monitoring the state of each audio input device and the audio stream quality in real time, and judging whether switching is triggered or not based on a multi-factor decision model; after the switching decision is triggered, seamless audio data stream switching is executed, and format unification processing and cross fade-in and fade-out transition are included; a unified equipment operation interface is provided through the hardware abstraction layer, and system resources are optimized and managed; a delay sensing closed-loop control mechanism is constructed, processing delay of each link is monitored in real time, a caching strategy, a processing algorithm and resource allocation parameters are dynamically adjusted, self-adaptive balance of low delay and high tone quality is achieved, and through the method, quick and smooth switching of audio input equipment is achieved, delay is remarkably reduced, and real-time audio experience is improved.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention belongs to the field of integrated circuits and computer system structures, and provides a caching method and system for a memory access unit of a superscalar processor, and the method comprises the steps: receiving a plurality of memory access instructions in the same period, and determining a corresponding Bank in a to-be-accessed cache through the memory access instructions; after the memory access instruction obtains a cache access permission, if cache line missing occurs, generating a missing request, merging all the missing requests, and performing parallel prefetching training on the merged missing requests by utilizing a mode of fusing a constant step length prefetching mode and a complex step length prefetching mode to obtain a prefetching request and a prefetching cache address corresponding to the prefetching request; requesting a missing cache line from the first-level cache to the second-level cache based on the missing queue, and writing the missing cache line back to the cache line of the corresponding data cache in the first-level cache; and storing the bus consistency request by using the sniffing queue, judging whether the data in the multi-core cache are consistent or not by using the consistency request, and performing consistency modification according to a judgment result. The cache hit rate and the bandwidth utilization rate are improved.

The invention relates to the technical field of cloud computing, and particularly provides a data cache prefetching method and device, a storage medium and a program product. According to the method, file access characteristics representing file access preferences of a user are obtained based on historical access data of the user, a target file meeting a cache prefetching strategy is determined based on the file access characteristics, and the target file is cached and prefetched. By dynamically analyzing the historical access data of the user, the system can adjust the cache content in real time, actively load the data possibly required by the user and ensure that the high-frequency access data is always available, and the mechanism not only improves the data access speed, but also remarkably reduces the influence caused by network delay.

The invention relates to a processor and a kernel synchronization method for the processor. Based on the method and the device, the query request initiated by the plurality of processing cores in the processor for the same specified data can be selectively forwarded by the route, so that the occupation of the query request on the on-chip bandwidth of the processor can be reduced, and the query response occupying the on-chip bandwidth of the processor can be indirectly reduced. Or, the data cache unit where the specified data is located can reduce the generation of the query response for promoting the processing kernel to continue to initiate the query request, so that not only can the occupation of the query response to the on-chip bandwidth of the processor be reduced, but also the query request occupying the on-chip bandwidth of the processor can be indirectly reduced. Therefore, the occupation of the query request and the query response for realizing kernel synchronization on the on-chip bandwidth of the processor can be inhibited from the routing forwarding source of the query request or the generation source of the query response, so that the on-chip bandwidth occupied by the kernel synchronization in the processor can be reduced.

The invention provides a data cache optimization method, device and equipment for a vehicle-specification MCU and a storage medium, and the method comprises the steps: building a multi-target cache decision through predicting the future data access probability distribution, and giving consideration to the real-time performance and the memory utilization rate. A cache is divided into logic partitions with different priorities, and the sizes of the partitions are dynamically adjusted, so that a self-adaptive cache layout is formed. In combination with access probability distribution and a partitioning strategy, a dynamic pre-fetching threshold value is set, data pre-fetching is executed, and elimination and updating are performed in a task execution period, so that the caching efficiency and stability of a vehicle gauge MCU in a high-temperature and strong-vibration environment are improved, and the method is suitable for a vehicle-mounted control system with strict requirements on safety and performance.

The present application relates to the technical field of wireless communications, and discloses a resource allocation method, apparatus and device, a storage medium and a product, comprising: receiving a scheduling request signaling sent by a user equipment, and determining a signaling interaction time between the user equipment and a base station; sending an initial allocation signaling to the user equipment based on the scheduling request signaling and the signaling interaction time; determining target cache data according to the data cache state and a historical data cache state reported by the user equipment last time; and allocating uplink resources to the user equipment based on the target cache data, and sending a target allocation signaling corresponding to the target cache data to the user equipment. According to the method, multiple cache time slots are allocated to the user according to the signaling interaction time between the user and the base station, so that multi-thread uplink resource allocation is initiated, the user equipment can instantly report a data cache state to a satellite, and user data can be more instantly allocated with resources and transmitted.

The invention discloses a data cache management method and system based on big data, and relates to the technical field of data cache management, and the method comprises the steps: collecting access mode metadata, constructing a data cache state space and an action space, and screening an effective action set of data cache; on the basis of the state space, calculating a context feature weight, and constructing a CO-IAM model to predict a data caching action; performing data caching action implementation based on a CO-IAM model prediction result; by constructing a state space and an action space of data caching, introducing a CO-IAM model, performing precise modeling and dynamic adjustment based on context feature weight, generating an invalid action mask, filtering useless caching actions, optimizing a caching hit rate and access delay, and improving the performance of the whole caching system.

The invention relates to the technical field of artificial intelligence chips and storage management, in particular to a cache line replacement method and device, a chip and electronic equipment. The method is applied to a chip comprising a data cache, the data cache comprises N cache lines in which data are stored, an access path corresponding to each cache line is managed based on a binary tree structure comprising N-1 nodes in a PLRU algorithm, and a data replacement instruction is responded, obtaining a path status bit from a root node to a leaf node on an access path corresponding to each cache line; for a specified cache line, calculating a PLRU path value according to the path status bit, and calculating a replacement score in combination with the importance level and the corresponding weight of the stored data; determining a replaceable cache line according to the replacement score; and storing the to-be-cached data and the importance level thereof into a replaceable cache line to replace the original data and the original level. Therefore, the cache line replacement priority is evaluated by combining the PLRU path value and the importance level of the stored data, the cache hit rate is effectively improved, and the system performance is optimized.

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention discloses a vehicle-mounted power supply short-circuit heat prediction method based on big data analysis, and the method comprises the following steps: collecting real-time operation data, and storing the data in a data cache, thereby obtaining a cache time sequence signal; filtering the cached time sequence signal, and extracting a basic feature sequence; constructing an RC network model based on the basic feature sequence, and converting a fractional order operator into an equivalent integer order model; performing parameter estimation on the equivalent integer order model to generate a thermal prediction model; taking the thermal prediction model and the basic feature sequence as joint input and output power loss features; inputting the power loss characteristics into a quantile regression forest model to form a heat prediction result; comparing the heat prediction result with a heat threshold value and a temperature rise threshold value, and outputting a control trigger signal; and calling parameters in a control strategy library according to the control trigger signal to generate a control strategy. According to the invention, vehicle-mounted power supply short-circuit heat prediction is realized.

The invention provides an LED constant-current driving chip and a display system, and relates to the field of display. The LED constant current driving chip comprises a line feed signal generation module, a display data cache module, a display control module and a constant current driving module. The line feed signal generation module is used for resetting in response to the received frame synchronization signal, and counting or timing based on the frame synchronization signal and a line feed period so as to periodically output a line feed signal; the display data caching module is used for caching the input display data; the display control module is used for generating a PWM (Pulse Width Modulation) signal according to the line feed signal and the display data read from the display data cache module; and the constant current driving module outputs a constant current driving signal based on the PWM signal so as to drive a corresponding LED lamp bead to emit light. The LED constant-current driving chip provided by the invention can output the line feed signal under the condition of no ROW line, so that the wiring is simplified, and the port utilization rate is improved.

The invention relates to the technical field of earthquake and acoustic exploration, and discloses a signal acquisition and transmission method, device, equipment and medium based on a main control unit, and the method comprises the steps: generating a sampling clock signal and a time counting signal, driving an analog-to-digital conversion unit to obtain a digital acquisition signal, and reading equipment state parameters; after the timestamp is added, the digital signal is stored in the first cache unit, the state data after the timestamp is added is stored in the second cache unit, the data signal cache unit is written into a first FLASH partition after being full, and the state data cache unit is written into a second FLASH partition after being full. And after data is read from the FLASH, differential signals are output through the multi-wire parallel interface, the logic processing unit and the serialization unit. According to the invention, power consumption is reduced through unified power management and optimization of clock control and a dormancy mechanism, and transmission bandwidth is improved in combination with high-speed differential output, so that both low power consumption and high efficiency are realized.

A single-instruction multi-thread processor micro-architecture device oriented to neural network parallel scheduling comprises a front-end instruction fetching module, an instruction cache module, a decoding module, an arithmetic logic operation unit, a multiplication and division module, a memory access unit and a data cache module, and the micro-architecture device allocates a unique thread number for each thread. Threads are organized into thread groups, and in each period, the fair alternate arbiter selects an instruction from an instruction buffer of the thread group and sends the instruction to a subsequent decoding stage. The micro-architecture not only solves challenges faced by end-side equipment when processing high-performance calculation requirements such as neural network reasoning, but also provides an effective solution capable of reducing energy consumption and improving calculation efficiency through an innovative architecture design. The method is of great significance in promoting development of end-side AI application.

The invention relates to an FPGA-based satellite-borne file adaptive storage and scheduling method, which comprises the following steps: defining a data plane and a control plane, the data plane being responsible for high-frequency and high-speed data processing, and the control plane being responsible for low-frequency and low-speed data management and decision making; the data plane obtains a real-time data stream to be stored and stores the real-time data stream into a data cache; monitoring the running state of the data cache in real time, generating cache state data and reporting the cache state data to a control plane; the control plane makes a strategy decision based on the cache state data to generate a target strategy instruction; the data plane obtains the instruction and carries out hardware priority judgment in combination with cache state data so as to determine a final data writing instruction; and the data plane responds to the write-in instruction, executes error correction coding processing, data write-in and file verification processing, and reports a file closing state to the control plane. The method has the advantages that the system can dynamically respond to the real-time system load, and the stability and reliability of system scheduling are improved.

The invention relates to the technical field of data storage, in particular to an enterprise financial data security storage management system and method based on the Internet of Things. The method comprises the following steps: acquiring an enterprise financial data transmission log based on the Internet of Things, and performing data cache chain node trust anchoring to obtain trust authentication equipment data; according to the data of the trust authentication device, analyzing a hop trust transmission node to obtain a hop trust transmission map; performing structured enhancement by using the trust authentication device data to obtain to-be-encrypted bill data; chain side security consensus packaging is carried out on the to-be-encrypted bill data to obtain a verifiable consensus block; performing multi-label traceability control filing on the verifiable consensus block to obtain a traceability label filing body; and performing jump point transmission on the traceability label archive body to an enterprise private database by using the jump point trust transmission map so as to execute a data archiving task. According to the invention, the stability and security of enterprise financial data storage are significantly enhanced.

The invention provides a data caching processing method, which is applied to the technical field of artificial intelligence. The data caching processing method comprises the following steps: in response to a plurality of processing requests for different target texts, obtaining a plurality of target text blocks of each target text; according to the multiple target text blocks, a first key value cache and a second key value cache are obtained, and the first key value cache is the key value cache of at least one target text block in the multiple target text blocks stored by the first computing node; the second key value cache is a key value cache obtained by inputting any target text block into the target model under the condition that the first computing node does not store the key value cache of any target text block in the plurality of target text blocks; and sending cache information to the second computing node, wherein the cache information comprises the first key value cache, the second key value cache and the identifier of the processing request. The invention further provides a data cache computing node.

The invention provides a processor supporting data multiplexing and instruction multiplexing, which is used for supporting multiplexing of operands and instructions of a previous calculation task in a later-executed calculation task, and realizes operand multiplexing and instruction multiplexing based on configuration information stored by a host control module connected with the processor. The processor comprises a configuration information caching module used for storing a storage offset and a storage offset use mark which are acquired from configuration information and correspond to each instruction in each calculation task; the base address dynamic generation module is used for storing a data cache index address of each calculation task and generating a real base address of each instruction in each calculation task; and the calculation module is used for acquiring an operand to execute each calculation task based on the real base address of each instruction in each calculation task generated by the base address dynamic generation module.

The invention discloses a data caching system and method and electronic equipment, and relates to the technical field of data storage, and the method comprises the steps: screening valid units in original input data, and carrying out centralized storage to prevent invalid data from occupying caching resources; an annular register array is segmented and spliced into a continuous data sequence covering a head-to-tail connection area, and the problem of fracture during cross-boundary reading is solved. Therefore, the problem of overflow or invalid reading caused by low storage efficiency, cross-boundary read data breakage and mismatching of read-write rhythms in the original data cache containing valid and invalid units is solved, and the effects of improving the cache utilization rate, ensuring continuous output of cross-boundary valid data and improving the data interaction stability and efficiency are achieved.

The invention discloses a self-calibration and drift compensation method for an automatic underground water monitoring station, and the method comprises the following steps: 1, transmitting a reference measurement starting instruction to an underground bubble method device by an edge calculation gateway, forming a reference data pair by a bubble method water level reference value and a reference acquisition moment, and writing the reference data pair into a reference data cache region; 2, the edge computing gateway creates a state storage structure and a covariance storage structure; and step 3, the edge computing gateway reads a drift amount estimation value from the state storage structure as a drift compensation amount, and when a drift estimation standard deviation exceeds a set threshold, bubble method hardware reference acquisition is triggered. According to the invention, the problems of high manual calibration cost and lack of independent reference support in pure software estimation in the prior art are solved, so that a monitoring station can stably operate for a long time under an unattended condition and continuously output high-precision underground water level monitoring data.

The invention provides a data cache access method and device of a multi-core processor, and relates to the technical field of computer processors. The method comprises the following steps: accessing a data cache according to an access instruction, and responding to the access instruction to hit access data and write back the access data, or responding to the access instruction to not hit the access data, fetching back-filling data from a memory access failure queue and forwarding the back-filling data to the access queue. Accessing the data cache according to the data storage instruction, writing the stored data into the data cache in response to the access hit of the data cache, or calling a stored data retransmission unit in response to the access miss of the data cache; and sending a data storage failure request to the memory access failure queue, and taking back the backfill data and / or authority by the memory access failure queue. According to the method, the flexibility of the processing mode of the data cache access pipeline on the memory access instruction and the external consistency request can be improved, the access parallelism degree is improved, and the hardware resource utilization rate of the processor is increased.

The embodiment of the invention provides a multi-level cache access method, system and device and a storage medium, and relates to the technical field of data cache access, and the method comprises the following steps: obtaining a key field in a user auditing request, and converting the key field into a feature vector; searching whether a reasoning result corresponding to the feature vector exists in a first preset cache or not; if yes, a reasoning result is returned to the user; if not, a corresponding semantic partition is found in a second preset cache, and a historical cache vector with the highest similarity and a corresponding reasoning result are determined from the semantic partition; and determining a reasoning result corresponding to the feature vector according to the feature vector, a historical cache vector and a reasoning result corresponding to the historical cache vector. In this way, a two-stage cache mechanism based on the feature vector is constructed, a corresponding reasoning result is found in combination with semantic partition, the cache hit rate is increased, repeated reasoning of a large model is reduced, response delay is reduced, and therefore the requirements for high redundancy and high real-time performance of cache data reasoning are met.

The present application relates to the technical field of data processing, and is used for realizing universal and efficient processing of a multi-dimensional tensor. Provided are a processor, a tensor processing method, and a device. A tensor processing unit in the processor comprises: a preprocessing circuit, which is used for adjusting first dimension information of a multi-dimensional tensor, so as to obtain second dimension information, wherein the product of the size of any dimension in the second dimension information and the capacity of a unit access storage space is smaller than or equal to the capacity of a data cache; an address generation circuit, which is used for generating, on the basis of the second dimension information, a plurality of source addresses corresponding to a plurality of pieces of data in the multi-dimensional tensor; an access control circuit, which is used for determining a plurality of pieces of cache mapping information corresponding to the plurality of source addresses, and sending a plurality of access requests on the basis of the plurality of source addresses, and is used for acquiring from a first memory the plurality of pieces of data of the multi-dimensional tensor; and the data cache, which is used for caching the plurality of pieces of data on the basis of the plurality of pieces of cache mapping information.

The invention provides a hanger CAN signal processing method and device, equipment and an upper system. The hanger CAN signal processing method comprises the following steps: acquiring an original CAN message of a hanger CAN bus; according to a preset data frame structure, packaging the original CAN message to obtain a standardized data frame; analyzing the standardized data frame according to a preset frame description template and the frame identifier of the standardized data frame to obtain a CAN signal mapping relation; verifying the CAN signal mapping relation to obtain a verification result; when the verification result represents that the CAN signal mapping relation meets the preset verification requirement, the CAN signal mapping relation is stored in the data cache pool, processing of the CAN signals of the lifting appliance is completed, multi-protocol compatibility of CAN messages is achieved, redundant transmission of data is reduced, and the CAN signal transmission efficiency of the lifting appliance communication system is improved.

The invention belongs to the technical field of energy storage power stations and microgrids, and particularly relates to a method for automatically identifying industrial equipment based on a configurable protocol of an EMS. A protocol management module containing point location, equipment and business group management is constructed in an EMS system, and equipment connection information of different manufacturers, point location information (integrated into a standard protocol through a business unified identifier) and a business function and point location association relationship are configured, stored in a corresponding data table and refreshed to a general protocol cache. And the data acquisition program calls the corresponding protocol module to acquire real-time data, stores the real-time data in the data cache, and reads the data from the cache during display. According to the method, logic separation of the protocol and the program is realized, heterogeneous equipment of multiple manufacturers can be dynamically adapted without modifying the program, the problem of incompatibility of the protocol is solved, busy equipment bus and data delay are avoided, and the stability and the maintenance efficiency are improved.

The invention discloses an intelligent hierarchical caching method and system based on a hyper-converged architecture. The method comprises the steps of converged architecture collection, initial cache grading, three-way load prediction, cache resource scheduling and intelligent hierarchical caching. The invention relates to the technical field of intelligent grading of data caches, in particular to an intelligent grading caching method and system based on a hyper-converged architecture, and adopts an initial cache grading method based on popularity score calculation to realize a more dynamic, fine-grained and controllable three-layer cache initialization structure. The cold and hot data misplacement rate and the initial scheduling cost are effectively reduced; a self-adaptive load three-channel prediction model improved by time sequence alignment enhancement is adopted, a time sequence alignment enhancement and neighborhood enhancement mechanism is introduced, and a dual-channel gating fusion backbone network of a time channel and a resource channel is combined to carry out three-path load prediction; and performing cache resource scheduling by adopting a reinforcement learning method based on risk-sensitive reward improvement.

The invention discloses a data caching method and device based on a data access request, terminal equipment and a storage medium, and relates to the technical field of data caching, and the method comprises the steps: determining the service priority of each piece of storage data in a service period through the service period, and according to a service scene, determining the service priority of each piece of storage data; determining a first weight of the access record, a second weight of the importance level and a third weight of the service priority, and performing weighted summation according to the access record, the first weight, the importance level, the second weight, the service priority and the third weight to calculate the data heat of each piece of storage data; and storing the storage data of which the data popularity is greater than a preset popularity threshold into a preset data cache region. Therefore, the data popularity of the storage data in each business period and business scene is evaluated from multiple dimensions, and then the storage data with the data popularity greater than the preset popularity threshold value is stored in the data cache region, so that the problem of low hit rate of cache data in the prior art is effectively solved.

The invention provides an integrated edge box with multi-protocol bidirectional conversion and intelligent reasoning, in the edge box, a multi-protocol access and bidirectional semantic conversion module analyzes protocol messages from different protocol devices through a plurality of pre-configured protocol adapters, and an analysis result is written into a unified data cache and message bus module; converting the content of the protocol message into a semantic object; according to a mapping rule defined by the semantic object, the semantic object is converted into a message format required by a target protocol, and semantic-driven cross-protocol bidirectional conversion is realized; the unified data caching and message bus module is responsible for data caching, format unification, inter-module communication and task scheduling; the edge AI reasoning and dynamic decision module obtains equipment data from the unified data cache and message bus module for AI reasoning; according to the scheme of the invention, heterogeneous equipment is enabled to cooperatively operate in a unified intelligent edge system, and cross-protocol semantic intercommunication and intelligent self-adaptive operation in a real sense are achieved.