822 results about "Data cache" patented technology

The invention provides a data management method, device and equipment and a readable storage medium, and the method comprises the steps: obtaining key value cache data generated by a first type of computing power unit in a pre-filling stage, transmitting the key value cache data to a memory pool, and caching the key value cache data in the memory pool; and in response to a data acquisition demand of the second type of computing power unit in a decoding stage, transmitting the specified key value cache data cached in the memory pool to the second type of computing power unit according to the data acquisition demand. According to the technical scheme of the invention, the memory pool is arranged and the aggregated transmission channel is utilized, so that the transmission efficiency of the key value cache data between the computing power devices is effectively improved, the data transmission delay is reduced, and the network transmission protocol overhead is reduced, thereby improving the data interaction efficiency of the computing power devices in a pre-filling stage and a decoding stage, and improving the user experience. The utilization of computing power resources is optimized, and the throughput and performance of large model reasoning are improved.

The invention discloses a large model data distributed management method and device, equipment and a storage medium, and relates to the technical field of data processing, and the method comprises the steps: segmenting large model training data to obtain a plurality of data blocks, and determining a predicted access frequency based on a long short-term memory network model and the historical access frequency of the data blocks; caching the large model training data corresponding to the data block to a corresponding data cache layer by utilizing the predicted access frequency; constructing a resource portrait by using the static attribute and the dynamic index of the GPU node, and allocating the large model training task to a target GPU node by using a preset hybrid strategy and the resource portrait based on the predicted access frequency and the storage position corresponding to the data block in the data cache layer; when it is monitored that the large model training task on the target GPU node is executed, periodic snapshot is conducted on the large model training task through a distributed snapshot algorithm, and the obtained complete data state is stored in a distributed storage center. And the resource vacancy rate is reduced.

The invention relates to the technical field of geographic information systems, in particular to a map tile data efficient access method and system based on hybrid storage and intelligent layering, and the method comprises the following steps: constructing a multi-level storage architecture, carrying out dynamic heat analysis, carrying out intelligent layering scheduling, preloading and space prediction, and carrying out transmission and access optimization. The method has the beneficial effects that the multi-level storage pool is constructed by combining the advantages of object storage and a distributed file system; adopting a dynamic tile popularity analysis model to realize hot data cache acceleration and cold data hierarchical archiving; and meanwhile, a tile request preloading mechanism is introduced, and an access path is optimized in combination with a spatial locality prediction algorithm. According to the method, the storage cost can be remarkably reduced, the tile request delay is reduced, quick response in a high-concurrency scene is supported, and the method is suitable for application scenes such as Internet map services and smart cities.

The invention provides a cache architecture and method of an AXI interconnection module, electronic equipment and a storage medium, and relates to the technical field of storage, the cache architecture comprises an index cache region, a shared cache region and a shared cache access controller, the index cache region comprises an index entry list, and the shared cache region comprises an instruction cache region and a data cache region; each index cache region corresponds to one main device, the shared cache region corresponds to all the main devices, and the index entry list is used for recording index information of access transactions of the corresponding main devices; each index entry in the index entry list corresponds to one access transaction; and the shared cache access controller is used for storing instruction information corresponding to the access transaction in the instruction cache region based on the index information and storing data information corresponding to the access transaction in the data cache region. By applying the scheme of the invention, the utilization efficiency of on-chip resources can be improved on the basis of ensuring the transaction processing performance.

The invention discloses an SSD (Solid State Disk) cache management method, which relates to the technical field of SSDs, and comprises the following steps: step 1, cache space division: the cache space of the SSD is divided into a plurality of different types of sub-cache regions, and each sub-cache region at least comprises a hot data cache region, a cold data cache region and an intermediate data cache region; 2, data popularity monitoring: monitoring the access frequency of the data stored in the SSD in real time, judging the popularity level of the data according to the access frequency, judging the data with the access frequency higher than a set threshold as hot data, judging the data with the access frequency lower than another set threshold as cold data, and judging the data between the hot data and the cold data as intermediate data; 3, data cache allocation: according to the heat level of the data, storing hot data into a hot data cache region, storing cold data into a cold data cache region, and storing intermediate data into an intermediate data cache region; the cache utilization rate and the read-write performance are comprehensively improved, and the delay is reduced.

The invention relates to the technical field of data processing, can be applied to business scenes such as financial science and technology and medical health, and discloses a popup strategy task processing method which comprises the following steps: defining a life cycle node of a popup queue in a task queue processing center, dividing a popup task into an independent execution thread task and a shared execution thread task according to priority, binding to life cycle nodes respectively; creating an exclusive policy execution assembly line in the independent execution thread, and creating an interruptible policy execution assembly line in the shared execution thread; a strategy execution state judgment node is arranged in the two strategy execution assembly lines, and a standby strategy execution assembly line is triggered when strategy execution is abnormal; and uniformly storing output data generated by the three policy execution assembly lines through a public data cache region. By setting the priority-based thread task binding mechanism and the strategy execution state judgment node, decoupling and exception handling automation of the pop-up window strategy execution process are realized, and the strategy maintenance cost is reduced.

The invention relates to the technical field of audio control, and discloses a low-delay audio input switching method and system, a storage medium and equipment, and the method comprises the steps: carrying out the parallel pre-initialization of a plurality of pieces of audio input equipment, and building an independent parallel audio data cache for each piece of equipment; monitoring the state of each audio input device and the audio stream quality in real time, and judging whether switching is triggered or not based on a multi-factor decision model; after the switching decision is triggered, seamless audio data stream switching is executed, and format unification processing and cross fade-in and fade-out transition are included; a unified equipment operation interface is provided through the hardware abstraction layer, and system resources are optimized and managed; a delay sensing closed-loop control mechanism is constructed, processing delay of each link is monitored in real time, a caching strategy, a processing algorithm and resource allocation parameters are dynamically adjusted, self-adaptive balance of low delay and high tone quality is achieved, and through the method, quick and smooth switching of audio input equipment is achieved, delay is remarkably reduced, and real-time audio experience is improved.

The invention relates to the technical field of communication, and discloses a flow control method, electronic equipment and a storage medium, and the method comprises the steps: responding to data transmission of a target node, configuring a first-level cache of the target node, and configuring a data cache position corresponding to the target node as the first-level cache; under the condition that the data volume in the first-level cache reaches a preset back pressure threshold value, switching a data cache position corresponding to the target node to a second-level cache, and performing flow control on the target node; wherein the second-level cache is configured to be a shared cache of all nodes transmitting data to the local node. According to the invention, the problem of cache overflow caused by traffic burst of the switching network node can be solved.

The invention discloses a depth operation implementation method and device for parallel pixels in the vertical direction, a medium, equipment and a product. The method comprises the following steps: mapping each channel group with a thread bundle containing NT threads; acquiring jumping step length of vertical direction access and parameter configuration of a sliding window operator; performing register resource allocation for each thread to form a sliding window data cache region; determining NH row starting point coordinates of the current scanning round; when the current scanning round is executed, in each column slice participating in calculation, pixel groups at NT row and column positions are scanned from each row starting point coordinate with the jump step length as the span, and the pixel groups are loaded to register groups of all threads in corresponding thread bundles in sequence, so that each thread can process the calculation task of the corresponding local sliding window view. According to the method, thread-level independent calculation task allocation is realized through a pixel parallel strategy among threads, and allocated hardware resources can be utilized to the maximum extent.

The invention provides a multi-core GPU cache division method, architecture and data access method, relates to the technical field of graphics processor design, and aims to realize cross-core access performance system-level optimization and improve the performance of processing large-scale image data by introducing a cache allocation mechanism based on topology awareness. The method comprises the steps that a multi-core-grain GPU topological structure comprising a target computing core grain and at least one associated computing core grain is obtained, a to-be-divided far-end data cache of the target computing core grain is used for caching image data from a far-end video memory, and the to-be-divided far-end data cache is connected with the associated computing core grain through an inter-core-grain interconnection network; if the number of the calculation core particles contained in the multi-core-particle GPU does not exceed a first preset threshold value, the inter-core-particle hop count between each associated calculation core particle and a target calculation core particle is determined based on the topological structure, and then the corresponding capacity of the associated calculation core particles in the to-be-divided cache of the target calculation core particle is determined; and dividing the to-be-divided cache according to the capacity corresponding to each associated calculation core particle.

The invention discloses a virtual power plant operation management and control method based on a block chain, original power data are compressed into Hash fingerprints to be chained through a collaborative architecture of an edge computing layer and an AI pre-decision module, the block chain network load is effectively reduced, and a dynamic elastic PBFT consensus mechanism adjusts the scale of verification nodes in real time based on transaction types, so that the efficiency is improved. And compared with a traditional fixed node consensus mechanism, the network communication overhead is reduced. And a hash value asynchronous pre-verification technology is adopted, so that the interaction rate of the multi-dimensional power data is improved, and the efficiency is improved compared with that of a conventional data uplink mode. Through the decoupling design of the intelligent contract execution flow and the consensus verification flow and in combination with the pre-decision data cache queue, the resource scheduling instruction issuing time delay is reduced. The block chain transaction throughput is improved and is effectively improved compared with a standard alliance chain architecture, and the technical problems that the consensus mechanism processing transaction speed of an existing block chain is limited and the high-frequency real-time data interaction requirement of a virtual power plant is difficult to meet are successfully solved.

The invention provides a data storage instruction processing method, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps that a block address of a target high-speed cache block corresponding to a target cache line is sent into a data storage instruction prefetching queue, all target data storage instructions cached by the target cache line are not fully written in the target cache line, and a data storage instruction address of the target data storage instruction comprises the block address of the target high-speed cache block; and executing data storage address hit check of the data cache on a target data storage instruction in the data storage instruction prefetching queue, and initiating a prefetching request and executing a block address access lower-layer storage system based on a target cache block under the condition that the data storage address is invalid, and the data of the target cache block is obtained and backfilled to the data cache, and the number storage instruction data included in the target number storage instruction which initiates the pre-fetching request and is successfully pre-fetched is written into the target cache block in the data cache, so that the pre-fetching accuracy and the pre-fetching timeliness of the number storage instruction can be improved.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention belongs to the field of integrated circuits and computer system structures, and provides a caching method and system for a memory access unit of a superscalar processor, and the method comprises the steps: receiving a plurality of memory access instructions in the same period, and determining a corresponding Bank in a to-be-accessed cache through the memory access instructions; after the memory access instruction obtains a cache access permission, if cache line missing occurs, generating a missing request, merging all the missing requests, and performing parallel prefetching training on the merged missing requests by utilizing a mode of fusing a constant step length prefetching mode and a complex step length prefetching mode to obtain a prefetching request and a prefetching cache address corresponding to the prefetching request; requesting a missing cache line from the first-level cache to the second-level cache based on the missing queue, and writing the missing cache line back to the cache line of the corresponding data cache in the first-level cache; and storing the bus consistency request by using the sniffing queue, judging whether the data in the multi-core cache are consistent or not by using the consistency request, and performing consistency modification according to a judgment result. The cache hit rate and the bandwidth utilization rate are improved.

The invention relates to the technical field of cloud computing, and particularly provides a data cache prefetching method and device, a storage medium and a program product. According to the method, file access characteristics representing file access preferences of a user are obtained based on historical access data of the user, a target file meeting a cache prefetching strategy is determined based on the file access characteristics, and the target file is cached and prefetched. By dynamically analyzing the historical access data of the user, the system can adjust the cache content in real time, actively load the data possibly required by the user and ensure that the high-frequency access data is always available, and the mechanism not only improves the data access speed, but also remarkably reduces the influence caused by network delay.

The invention relates to a processor and a kernel synchronization method for the processor. Based on the method and the device, the query request initiated by the plurality of processing cores in the processor for the same specified data can be selectively forwarded by the route, so that the occupation of the query request on the on-chip bandwidth of the processor can be reduced, and the query response occupying the on-chip bandwidth of the processor can be indirectly reduced. Or, the data cache unit where the specified data is located can reduce the generation of the query response for promoting the processing kernel to continue to initiate the query request, so that not only can the occupation of the query response to the on-chip bandwidth of the processor be reduced, but also the query request occupying the on-chip bandwidth of the processor can be indirectly reduced. Therefore, the occupation of the query request and the query response for realizing kernel synchronization on the on-chip bandwidth of the processor can be inhibited from the routing forwarding source of the query request or the generation source of the query response, so that the on-chip bandwidth occupied by the kernel synchronization in the processor can be reduced.

The invention provides a data cache optimization method, device and equipment for a vehicle-specification MCU and a storage medium, and the method comprises the steps: building a multi-target cache decision through predicting the future data access probability distribution, and giving consideration to the real-time performance and the memory utilization rate. A cache is divided into logic partitions with different priorities, and the sizes of the partitions are dynamically adjusted, so that a self-adaptive cache layout is formed. In combination with access probability distribution and a partitioning strategy, a dynamic pre-fetching threshold value is set, data pre-fetching is executed, and elimination and updating are performed in a task execution period, so that the caching efficiency and stability of a vehicle gauge MCU in a high-temperature and strong-vibration environment are improved, and the method is suitable for a vehicle-mounted control system with strict requirements on safety and performance.

The invention discloses a laser radar multi-channel echo data online processing system, which sequentially comprises a data distribution layer, a data processing layer and a data processing layer, the data distribution layer divides the echo data and then sends the echo data to the data cache layer to extract a local maximum value, a filtered sampling point sub-sequence corresponding to the local maximum value and a serial number of the local maximum value in the corresponding filtered sampling point sub-sequence; and inputting the data to be pre-fitted into a data processing layer for pre-fitting and fitting based on a polarization normal waveform fitting function in sequence to obtain the optimized signal intensity and the optimized waveform center position, thereby further obtaining the channel calculation distance of the target. The invention further discloses a laser radar multichannel echo data on-line processing method. The on-line processing system is used for obtaining the spatial position information, the corrected spectral information and the spectral reflectivity of a target. According to the invention, by adopting an FPGA pipeline processing architecture, efficient online processing of multi-channel echo data of the hyperspectral laser radar is realized.

The present application relates to the technical field of wireless communications, and discloses a resource allocation method, apparatus and device, a storage medium and a product, comprising: receiving a scheduling request signaling sent by a user equipment, and determining a signaling interaction time between the user equipment and a base station; sending an initial allocation signaling to the user equipment based on the scheduling request signaling and the signaling interaction time; determining target cache data according to the data cache state and a historical data cache state reported by the user equipment last time; and allocating uplink resources to the user equipment based on the target cache data, and sending a target allocation signaling corresponding to the target cache data to the user equipment. According to the method, multiple cache time slots are allocated to the user according to the signaling interaction time between the user and the base station, so that multi-thread uplink resource allocation is initiated, the user equipment can instantly report a data cache state to a satellite, and user data can be more instantly allocated with resources and transmitted.

The invention discloses a data cache management method and system based on big data, and relates to the technical field of data cache management, and the method comprises the steps: collecting access mode metadata, constructing a data cache state space and an action space, and screening an effective action set of data cache; on the basis of the state space, calculating a context feature weight, and constructing a CO-IAM model to predict a data caching action; performing data caching action implementation based on a CO-IAM model prediction result; by constructing a state space and an action space of data caching, introducing a CO-IAM model, performing precise modeling and dynamic adjustment based on context feature weight, generating an invalid action mask, filtering useless caching actions, optimizing a caching hit rate and access delay, and improving the performance of the whole caching system.

The invention relates to the technical field of artificial intelligence chips and storage management, in particular to a cache line replacement method and device, a chip and electronic equipment. The method is applied to a chip comprising a data cache, the data cache comprises N cache lines in which data are stored, an access path corresponding to each cache line is managed based on a binary tree structure comprising N-1 nodes in a PLRU algorithm, and a data replacement instruction is responded, obtaining a path status bit from a root node to a leaf node on an access path corresponding to each cache line; for a specified cache line, calculating a PLRU path value according to the path status bit, and calculating a replacement score in combination with the importance level and the corresponding weight of the stored data; determining a replaceable cache line according to the replacement score; and storing the to-be-cached data and the importance level thereof into a replaceable cache line to replace the original data and the original level. Therefore, the cache line replacement priority is evaluated by combining the PLRU path value and the importance level of the stored data, the cache hit rate is effectively improved, and the system performance is optimized.

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention discloses a vehicle-mounted power supply short-circuit heat prediction method based on big data analysis, and the method comprises the following steps: collecting real-time operation data, and storing the data in a data cache, thereby obtaining a cache time sequence signal; filtering the cached time sequence signal, and extracting a basic feature sequence; constructing an RC network model based on the basic feature sequence, and converting a fractional order operator into an equivalent integer order model; performing parameter estimation on the equivalent integer order model to generate a thermal prediction model; taking the thermal prediction model and the basic feature sequence as joint input and output power loss features; inputting the power loss characteristics into a quantile regression forest model to form a heat prediction result; comparing the heat prediction result with a heat threshold value and a temperature rise threshold value, and outputting a control trigger signal; and calling parameters in a control strategy library according to the control trigger signal to generate a control strategy. According to the invention, vehicle-mounted power supply short-circuit heat prediction is realized.

The invention provides an LED constant-current driving chip and a display system, and relates to the field of display. The LED constant current driving chip comprises a line feed signal generation module, a display data cache module, a display control module and a constant current driving module. The line feed signal generation module is used for resetting in response to the received frame synchronization signal, and counting or timing based on the frame synchronization signal and a line feed period so as to periodically output a line feed signal; the display data caching module is used for caching the input display data; the display control module is used for generating a PWM (Pulse Width Modulation) signal according to the line feed signal and the display data read from the display data cache module; and the constant current driving module outputs a constant current driving signal based on the PWM signal so as to drive a corresponding LED lamp bead to emit light. The LED constant-current driving chip provided by the invention can output the line feed signal under the condition of no ROW line, so that the wiring is simplified, and the port utilization rate is improved.

The invention relates to the technical field of earthquake and acoustic exploration, and discloses a signal acquisition and transmission method, device, equipment and medium based on a main control unit, and the method comprises the steps: generating a sampling clock signal and a time counting signal, driving an analog-to-digital conversion unit to obtain a digital acquisition signal, and reading equipment state parameters; after the timestamp is added, the digital signal is stored in the first cache unit, the state data after the timestamp is added is stored in the second cache unit, the data signal cache unit is written into a first FLASH partition after being full, and the state data cache unit is written into a second FLASH partition after being full. And after data is read from the FLASH, differential signals are output through the multi-wire parallel interface, the logic processing unit and the serialization unit. According to the invention, power consumption is reduced through unified power management and optimization of clock control and a dormancy mechanism, and transmission bandwidth is improved in combination with high-speed differential output, so that both low power consumption and high efficiency are realized.

A single-instruction multi-thread processor micro-architecture device oriented to neural network parallel scheduling comprises a front-end instruction fetching module, an instruction cache module, a decoding module, an arithmetic logic operation unit, a multiplication and division module, a memory access unit and a data cache module, and the micro-architecture device allocates a unique thread number for each thread. Threads are organized into thread groups, and in each period, the fair alternate arbiter selects an instruction from an instruction buffer of the thread group and sends the instruction to a subsequent decoding stage. The micro-architecture not only solves challenges faced by end-side equipment when processing high-performance calculation requirements such as neural network reasoning, but also provides an effective solution capable of reducing energy consumption and improving calculation efficiency through an innovative architecture design. The method is of great significance in promoting development of end-side AI application.

The invention discloses a commodity inventory multi-dimensional query management method and system oriented to multi-terminal equipment, and relates to the technical field of information and communication specially suitable for the management purpose, in the method, a query dimension association graph is constructed, and a dimension priority sequence is generated; dividing the query dimensions into a strong association dimension group and a weak association dimension group; distributing query tasks in the weak association dimension group for each processing pipeline; constructing an annular data cache queue, and storing a query result of the strong association dimension group into a continuous storage unit of the annular cache queue; reading strong association dimension data from the annular cache queue, asynchronously obtaining weak association dimension data, and recombining query results according to a dimension priority sequence; performing hierarchical compression on the recombined query result based on a data compression algorithm; and according to the network state of the multi-terminal device, the compressed query result is sent to the multi-terminal device in batches through a self-adaptive transmission window mechanism. The method and the device are used for improving the efficiency of commodity inventory query management in a complex multi-dimensional query scene.

The invention relates to an FPGA-based satellite-borne file adaptive storage and scheduling method, which comprises the following steps: defining a data plane and a control plane, the data plane being responsible for high-frequency and high-speed data processing, and the control plane being responsible for low-frequency and low-speed data management and decision making; the data plane obtains a real-time data stream to be stored and stores the real-time data stream into a data cache; monitoring the running state of the data cache in real time, generating cache state data and reporting the cache state data to a control plane; the control plane makes a strategy decision based on the cache state data to generate a target strategy instruction; the data plane obtains the instruction and carries out hardware priority judgment in combination with cache state data so as to determine a final data writing instruction; and the data plane responds to the write-in instruction, executes error correction coding processing, data write-in and file verification processing, and reports a file closing state to the control plane. The method has the advantages that the system can dynamically respond to the real-time system load, and the stability and reliability of system scheduling are improved.

The invention relates to the technical field of data storage, in particular to an enterprise financial data security storage management system and method based on the Internet of Things. The method comprises the following steps: acquiring an enterprise financial data transmission log based on the Internet of Things, and performing data cache chain node trust anchoring to obtain trust authentication equipment data; according to the data of the trust authentication device, analyzing a hop trust transmission node to obtain a hop trust transmission map; performing structured enhancement by using the trust authentication device data to obtain to-be-encrypted bill data; chain side security consensus packaging is carried out on the to-be-encrypted bill data to obtain a verifiable consensus block; performing multi-label traceability control filing on the verifiable consensus block to obtain a traceability label filing body; and performing jump point transmission on the traceability label archive body to an enterprise private database by using the jump point trust transmission map so as to execute a data archiving task. According to the invention, the stability and security of enterprise financial data storage are significantly enhanced.