1033 results about "Data cache" patented technology

The invention provides a multilevel caching method and system based on CAN bus communication, and is applied to the field of data transmission. According to the method, the influence coefficient of the CAN bus is obtained by presetting load scenes (idle, low load and high load), whether the influence coefficient is limited by hardware is judged, the optimization direction is ensured to be accurate, data cache management is performed by adopting an annular buffer area, and the data transmission interval is dynamically adjusted and the data packaging strategy is optimized (small data merging, data alignment and filling byte reduction), so that the data transmission efficiency is improved. The CAN ID priority is dynamically adjusted by collecting communication data category information, it is ensured that high-priority data (such as ECU control signals) are transmitted in time, bandwidth occupation of low-priority data is reduced, in addition, the processing response speed of data frames is monitored, and if the processing response speed does not reach the standard, the data sending frequency is optimized, and the real-time performance is improved.

The invention provides a data management method, device and equipment and a readable storage medium, and the method comprises the steps: obtaining key value cache data generated by a first type of computing power unit in a pre-filling stage, transmitting the key value cache data to a memory pool, and caching the key value cache data in the memory pool; and in response to a data acquisition demand of the second type of computing power unit in a decoding stage, transmitting the specified key value cache data cached in the memory pool to the second type of computing power unit according to the data acquisition demand. According to the technical scheme of the invention, the memory pool is arranged and the aggregated transmission channel is utilized, so that the transmission efficiency of the key value cache data between the computing power devices is effectively improved, the data transmission delay is reduced, and the network transmission protocol overhead is reduced, thereby improving the data interaction efficiency of the computing power devices in a pre-filling stage and a decoding stage, and improving the user experience. The utilization of computing power resources is optimized, and the throughput and performance of large model reasoning are improved.

The invention provides a wireless communication network method and system of a mobile first-aid station. The method comprises the following steps: monitoring and evaluating a surrounding environment in real time, selecting an optimal working frequency band, and adjusting a frequency band switching strategy to obtain a self-adaptive multi-frequency-band access mechanism; the bandwidth and the connection priority of the wireless communication network are dynamically adjusted, the task priority is evaluated, and a dynamic resource allocation strategy is generated; deploying a distributed cache and synchronization system, realizing balanced distribution and rapid positioning of data, and generating a distributed temporary data cache pool; establishing an intelligent routing algorithm of deep reinforcement learning, calculating an optimal transmission path from a source to a destination, and finally generating an intelligent routing planning scheme; a redundant path is preset on the path, and a redundant path planning scheme is generated according to a dynamic resource allocation strategy and an intelligent routing planning result. According to the technical scheme provided by the invention, the reliability and the response speed of the wireless communication network of the mobile first-aid station are improved.

The invention relates to the technical field of countercurrent prevention, in particular to a photovoltaic system countercurrent prevention method, which comprises the following steps of: periodically sampling the voltage of a grid-connected point where a photovoltaic system is connected with a power grid, continuously obtaining an instantaneous measurement value of the voltage, and establishing and updating an instantaneous voltage data cache; and based on the instant voltage data cache, extracting voltage data in the latest fixed time window, calculating the maximum change rate of the voltage amplitude in the time window, and judging and generating a voltage transient trigger signal. According to the invention, on the basis of continuous and periodic sampling of the grid-connected point voltage, an instant voltage data cache is established, and accurate capture of voltage disturbance is realized; by calculating the change rate of the voltage amplitude in the specific time window, the accurate moment when the voltage transient event occurs can be identified, and the real-time performance and accuracy of voltage transient detection are improved.

The invention discloses a large model data distributed management method and device, equipment and a storage medium, and relates to the technical field of data processing, and the method comprises the steps: segmenting large model training data to obtain a plurality of data blocks, and determining a predicted access frequency based on a long short-term memory network model and the historical access frequency of the data blocks; caching the large model training data corresponding to the data block to a corresponding data cache layer by utilizing the predicted access frequency; constructing a resource portrait by using the static attribute and the dynamic index of the GPU node, and allocating the large model training task to a target GPU node by using a preset hybrid strategy and the resource portrait based on the predicted access frequency and the storage position corresponding to the data block in the data cache layer; when it is monitored that the large model training task on the target GPU node is executed, periodic snapshot is conducted on the large model training task through a distributed snapshot algorithm, and the obtained complete data state is stored in a distributed storage center. And the resource vacancy rate is reduced.

An intelligent power monitoring management system based on Internet of Things belongs to the technical field of power supervision and comprises a data acquisition module, a communication transmission module, a data processing and analysis module, an edge calculation module, an intelligent control module, an early warning management module and an authority control module. According to the invention, by deploying various types of sensors, real-time acquisition and dynamic monitoring of key parameters of the power system are realized. The system can obtain and analyze data such as voltage, current and power in time, ensures the accuracy and high efficiency of operation of the power system, and effectively avoids energy consumption waste and equipment faults. The edge computing technology is adopted, preprocessing and preliminary analysis are carried out at a data acquisition end, the data processing pressure of a central server is relieved, the bandwidth requirement for data transmission is lowered, and the response speed is increased. Even if the network is interrupted, the edge device can realize short-term data caching, and data continuity is guaranteed. And performing anomaly detection on the power system, identifying potential risks and giving an alarm.

The invention relates to the technical field of geographic information systems, in particular to a map tile data efficient access method and system based on hybrid storage and intelligent layering, and the method comprises the following steps: constructing a multi-level storage architecture, carrying out dynamic heat analysis, carrying out intelligent layering scheduling, preloading and space prediction, and carrying out transmission and access optimization. The method has the beneficial effects that the multi-level storage pool is constructed by combining the advantages of object storage and a distributed file system; adopting a dynamic tile popularity analysis model to realize hot data cache acceleration and cold data hierarchical archiving; and meanwhile, a tile request preloading mechanism is introduced, and an access path is optimized in combination with a spatial locality prediction algorithm. According to the method, the storage cost can be remarkably reduced, the tile request delay is reduced, quick response in a high-concurrency scene is supported, and the method is suitable for application scenes such as Internet map services and smart cities.

The invention discloses a self-adaptive data caching and synchronizing method, system and device for an edge gateway of the Internet of Things and a storage medium, and the method comprises the steps: obtaining network quality parameters, such as link bandwidth, time delay and packet loss rate, between nodes, detecting and solving instruction conflicts based on a vector clock mechanism, generating an instruction execution sequence, and carrying out the self-adaptive data caching and synchronizing of the edge gateway of the Internet of Things; local caching and incremental synchronization strategies are adopted for hotspot data, a data access mode is dynamically predicted in combination with a machine learning algorithm, and a cache updating period is optimized. The future data is predicted according to the data characteristics of the Internet of Things application, and the data cache updating period of each node is dynamically adjusted, so that each node can keep a relatively consistent updating rhythm when caching a hotspot data copy; therefore, the hot spot data copies of different nodes can be ensured to have similar accuracy and timeliness at the same time point, so that the data consistency is maintained.

The invention discloses a computer network security monitoring system and method. The system comprises a quantum encryption traffic acquisition module, a biological recognition feature extraction module, a block chain detection traceability analysis module and a visual management module. The quantum encryption flow collection module generates and distributes a secure quantum key through a quantum key distribution unit, encrypts a collected data packet through an encryption transmission unit, and generates a flow data segment through a flow collection subunit and a data cache statistical analysis subunit. The biological recognition feature extraction module verifies the identity of a user through a biological recognition unit, and extracts a multi-dimensional feature vector by using a feature extraction subunit. And the block chain detection traceability analysis module performs detection and traceability analysis on the abnormal traffic through the anomaly detection subunit and the traceability analysis subunit, and stores a result in the block chain storage unit. The visual management module provides visual network state display and user identity verification functions through a visual display subunit and an identity verification and access control subunit. According to the invention, quantum encryption, biological recognition and block chain technologies are combined, so that the accuracy, security and traceability of network security monitoring are improved.

The invention provides a memory access instruction processing method and a processor, and relates to the technical field of data processing, and the method comprises the following steps: splitting a target vector memory access instruction into a plurality of target vector memory access micro-operations based on a memory access width, combining the target scalar memory access instruction with at least one unexecuted scalar memory access instruction into a target scalar memory access micro-operation; executing each target vector memory access micro-operation, and / or executing a target scalar memory access micro-operation; the memory access width is determined based on a number of data cache banks in a data cache in the processor and a bit width of the data cache banks. According to the memory access instruction processing method and the processor provided by the invention, resources can be more reasonably allocated for vector memory access and scalar memory access during data memory access through splitting of the vector memory access instruction and merging of the scalar memory access instruction, and maximum resource sharing of the vector memory access and the scalar memory access is realized.

The invention provides a cache architecture and method of an AXI interconnection module, electronic equipment and a storage medium, and relates to the technical field of storage, the cache architecture comprises an index cache region, a shared cache region and a shared cache access controller, the index cache region comprises an index entry list, and the shared cache region comprises an instruction cache region and a data cache region; each index cache region corresponds to one main device, the shared cache region corresponds to all the main devices, and the index entry list is used for recording index information of access transactions of the corresponding main devices; each index entry in the index entry list corresponds to one access transaction; and the shared cache access controller is used for storing instruction information corresponding to the access transaction in the instruction cache region based on the index information and storing data information corresponding to the access transaction in the data cache region. By applying the scheme of the invention, the utilization efficiency of on-chip resources can be improved on the basis of ensuring the transaction processing performance.

The invention discloses an SSD (Solid State Disk) cache management method, which relates to the technical field of SSDs, and comprises the following steps: step 1, cache space division: the cache space of the SSD is divided into a plurality of different types of sub-cache regions, and each sub-cache region at least comprises a hot data cache region, a cold data cache region and an intermediate data cache region; 2, data popularity monitoring: monitoring the access frequency of the data stored in the SSD in real time, judging the popularity level of the data according to the access frequency, judging the data with the access frequency higher than a set threshold as hot data, judging the data with the access frequency lower than another set threshold as cold data, and judging the data between the hot data and the cold data as intermediate data; 3, data cache allocation: according to the heat level of the data, storing hot data into a hot data cache region, storing cold data into a cold data cache region, and storing intermediate data into an intermediate data cache region; the cache utilization rate and the read-write performance are comprehensively improved, and the delay is reduced.

The invention relates to the technical field of computers, in particular to an adaptive method and device based on Warp scheduling and cache replacement and a medium. The method comprises the following steps: dynamically monitoring an access behavior of a Warp in an L1 data cache through a locality sensing unit, and identifying locality preference of a workload; according to the locality preference, adaptively selecting a Warp scheduling algorithm; periodically collecting cache access count and cache missing count through a cache state monitor, calculating the memory access missing rate of the current sampling period, and comparing the memory access missing rate with the missing rate of the previous sampling period; if the memory access missing rate of the current sampling period is higher than that of the previous sampling period, switching a cache replacement strategy; if not, the current strategy is kept. According to the method, the Warp scheduling algorithm and the cache replacement strategy are adaptively adjusted, so that the cache utilization rate and the performance of the GPGPU are optimized.

The invention discloses a signal data dynamic loading method based on Web graphical programming. The method comprises the steps that a server collects waveform data; the waveform data caching module caches waveform data and sends the waveform data to the adapter module and the downsampling module; the down-sampling module carries out down-sampling on the waveform data, and the down-sampled data is sent to the adapter module through the down-sampled data cache module; the database adapter writes basic information into a service database, and the time sequence database adapter writes time sequence data into a time sequence database; the browser obtains a data loading request instruction; the query module determines a query condition; the query module queries corresponding waveform target data; the query module preprocesses the waveform target data and sends the waveform target data to the browser; and the waveform display control performs graphical format conversion on the graphical waveform data and displays the graphical waveform data in a browser. The method has the advantages that dynamic loading and visual display of the real-time data can be achieved in a graphical mode, and a new solution is provided for monitoring, analyzing and processing the real-time data.

The invention relates to the technical field of data processing, can be applied to business scenes such as financial science and technology and medical health, and discloses a popup strategy task processing method which comprises the following steps: defining a life cycle node of a popup queue in a task queue processing center, dividing a popup task into an independent execution thread task and a shared execution thread task according to priority, binding to life cycle nodes respectively; creating an exclusive policy execution assembly line in the independent execution thread, and creating an interruptible policy execution assembly line in the shared execution thread; a strategy execution state judgment node is arranged in the two strategy execution assembly lines, and a standby strategy execution assembly line is triggered when strategy execution is abnormal; and uniformly storing output data generated by the three policy execution assembly lines through a public data cache region. By setting the priority-based thread task binding mechanism and the strategy execution state judgment node, decoupling and exception handling automation of the pop-up window strategy execution process are realized, and the strategy maintenance cost is reduced.

The invention relates to a satellite Internet of Things scene-oriented swan-gap intelligent gateway architecture, which is used for link adaptation between a satellite Internet of Things terminal and a sensor in an application scene of a satellite Internet of Things, and comprises a data transmission module, a data processing module and a data management module, wherein the data transmission module comprises a serial port communication transmission unit and a wireless communication transmission unit; the swan intelligent gateway performs data transmission and data reception with the sensor and the satellite Internet of Things terminal through the serial port communication transmission unit or the wireless communication transmission unit; the data processing module comprises a protocol conversion unit, a data encryption unit, a data priority division unit and a data compression unit which are respectively used for realizing core functions of protocol conversion, data encryption, data priority judgment and data compression; and the data management module is mainly responsible for simple caching of data, so that the cloud platform can perform remote short-term access.

The invention relates to the technical field of database cache management, in particular to an LSM engine data cache optimization method, which comprises the following steps of: based on cache region data of an LSM storage engine, recording access times of implementation detailed rules, counting distribution density of implementation detailed rules, arranging the data into a priority sequence, and generating an implementation detailed rule access distribution information set. According to the method, accurate mastering of the implementation detailed rule distribution density is achieved by recording the implementation detailed rule access times and distribution positions, the implementation detailed rule distribution density is grouped and sorted into the priority sequence, the cache data reading efficiency is improved, and the cache data reading efficiency is improved by adjusting and optimizing the data storage layout and reducing the high-frequency data retrieval delay. The method has the advantages that the problem of uneven storage allocation is solved, the resource utilization rate is increased, data distribution is optimized through high-frequency implementation rule comparison, new implementation rule matching is dynamically adjusted, the hit rate and the response speed are increased, the system load is reduced, and the storage performance and the resource allocation efficiency are remarkably improved.

The invention relates to the technical field of data cache management, in particular to a multilayer data cache dynamic management method and system, and the method comprises the following steps: based on a data access path, extracting a data access path hierarchy identifier, analyzing path hierarchy depth, recording access continuity, classifying the path to be stable or unstable, and obtaining path hierarchy distribution information. In the invention, through hierarchical analysis and stability classification of the data access paths, the cache resource allocation efficiency, the stable paths and the unstable paths are improved, the access delay is reduced, the access continuity is improved, the cache waste caused by hopping is reduced, the space utilization rate is improved, the cache pollution is avoided, the storage sequence is optimized, and the hit rate is improved; through dynamic elimination, resource competition is reduced, storage medium I / O load is monitored, medium load is balanced, throughput capacity is improved, data flow is optimized, cache coordination capacity is improved, cache levels can flexibly adapt to access mode changes, and data storage stability and load balance are enhanced.

The invention relates to the technical field of audio control, and discloses a low-delay audio input switching method and system, a storage medium and equipment, and the method comprises the steps: carrying out the parallel pre-initialization of a plurality of pieces of audio input equipment, and building an independent parallel audio data cache for each piece of equipment; monitoring the state of each audio input device and the audio stream quality in real time, and judging whether switching is triggered or not based on a multi-factor decision model; after the switching decision is triggered, seamless audio data stream switching is executed, and format unification processing and cross fade-in and fade-out transition are included; a unified equipment operation interface is provided through the hardware abstraction layer, and system resources are optimized and managed; a delay sensing closed-loop control mechanism is constructed, processing delay of each link is monitored in real time, a caching strategy, a processing algorithm and resource allocation parameters are dynamically adjusted, self-adaptive balance of low delay and high tone quality is achieved, and through the method, quick and smooth switching of audio input equipment is achieved, delay is remarkably reduced, and real-time audio experience is improved.

The invention relates to the technical field of communication, and discloses a flow control method, electronic equipment and a storage medium, and the method comprises the steps: responding to data transmission of a target node, configuring a first-level cache of the target node, and configuring a data cache position corresponding to the target node as the first-level cache; under the condition that the data volume in the first-level cache reaches a preset back pressure threshold value, switching a data cache position corresponding to the target node to a second-level cache, and performing flow control on the target node; wherein the second-level cache is configured to be a shared cache of all nodes transmitting data to the local node. According to the invention, the problem of cache overflow caused by traffic burst of the switching network node can be solved.

The invention discloses a reconfigurable systolic array tensor IP core based on an FPGA. The architecture comprises a core controller, a shift distributor, a data processing array and a four-stage data cache. The tensor core can adapt to general tensor multiplication and addition operations in Prefill and Decode stages of the generative neural network at the same time through reconfigurable design. The core controller receives the tensor multiplication instruction and the configuration information and decouples the tensor multiplication instruction and the configuration information according to a data stream to generate a plurality of block tensor multiplication instructions. The shift distributor decodes a block tensor multiplication instruction, decoded mode information controls data communication between a first-level cache and a second-level cache (Distrided RAM and Bram), a control signal of a data processing array is generated, and the control signal enters the array together with data to flow. And the data processing array is connected with different secondary BRAM caches according to the received configuration information and is used for processing data in a bubble-free pulsating flow manner. The four-stage data cache realizes the multi-stage pinpong operation of the loading of the operation data of the tensor operation core, and realizes the multi-stage pipeline design of the data from the off-chip HBM to the on-chip URAM, from the URAM to the BRAM and from the BRAM to the operation unit. Aiming at a single-user edge end generation type network reasoning task, a core controller generates a data processing unit mode configuration signal in a fine-grained (tensor element level) manner, and the data processing unit mode configuration signal is transmitted by a shift distributor and flows in parallel with operation data, so that the mode configuration efficiency and the hardware resource utilization rate are greatly improved, the problem of high fan-out caused by broadcast control is reduced, and the user experience is improved. A control flow is designed by means of the structural characteristics of the systolic array, and a complex control algorithm is realized with low resource occupation.

The invention discloses a shared cache system applied to a real-time network terminal chip. The shared cache system comprises queue management, enqueue scheduling control, dequeue scheduling control, write bus control, read bus control, a data cache, a register module, an RXFIFO module and a TXFIFO module. According to the cache allocation strategy, the variable-length data is stored by using the fixed-length unit. The user can customize and configure the private space, the residual space is the shared space, and the storage utilization rate is high. The shared cache is mainly used for storing data packets sent by an external application layer through a host interface. And storing the received data packet, extracting frame information according to a network flow protocol, and directly discarding frames which do not meet the protocol. The shared cache is provided with a dynamic cache structure, the state of each queue can be updated in real time, frame loss is prevented, and the data stream processing capacity is improved. And meanwhile, complex hybrid scheduling of a real-time network is met. The whole shared cache is subjected to anti-radiation reinforcement, the scene requirement of space navigation application is met, and high reliability is achieved.

The invention discloses a depth operation implementation method and device for parallel pixels in the vertical direction, a medium, equipment and a product. The method comprises the following steps: mapping each channel group with a thread bundle containing NT threads; acquiring jumping step length of vertical direction access and parameter configuration of a sliding window operator; performing register resource allocation for each thread to form a sliding window data cache region; determining NH row starting point coordinates of the current scanning round; when the current scanning round is executed, in each column slice participating in calculation, pixel groups at NT row and column positions are scanned from each row starting point coordinate with the jump step length as the span, and the pixel groups are loaded to register groups of all threads in corresponding thread bundles in sequence, so that each thread can process the calculation task of the corresponding local sliding window view. According to the method, thread-level independent calculation task allocation is realized through a pixel parallel strategy among threads, and allocated hardware resources can be utilized to the maximum extent.

The invention provides a multi-core GPU cache division method, architecture and data access method, relates to the technical field of graphics processor design, and aims to realize cross-core access performance system-level optimization and improve the performance of processing large-scale image data by introducing a cache allocation mechanism based on topology awareness. The method comprises the steps that a multi-core-grain GPU topological structure comprising a target computing core grain and at least one associated computing core grain is obtained, a to-be-divided far-end data cache of the target computing core grain is used for caching image data from a far-end video memory, and the to-be-divided far-end data cache is connected with the associated computing core grain through an inter-core-grain interconnection network; if the number of the calculation core particles contained in the multi-core-particle GPU does not exceed a first preset threshold value, the inter-core-particle hop count between each associated calculation core particle and a target calculation core particle is determined based on the topological structure, and then the corresponding capacity of the associated calculation core particles in the to-be-divided cache of the target calculation core particle is determined; and dividing the to-be-divided cache according to the capacity corresponding to each associated calculation core particle.

The invention discloses a virtual power plant operation management and control method based on a block chain, original power data are compressed into Hash fingerprints to be chained through a collaborative architecture of an edge computing layer and an AI pre-decision module, the block chain network load is effectively reduced, and a dynamic elastic PBFT consensus mechanism adjusts the scale of verification nodes in real time based on transaction types, so that the efficiency is improved. And compared with a traditional fixed node consensus mechanism, the network communication overhead is reduced. And a hash value asynchronous pre-verification technology is adopted, so that the interaction rate of the multi-dimensional power data is improved, and the efficiency is improved compared with that of a conventional data uplink mode. Through the decoupling design of the intelligent contract execution flow and the consensus verification flow and in combination with the pre-decision data cache queue, the resource scheduling instruction issuing time delay is reduced. The block chain transaction throughput is improved and is effectively improved compared with a standard alliance chain architecture, and the technical problems that the consensus mechanism processing transaction speed of an existing block chain is limited and the high-frequency real-time data interaction requirement of a virtual power plant is difficult to meet are successfully solved.

The invention provides a data storage instruction processing method, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps that a block address of a target high-speed cache block corresponding to a target cache line is sent into a data storage instruction prefetching queue, all target data storage instructions cached by the target cache line are not fully written in the target cache line, and a data storage instruction address of the target data storage instruction comprises the block address of the target high-speed cache block; and executing data storage address hit check of the data cache on a target data storage instruction in the data storage instruction prefetching queue, and initiating a prefetching request and executing a block address access lower-layer storage system based on a target cache block under the condition that the data storage address is invalid, and the data of the target cache block is obtained and backfilled to the data cache, and the number storage instruction data included in the target number storage instruction which initiates the pre-fetching request and is successfully pre-fetched is written into the target cache block in the data cache, so that the pre-fetching accuracy and the pre-fetching timeliness of the number storage instruction can be improved.

The invention relates to the field of semiconductors, and discloses an FPGA-based time sequence generator, a time sequence generation method, terminal equipment and a readable storage medium, and the FPGA-based time sequence generator comprises a clock source which is used for providing a working frequency; the test period buffer is used for sequentially caching the data of each test period; the time sequence data cache is used for sequentially caching all time sequence data; the test period counter is used for starting counting every time one test period is entered; the time sequence edge generator is used for determining whether the time sequence clock is enabled or not according to the count of the test period data of the same test period and the integer part value of the time sequence data, and outputting the decimal part value of the time sequence clock which is not full of the integer multiple; the data generator is used for generating the received one-bit mode data into parallel data with a preset bit width when the time sequence clock is enabled; and the converter is used for converting the parallel data into serial data by using the preset frequency multiplication clock of the working frequency and then outputting the serial data. According to the scheme, the time resolution based on the time sequence generator can be improved.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention belongs to the field of integrated circuits and computer system structures, and provides a caching method and system for a memory access unit of a superscalar processor, and the method comprises the steps: receiving a plurality of memory access instructions in the same period, and determining a corresponding Bank in a to-be-accessed cache through the memory access instructions; after the memory access instruction obtains a cache access permission, if cache line missing occurs, generating a missing request, merging all the missing requests, and performing parallel prefetching training on the merged missing requests by utilizing a mode of fusing a constant step length prefetching mode and a complex step length prefetching mode to obtain a prefetching request and a prefetching cache address corresponding to the prefetching request; requesting a missing cache line from the first-level cache to the second-level cache based on the missing queue, and writing the missing cache line back to the cache line of the corresponding data cache in the first-level cache; and storing the bus consistency request by using the sniffing queue, judging whether the data in the multi-core cache are consistent or not by using the consistency request, and performing consistency modification according to a judgment result. The cache hit rate and the bandwidth utilization rate are improved.

The invention relates to the technical field of cloud computing, and particularly provides a data cache prefetching method and device, a storage medium and a program product. According to the method, file access characteristics representing file access preferences of a user are obtained based on historical access data of the user, a target file meeting a cache prefetching strategy is determined based on the file access characteristics, and the target file is cached and prefetched. By dynamically analyzing the historical access data of the user, the system can adjust the cache content in real time, actively load the data possibly required by the user and ensure that the high-frequency access data is always available, and the mechanism not only improves the data access speed, but also remarkably reduces the influence caused by network delay.