50 results about "Instruction window" patented technology

Malicious software is identified in an executable file by identifying malicious structural features, decryption code, and cryptographic functions. A malicious structural feature is identified by comparing a known malicious structural feature to one or more instructions of the executable file. A malicious structural feature is also identified by graphically and statistically comparing windows of bytes or instructions in a section of the executable file. Cryptography is an indicator of malicious software. Decryption code is identified in an executable file by identifying a tight loop around a reversible instruction that writes to random access memory. Cryptographic functions are identified in an executable file be obtaining a known cryptographic function and performing a string comparison of the numeric constants of the known cryptographic function with the executable file.

A just-in-time (JIT) compiler typically generates code from bytecodes that have a sequence of assembly instructions forming a "template". It has been discovered that a just-in-time (JIT) compiler generates a small number, approximately 2.3, assembly instructions per bytecode. It has also been discovered that, within a template, the assembly instructions are almost always dependent on the next assembly instruction. The absence of a dependence between instructions of different templates is exploited to increase the size of issue groups using scheduling. A fast method for scheduling program instructions is useful in just-in-time (JIT) compilers. Scheduling of instructions is generally useful for just-in-time (JIT) compilers that are targeted to in-order superscalar processors because the code generated by the JIT compilers is often sequential in nature. The disclosed fast scheduling method has a complexity, and therefore an execution time, that is proportional to the number of instructions in an instruction block (N complexity), a substantial improvement in comparison to the N2 complexity of conventional compiler schedulers. The described fast scheduler advantageously reorders instructions with a single pass, or few passes, through a basic instruction block while a conventional compiler scheduler such as the DAG scheduler must iterate over an instruction basic block many times. A fast scheduler operates using an analysis of a sliding window of three instructions, applying two rules within the three instruction window to determine when to reorder instructions. The analysis includes acquiring the opcodes and operands of each instruction in the three instruction window, and determining register usage and definition of the operands of each instruction with respect to the other instructions within the window. The rules are applied to determine ordering of the instructions within the window.

A method and apparatus for predicting load addresses and identifying new threads of instructions for execution in a multithreaded processor. A load prediction unit scans an instruction window for load instructions. A load prediction table is searched for an entry corresponding to a detected load instruction. If an entry is found in the table, a load address prediction is made for the load instruction and conveyed to the data cache. If the load address misses in the cache, the data is prefetched. Subsequently, if it is determined that the load prediction was incorrect, a miss counter in the corresponding entry in the load prediction table is incremented. If on a subsequent detection of the load instruction, the miss counter has reached a threshold, the load instruction is predicted to miss. In response to the predicted miss, a new thread of instructions is identified for execution.

A processor includes at least one functional unit configured to execute an instruction. The processor also includes an instruction window configured to supply the instruction to the functional unit. The processor further includes a register file configured such that data and a result of execution of the instruction are temporarily stored in the register file. The processor still further includes a branch prediction circuit having a branch execution unit and a branch prediction table. The processor also includes a data value prediction circuit configured to predict a first operand value which will be used by the functional unit and a second operand value which will be used by the branch execution unit to predict a direction of a branch and to store the direction of the branch in the branch prediction table. With such a processor, a branch prediction is made by executing a branch instruction rather than by referring to the history of the branch instruction.

Scheduling threads in a multi-threaded/multi-core processor having a given instruction window, and scheduling a predefined number N of threads among a set of M active threads in each context switch interval are provided. The actual power consumption of each running thread during a given context switch interval is determined, and a predefined priority level is associated with each thread among the active threads based on the actual power consumption determined for the threads. The power consumption expected for each active thread during the next context switch interval in the current instruction window (CIW_Power_Th) is predicted, and a set of threads to be scheduled among the active threads are selected from the priority level associated with each active thread and the power consumption predicted for each active thread in the current instruction window.

A multithreading processor achieves a very large lookahead instruction window by allowing non-sequential fetch and processing of the dynamic instruction stream. A speculative thread is spawned at a specified point in the dynamic instruction stream and the instructions subsequent to the specified point are speculatively executed so that these instructions are fetched and issued out of sequential order. Very minimal modifications to existing processor design of a multithreading processor are required to achieve the very large lookahead instruction window. The modifications include changes to the control logic of the issue unit, only three additional bits in the register scoreboard.

A memory disambiguation apparatus includes a store queue, a store forwarding buffer, and a version count buffer. The store queue includes an entry for each store instruction in the instruction window of a processor. Some store queue entries include resolved store addresses, and some do not. The store forwarding buffer is a set-associative buffer that has entries allocated for store instructions as store addresses are resolved. Each entry in the store forwarding buffer is allocated into a set determined in part by a subset of the store address. When the set in the store forwarding buffer is full, an older entry in the set is discarded in favor of the newly allocated entry. A version count buffer including an array of overflow indicators is maintained to track overflow occurrences. As load addresses are resolved for load instructions in the instruction window, the set-associative store forwarding buffer can be searched to provide memory disambiguation.

In a navigation device, multi-layered menu windows are sequentially displayed in a display unit and narrowed down by repeatedly selecting an item in each menu window to thereby consequently display a certain instruction window for instructing an execution of a function. This selection procedure is stored such that a selection record, which indicates an association with the certain instruction window, is assigned to each of the selected items in the displayed menu windows. When a certain item assigned the selection record is operated more than a predetermined time period, the currently displayed menu window including the certain item is switched to the certain instruction window without intermediate menu windows displayed. Thus, when intending to display the certain instruction window, which was previously displayed after the selection procedure, a user can significantly simplify the selection procedure and decrease workloads.

A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.

An instruction rollback processor system according to the present invention is provided. The instruction rollback processor system includes: an instruction window buffer storing a plurality of instructions not yet executed and are arranged in a predetermined order; a multiplexer receiving an output of the instruction window buffer; and a rollback unit connected between the output side of the multiplexer and another input of the multiplexer.

The device information of an information processing apparatus is acquired. It is determined, based on the acquired device information, whether a function of the information processing apparatus is usable. Upon determining that the function of the information processing apparatus is usable, a file to display the execution instruction window of processing using the function of the information processing apparatus is requested of the server. On the other hand, upon determining that the function of the information processing apparatus is not usable, a file to display a warning window is requested from the server.

Distinct system registers for logical processors are disclosed. In one example of the disclosed technology, a processor includes a plurality of block-based physical processor cores for executing a program comprising a plurality of instruction blocks. The processor also includes a thread scheduler configured to schedule a thread of the program for execution, the thread using the one or more instruction blocks. The processor further includes at least one system register. The at least one system register stores data indicating a number and placement of the plurality of physical processor cores toform a logical processor. The logical processor executes the scheduled thread. The logical processor is configured to execute the thread in a continuous instruction window.

A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction window whether there is a data dependency relationship between the instruction that will be stored in the instruction window and a previous instruction stored in the instruction window. When there is a data dependency relationship, the execution result of the previous instruction of one cluster is communicated to a register cache of another cluster that executes the instruction having a data dependency relationship with the previous instruction.

The present invention relates to a method and system for determining the status of each entry in an instruction window buffer in multi-processor, parallel processing environments. A combinatorial circuit, which automatically generates active instruction window status information, is added to the buffer itself. This status information is used by a plurality of processes like renaming registers and issuing and committing instructions as an output associated with a respective buffer entry.

A processor core in an instruction block-based microarchitecture is configured so that an instruction window and operand buffers are decoupled for independent operation in which instructions in the block are not tied to resources such as control bits and operands that are maintained in the operand buffers. Instead, pointers are established among instructions in the block and the resources so thatcontrol state can be established for a refreshed instruction block (i.e., an instruction block that is reused without re-fetching it from an instruction cache) by following the pointers. Such decoupling of the instruction window from the operand space can provide greater processor efficiency, particularly in multiple core arrays where refreshing is utilized (for example when executing program codethat uses tight loops), because the operands and control bits are pre-validated.

The present invention is an economical exercise trainer or workout of the arm, waist and abdomen. It is an economically improved design for workout of the arm, waist and abdomen. On the top portion of the unit frame is a video signal instruction window and at the bottom is disposed a slightly protruded driven pulley and swing roller. Inside the unit frame is disposed a circuit controller for controlling the video signal instruction window to generate different lamp shadow direction changes. The driven pulley and the swing roller are slightly protruded beyond the bottom of the stand and between the driven pulley and shaft sleeve rod is disposed a reset spring, and two sides of the shaft rod protrude leftward and rightward to form the grip handles for holding. Such repeated back and forth exercise would be effective for workout of your arm, waist and abdomen.

A method and system are described for simulating a set of instructions to be executed on a processor. The method comprises performing a performance simulation of the processor over a number of simulation cycles. Performing the performance simulation of the processor comprises modeling an instruction window for the cycle and deriving a performance parameter of the processor without modeling a reorder buffer, issue queue(s), register renaming, load-store queue(s) and other buffers of the processor.

The invention relates to an instruction obtaining device for a processor. The instruction obtaining device comprises an instruction caching unit, an instruction buffer unit, an instruction window and an instruction achieving logical unit, wherein the instruction caching unit is used for storing instructions and transmitting the instructions stored in the instruction caching unit to the instruction buffer unit in order; the instruction buffer unit is used for transmitting instructions needing to be executed at present and obtained by the instruction achieving logical unit at one time to the instruction window to be stored; the instruction achieving logical unit obtains the instructions from the instruction window, processes the instructions and outputs and executes the instructions; the instruction achieving logical unit also returns read pointers and write pointers of current execution instructions back to the instruction buffer unit. The invention further relates to a processor with the instruction obtaining device. The instruction obtaining device for the processor and the processor with the instruction obtaining device have the advantage of shortening instruction output time on the whole.

The invention provides an automatic early warning window lowering device for preventing human body suffocation in the vehicle. The automatic early warning window lowering device includes a start button. When the start button is pressed, the control module controls the timing module to perform timing. Start the human body sensing module; during the timing of the timing module, the human body sensing module senses whether there are human vital signs and transmits the feedback signal to the control module; the control module controls the motor controller according to the feedback signal of the human body sensing module; the stepper motor According to the instructions of the motor controller, the window lifting device is controlled, and then the opening and closing of the car windows are controlled. The present invention utilizes sensor induction to determine whether there is human vital signs in the vehicle within a preset time when the vehicle stops running, and then utilizes a stepping motor to control the switch, opening size and speed of the vehicle window to solve the problem of human body in the vehicle. The problem of being trapped or opening a window by mistake.

Systems and methods are disclosed for allocating resources to contexts in block-based processor architectures. In one example of the disclosed technology, a processor is configured to spatially allocate resources between multiple contexts being executed by the processor, including caches, functional units, and register files. In a second example of the disclosed technology, a processor is configured to temporally allocate resources between multiple contexts, for example, on a clock cycle basis, including caches, register files, and branch predictors. Each context is guaranteed access to its allocated resources to avoid starvation from contexts competing for resources of the processor. A results buffer can be used for folding larger instruction blocks into portions that can be mapped to smaller-sized instruction windows. The results buffer stores operand results that can be passed to subsequent portions of an instruction block.

Performing distributed branch prediction using fused processor cores in processor-based systems is disclosed. In one aspect, a distributed branch predictor is provided as a plurality of processor cores supporting core fusion. Each processor core is configured to receive a program identifier from another of the processor cores (or from itself), generate a subsequent predicted program identifier, and forward the predicted program identifier (and, optionally, a global history indicator) to the appropriate processor core responsible for handling the next prediction. The processor core also fetches a header and/or one or more instructions for the received program identifier, and sends the header and/or the one or more instructions to the appropriate processor core for execution. The processor core also determines the processor core that will handle execution of the predicted program identifier, and sends that information to the processor core that received the predicted program identifier as an instruction window tracker.