407 results about "Data dependency" patented technology

A method and system is described for video encoding with multiple parallel encoders. The system uses multiple encoders which operate in different rows of the same slice of the same video frame. Data dependencies between frames, rows, and blocks are resolved through the use of a data network. Block information is passed between encoders of adjacent rows. The system can achieve low latency compared to other parallel approaches.

Methods and apparatus are described for updating a database using a multi-dimensional data model in which data corresponding to the database are organized in multi-dimensional blocks. Each block has summary information associated therewith corresponding to a current state of evolution of the associated block. Dependency information is maintained in the data model which identifies data dependencies within and among the blocks. Change information is maintained which identifies changes made to particular ones of the blocks and times at which the changes were made. The database is updated with reference to the dependency information, the summary information, and the change information. At least some of the blocks are updated without reference to all dependents thereof. In some implementations, the underlying database may be a relational database, the data from the relational database being mapped to the multi-dimensional data model.

An input/output (I/O) method, system, and computer program product are disclosed. An incoming I/O request is received from an application running on a processor. A tree structure including processor-executable instructions defines one or more layers of processing associated with the I/O request. The instructions divide the data in the I/O request into one or more chunks at each of the one or more layers of processing. Each instruction has an associated data dependency to one or more corresponding instructions in a previous layer. The instructions are sorted into an order of processing by determining a location of each chunk and data dependencies between chunks of different layers of processing. One or more instructions are inserted into a schedule that depends at least partly on the order of processing. The I/O request is serviced by executing the instructions according to the schedule with the processor according to the order of processing.

A computer-implemented method of automatically generating an embedded system on the basis of an original computer program, comprising analyzing the original computer program, comprising a step of compiling the original computer program into an executable to obtain data flow graphs with static data dependencies and a step of executing the executable using test data to provide dynamic data dependencies as communication patterns between load and store operations of the original computer program, and a step of transforming the original computer program into an intermediary computer program that exhibits multi-threaded parallelism with inter-thread communication, which comprises identifying at least one static and/or dynamic data dependency that crosses a thread boundary and converting said data dependency into a buffered communication channel with read/write access.

A processing architecture supports executing instructions in parallel after identifying at least one level of dependency associated with a set of traces within a segment of code. Each trace represents a sequence of logical instructions within the segment of code that can be executed in a corresponding operand stack. Scheduling information is generated based on a dependency order identified among the set of traces. Thus, multiple traces may be scheduled for parallel execution unless a dependency order indicates that a second trace is dependent upon a first trace. In this instance, the first trace is executed prior to the second trace. Trace dependencies may be identified at run-time as well as prior to execution of traces in parallel. Results associated with execution of a trace are stored in a temporary buffer (instead of memory) until after it is known that a data dependency was not detected at run-time.

The invention discloses a parallel transaction execution method based on a blockchain. Firstly, a data unit on the datachain is subjected to index numbering, the parallel transaction of a user needs to provide a data index which needs to be read and written for transaction execution in addition to basic transaction contents. The serial transaction of the user only needs to provide the basic transaction contents. A node arranges parallel processing according to the data dependency relationship of the parallel transaction, and the transaction which can not carry out concurrence and the serial transaction can be executed in sequence.

An improved system and method for a task management library to execute map-reduce applications is provided. A map-reduce application may be operably coupled to a task manager library and a map-reduce library on a client device. The task manager library may include a wrapper application programming interface that provides application programming interfaces invoked by a wrapper to parse data input values of the map-reduce application. The task manager library may also include a configurator that extracts data and parameters of the map-reduce application from a configuration file to configure the map-reduce application for execution, a scheduler that determines an execution plan based on input and output data dependencies of mappers and reducers, a launcher that iteratively launches the mappers and reducers according to the execution plan, and a task executor that requests the map-reduce library to invoke execution of mappers on mapper servers and reducers on reducer servers.

A method of tracking instruction dependency in a processor issuing instructions speculatively includes recording in an instruction dependency array (IDA) an entry for each instruction that indicates data dependencies, if any, upon other active instructions. An output vector read out from the IDA indicates data readiness based upon which instructions have previously been selected for issue. The output vector is used to select and read out issue-ready instructions from an instruction buffer.

A circuit (10) for multiplying two floating point operands (A and C) while adding or subtracting a third floating point operand (B) removes latency associated with normalization and rounding from a critical speed path for dependent calculations. An intermediate representation of a product and a third operand are selectively shifted to facilitate use of prior unnormalized dependent resultants. Logic circuitry (24, 42) implements a truth table for determining when and how much shifting should be made to intermediate values based upon a resultant of a previous calculation, upon exponents of current operands and an exponent of a previous resultant operand. Normalization and rounding may be subsequently implemented, but at a time when a new cycle operation is not dependent on such operations even if data dependencies exist.

Streaming data may be decoded by dividing a process for decoding the streaming data into two or more tasks based on data dependencies between the two or more tasks. The two or more tasks may be executed in parallel on three or more processors in a way that balances a processing load of executing the two or more tasks among the three or more processors.

An Adaptive Software Application consists of several types of modules, called Adaptive Units, which are highly parameterized such that they can adapt to varying business requirements by virtue of externally provided parameters. An Adaptive Application is assembled through repeated use of various combinations of different types of Adaptive Units. Large and complex business systems can be rapidly implemented through this approach. An Adaptive Unit includes an interface component that can present information to and accept information from the outside world (such as a web page or a system interface), a processing logic component that can manipulate and evaluate information based on received parameters received (such as comparisons and decisions as in the case of data dependency decisions), and a data persistence logic component that retrieves, adds, updates, and deletes data targeting one or more Occurrence Databases. All three components of an Adaptive Unit are parameter driven. These parameters are not specific to any particular business. One embodiment for providing parameters to these components includes a Definition Database. There may be one or more Occurrence Databases depending on the number of business processes supported by the business application for which the Adaptive Application is being adapted. The Occurrence Database includes generic (also referred to as meta model driven) tables that are not specific to any particular business.

The described embodiments provide a system that executes program code. While executing program code, the processor encounters at least one vector instruction and at least one vector-control instruction. The vector instruction includes a set of elements, wherein each element is used to perform an operation for a corresponding iteration of a loop in the program code. The vector-control instruction identifies elements in the vector instruction that may be operated on in parallel without causing an error due to a runtime data dependency between the iterations of the loop. The processor then executes the loop by repeatedly executing the vector-control instruction to identify a next group of elements that can be operated on in the vector instruction and selectively executing the vector instruction to perform the operation for the next group of elements in the vector instruction, until the operation has been performed for all elements of the vector instruction.

A program parallelization supporting apparatus determines a determinacy in at least one dependency relationship of a data dependency, a control dependency and a pointer dependency in a program, extracts a critical path in the program, and extracts a processing instruction which exists on the critical path and has a non-deterministic determinacy in the dependency relationship. Furthermore, if a process related to a path of the extracted non-deterministic processing instruction is parallelized and the path of the non-deterministic processing instruction is deleted, the program parallelization supporting apparatus outputs parallelization labor hour information depending on the number of dependency relationships disturbing the parallelization and parallelization effect information depending on the number of processing instructions which are shortened by the parallelization.

One embodiment of the present invention provides a system which supports out-of-order issue in a processor that normally executes instructions in-order. The system starts by issuing instructions from an issue queue in program order during a normal-execution mode. While issuing the instructions, the system determines if any instruction in the issue queue has an unresolved short-latency data dependency which depends on a short-latency operation. If so, the system generates a checkpoint and enters an out-of-order-issue mode, wherein instructions in the issue queue with unresolved short-latency data dependencies are held and not issued, and wherein other instructions in the issue queue without unresolved data dependencies are allowed to issue out-of-order.

The disclosed embodiments relate to a system that executes program instructions on a processor. During a normal-execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system speculatively executes subsequent instructions in a lookahead mode to prefetch future loads. While executing in the lookahead mode, if the processor determines that the lookahead mode is unlikely to uncover any additional outer-level cache misses, the system terminates the lookahead mode. Then, after the unresolved data dependency is resolved, the system recommences execution in the normal-execution mode from the instruction that triggered the lookahead mode.

Embodiments include systems and methods for handling task dependencies in a runtime environment using dependence graphs. For example, a computer-implemented runtime engine includes runtime libraries configured to handle tasks and task dependencies. The task dependencies can be converted into data dependencies. At runtime, as the runtime engine encounters tasks and associated data dependencies, it can add those identified tasks as nodes of a dependence graph, and can add edges between the nodes that correspond to the data dependencies without deadlock. The runtime engine can schedule the tasks for execution according to a topological traversal of the dependence graph in a manner that preserves task dependencies substantially as defined by the source code.

A data dependency path calculator for a semantic search engine is provided. A body of semantically related data is modeled according to a semantic data model. A user is presented a list of data elements from which they may select desired data elements. The system automatically calculates all of the possible paths through the database that may be used to retrieve meaningful data based on the selected data elements. The available data dependency paths are returned to the user for selection. The system further provides a type of data permission that allows restricted data elements to be used as a pass-through data element for relating, connecting and retrieving non-restricted data. Thus, a user can use restricted data to create data dependency paths to retrieve meaningful data. The system further provides for defining access privileges for all levels of data structures, allowing data to be secured with an increased level of granularity than previously possible.

In one embodiment of the present invention a driver configures a graphics pipeline implemented in a cache tiling architecture to perform dynamically-defined multi-pass rendering sequences. In operation, based on sequence-specific configuration data, the driver determines an optimized tile size and, for each pixel in each pass, the set of pixels in each previous pass that influence the processing of the pixel. The driver then configures the graphics pipeline to perform per-tile rendering operations in a region that is translated by a pass-specific offset backward—vertically and/or horizontally—along a tiled caching traversal line. Notably, the offset ensures that the required pixel data from previous passes is available. The driver further configures the graphics pipeline to store the rendered data in cache lines. Advantageously, the disclosed approach exploits the efficiencies inherent in cache tiling architecture while honoring highly configurable data dependencies between passes in multi-pass rendering sequences.

The described embodiments include a processor that determines instructions that can be issued based on unresolved data dependencies. In an issue unit in the processor, the processor keeps a record of each instruction that is directly or indirectly dependent on a base instruction. Upon determining that the base instruction has been deferred, the processor monitors instructions that are being issued from an issue queue to an execution unit for execution. Upon determining that an instruction from the record has reached a head of the issue queue, the processor immediately issues the instruction from the issue queue.

A loop having an index set that can be distributed but with data dependency on the right side of an assignment expression that is indefinite can be parallelized. The index set of the loop is distributed to a plurality of processors. A processor set that uses values that are defined before the loop and a processor set using values defined after the loop is calculated. Code is interpolated that enables these processors to engage in communication before and after loops, thereby eliminating communication between processors in the loop and improving the execution speed of the program.

A method for pipeline parallelizing a control program for multi-core execution includes using (12) data dependency analysis on a control program to identify tasks that can be performed in parallel, identifying (13) a largest task Tmax requiring the most execution time of the identified tasks, identifying (14) cut-points in the largest task Tmax where data dependency delays decouple the task, inserting (15) delayed data dependencies into cut-points of the largest task Tmax to create N pipeline sub-tasks, in which N is a number of cores available to a processor on which the control program will be executed, and scheduling (16) the tasks and pipeline sub-tasks to the available processor cores.

Guidance provision to the creation of an electronic design is facilitated through a method that includes facilitating interactive exploration of the electronic design by a designer to aid the designer in formulating his/her guidance, and facilitating the designer in interactively providing the formulated guidance. In one embodiment, facilitation of interactive exploration by the designer include facilitating interactive cross-probing into a number of issues about the design, including generated candidate architectures for the design. In one embodiment, the issues available for cross probing include inter-dependencies of data and mobility of operations of the design, as well as occupation of hardware resources for the generated candidate architectures. In one embodiment, Gantt diagrams are employed to facilitate navigation by the designer in performing the interactive cross probing. Gantt diagrams graphically representing the generated candidate architectures are selectively presented to the designer. Data dependencies may be graphically depicted on the Gantt diagrams. Additionally, various aspects of the generated candidate architectures may be correlated back to the behavioral specification of the electronic design for the designer. In one embodiment, the designer may also modified the constraints on the electronic design interactively, applying the information the designer learned through the interactive exploration.