3241 results about "Logic circuitry" patented technology

A memory device can be coupled to a host device using a compute express link (CXL) interconnect. The memory device can include a host interface circuit and processing logic circuitry, such as a subsystem manager circuit. The host interface circuit of the memory device can be configured to operate in one of an autonomous mode and a distribution mode. In the autonomous mode, the host interface circuit is configured to maintain a connection between the host device and the memory device while the subsystem manager circuit of the memory device is unavailable, such as when the subsystem manager circuit undergoes a reset routine. In the distribution mode, the host interface circuit is configured to allow communication between the host device and the subsystem manager circuit of the memory device.

The invention provides a ternary logic gate circuit, a calculation circuit, a chip and electronic equipment. The ternary logic gate circuit provided by the invention can realize addition and subtraction of 1 to an input logic value. Based on the ternary logic gate circuit, 27 univariate functions of ternary logic are utilized, the ternary logic gate circuit is applied to the ternary logic circuit, the purpose of simplifying the structure of the ternary logic circuit can be achieved, the number of transistors in the ternary logic circuit can be reduced, the power consumption of the ternary logic circuit can be reduced, and the reliability of the ternary logic circuit is improved. And the calculation efficiency of the ternary logic circuit is improved.

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

The invention provides a display panel, a driving method thereof, a driving circuit and a display device.The display panel comprises a plurality of scanning lines, a plurality of data lines and pixel units arranged in an array mode, and each pixel unit comprises a pixel electrode, a storage capacitor, a first transistor, a comparison circuit and a switch logic circuit; the comparison circuit compares a signal input by a data line with a first reference voltage and outputs a comparison signal corresponding to high and low levels, and the switch logic circuit performs logic judgment and corresponding on-off on the level of the signal input by the scanning line and the comparison signal, so that the line scanning signal and the data signal are input to the first transistor; the data lines and the scanning lines are connected to control whether data signals of the pixel electrodes and the storage capacitors are written and refreshed or not, the pixel units can be controlled to maintain a current picture and switch a display picture by inputting data signals and line scanning signals of different sizes to the data lines and the scanning lines, independent control over the single pixel unit can be achieved, and the display requirements of different refresh rates are met.

Described embodiments include a control circuit with a first comparator having a first comparator input receiving a first threshold voltage, and a second comparator input coupled to an output voltage terminal. A second comparator has a third comparator input receiving a second threshold voltage, and a fourth comparator input coupled to a current output terminal. A first logic circuit provides a true signal at its output responsive to a particular number of its inputs receiving a true input. A second logic circuit has inputs coupled to the first comparator output, and to the first logic output. A variable resistance circuit has an output coupled to a mode detection output. An amplifier has inputs coupled to the variable resistance circuit output, and a third reference voltage source. A duty cycle generation circuit provides a respective pulse width modulation (PWM) signal at each of its respective duty cycle outputs.

The invention discloses a method and a device for improving positive and negative recognition accuracy of a test strip and a storage medium. The method comprises the following steps: acquiring image data of C-line and T-line areas of a test strip by using a multispectral camera; performing feature extraction and optimization processing on the acquired multispectral image; the abstraction detection process is a logic circuit model, and a node feature matrix is constructed; randomly injecting a fault into the model, simulating an environment problem, and generating a test vector; training a graph convolutional neural network model by using the failure response data, and adding cavity convolution; the trained model is applied to analyze real-time data, predict faults and evaluate color changes; if the detection is abnormal, accurately distinguishing red types by using a color difference matrix and time sequence analysis; and calculating the confidence coefficient based on the optimized features and the high-precision color information, and determining an object frame. By implementing the method provided by the invention, the problems of low accuracy, weak anti-interference capability and lack of effective fault simulation in the existing test strip detection technology can be solved.

The invention provides a circuit logic synthesis method for FPGA mapping based on reinforcement learning, and aims at solving the problem that in a traditional netlist optimization method, a circuit is not seen in model optimization, and the capacity is insufficient. The method comprises the following steps: firstly, constructing a logic comprehensive data set, and then preprocessing the data set to obtain statistical characteristics and a graph structure of a circuit; then, a logic comprehensive model based on reinforcement learning and aiming at FPGA mapping is constructed, pre-training is conducted through the preprocessed data set, and finally logic optimization is conducted on a circuit through the pre-trained logic comprehensive model based on reinforcement learning and aiming at FPGA mapping. According to the circuit feature extraction module, a GNN module is adopted to analyze a logic circuit and a netlist structure to obtain graph embedding, statistical features of the logic circuit and the netlist are analyzed through an FCN module, the features of the two parts are spliced to obtain an accurate enhanced representation state of the circuit, and the understanding capacity of a reinforcement learning model on different circuits is improved.

There is provided a gaming system that utilizes game-logic circuitry and a presentation assembly for presenting a multi-state bonus game. The bonus game is conducted with a first bonus game feature for a first duration by the presentation assembly presenting a bonus game interface including one or more modifiable game elements associated with the first bonus game feature, presenting first bonus game outcomes, and, in response to detecting a modifier event, updating at least one of the modifiable game elements based on the modifier event. In response to the first duration concluding, the bonus game is conducted with a second bonus game feature for a second duration, wherein the updated modifiable game elements persist between the bonus game features. The bonus game within the second duration includes the presentation assembly presenting second bonus game outcomes based on the second bonus game feature and the updated modifiable game elements.

A hardware sampling device (200) and related method for generating observations of arbitrary random variables from probabilistic bits are disclosed. The sampling device comprises a programming unit (250) for adjusting the mean value of probabilistic bits generated by each one of a plurality of probabilistic bit generators (271a-h), a binary selection tree structure (210) comprising a plurality of nodes, and a detection logic circuit (240) for detecting a tie condition for each depth stage of the binary selection tree (210). Each node comprises a selector circuit (213) connected between a pair of input terminals (211a-b) and an output terminal (212). The and configured to randomly admit one of the two input signals to the output terminal if a tie condition is detected, or else admit the input signal which represents a logical '1'. The position index bit related to the admitted input signal is supplied to the output terminal of the node and concatenated with a sequence of previously transmitted position index bits.

A control circuit for a switching converter includes a compensation circuit, a ramp generation circuit, a comparison circuit and a logic circuit. The compensation circuit is configured to generate a compensation signal in response to a feedback signal and a reference signal. The ramp generation circuit is configured to generate a ramp signal. The comparison circuit is configured to provide a comparison signal in response to the compensation signal and the ramp signal. The logic circuit is configured to provide the PWM control signal to the switching converter. The PWM control signal is at a first voltage level when a value of the ramp signal reaches a value of the compensation signal. The PWM control signal is at a second voltage level in response to the clock signal.

There are provided a gaming machine and method that utilize game-logic circuitry and a presentation assembly configured to present a plurality of symbol-bearing reels and an array. The symbols include base symbols, value-bearing symbols and catalyst symbols. The value-bearing symbols may bear credit amounts or be associated with a progressive or non-progressive jackpot. The reels are spun to land symbols from the reels in the array. In response to the landed symbols including at least one catalyst symbol, a number of enhancements to the landed symbols may be randomly selected and the selected enhancements may be animated via a presentation assembly. The enhancements may be applied a random number of times for each appearance of a landed catalyst symbol. A landed catalyst symbol may also trigger a number of bonus free spins of the reels during which the catalyst symbol remains locked in place in the array.

The invention relates to the technical field of monolithic integration, in particular to a monolithic three-dimensional integration implementation method and device for a hybrid precision in-memory computing architecture, and the method comprises the steps: obtaining a silicon-based CMOS technology and a subsequent integration technology in a monolithic three-dimensional integration technology; manufacturing a control logic circuit on the computing architecture in the mixed precision memory by adopting a silicon-based CMOS (Complementary Metal Oxide Semiconductor) process; a plurality of functional layers are vertically stacked on a logic circuit by adopting a back-end integration process, communication among the functional layers is realized through interlayer dielectric via holes in the vertical direction, an analog in-memory array, a digital in-memory array and a cache are arranged on the functional layers, the analog in-memory array realizes matrix and vector multiplication with fixed weight, and the digital in-memory array realizes matrix and vector multiplication with fixed weight. And the array in the digital memory realizes matrix multiplication of refresh weight. Therefore, the problems that an in-memory computing architecture usually needs to occupy a relatively large part of chip area, the computing efficiency is relatively low and the like in related technologies are solved.

The present application belongs to the technical field of wireless communications and radar systems. Disclosed are a dual-band fusion and multiplexing frequency source, chips, a radio-frequency transceiver, a system, and a device. The system comprises: a full-function millimeter-wave CMOS 4+1 phased array chip, which is connected to an antenna end, and is used for realizing signal processing and frequency conversion between a millimeter-wave signal and a C-band intermediate-frequency signal, performing phase control and gain adjustment on the millimeter-wave signal, and providing an internal frequency source and a calibration function; a C-band front end, which is connected to the antenna end, and is used for receiving or transmitting a C-band signal; a C-band / intermediate-frequency transceiver multiplexing chip, which is used for performing frequency conversion between a C-band or intermediate-frequency signal and a baseband signal in a multiplexing manner, and performing signal processing and gain control on the C-band intermediate-frequency signal; a dual-band fusion and multiplexing frequency source, which is used for providing a local oscillator signal; and an all-digital control logic circuit, which is used for providing a control instruction. The present application improves the efficiency and performance of dual-band joint communications.

A network interface module for coupling a host device to a switched network as a network node is described. The network interface module comprises a single half-duplex port for communicatively coupling to a shared bus of the switched network, at least one frame queue sized to store one multicast read frame received via the shared bus, and logic circuitry. The logic circuitry is configured to decode a read command for the interface module included in a payload of the multicast read frame that includes multiple read commands for other network nodes of the switched network, and transmit a response frame including read data on the shared bus when detecting the shared bus is available for transmitting.

The invention relates to the technical field of quantum compilation, and discloses an error suppression compilation optimization method for a quantum computer, which comprises the following steps of: capturing a physical quantum gate operation error rate and a hardware topological structure of a quantum processor for executing a mapping task, and constructing a hardware feature matrix; capturing gate interaction attributes of a to-be-compiled quantum logic circuit, and constructing a circuit characteristic matrix; according to the constructed hardware feature matrix and circuit feature matrix, establishing a mapping scheme representation model and a corresponding overhead function; solving the overhead function by using a genetic algorithm, and searching a mapping scheme which minimizes the overhead function value under the condition of meeting the resource constraint of the quantum processor; applying the optimized mapping scheme to the quantum logic circuit to be compiled, and compiling and optimizing the quantum logic circuit to be compiled; according to the method, the problems of poor adaptability, insufficient error rate optimization and the like of a quantum bit allocation scheme in the prior art are solved, and low-error and reliable quantum circuit mapping processing is realized.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

The utility model discloses a digital auxiliary simulation LDO circuit without an off-chip capacitor. A simulation main loop of the circuit comprises an error amplifier, a buffer stage circuit, a simulation power stage circuit and a VG voltage detection circuit. The digital auxiliary loop includes a digital control logic circuit, a ring oscillator circuit, and a digital power stage circuit. By introducing the digital power adjusting tube, the parasitic capacitance of the grid electrode of the analog power tube is reduced, the pole of the grid electrode is located at high frequency, and on the basis, the super source follower is added to push the pole to higher frequency, so that the circuit has better loop stability. In a steady state, the digital auxiliary loop is forbidden, and the analog main loop can ensure strict adjustment, low quiescent current and no switching noise at the output end; when a load current suddenly changes, a ring oscillator in the digital auxiliary loop is called to generate a clock signal, and the number of conducted digital power tubes is changed, so that response time is not limited by a clock period, dependence on an external clock is avoided, meanwhile, voltage precision and rapid transient response are guaranteed, and static power consumption of the circuit is reduced.

An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

The invention discloses a time domain and security attribute joint modeling method based on RTL information flow, belongs to the technical field of hardware security, and solves the problems of how to model time domain attributes from the perspective of information flow to design security behaviors and detect time sequence channel attacks. The security behavior is modeled and designed by the security attribute and the time domain attribute from the angle of information flow, the additional time domain attribute tracking logic circuit is used for capturing data flow and the updating time of a signal in the process, the security attribute and the time domain attribute of RTLIFT are modeled in a dual mode, and the security behavior is modeled and designed by analyzing propagation of a time label. According to the method, how the input change affects the output time change can be determined, so that the model can capture and analyze the time difference caused by the imbalance of the execution path, and the hardware time side channel possibly causing sensitive information leakage can be effectively identified.

Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

An electronic component. The electronic component includes a base; a first semiconductor device attached to the base and having: a first Gallium nitride (GaN)-based switch having a first gate, a first source and a first drain, the first gate arranged to control a current flow between the first source and the first drain; a second GaN-based switch having a second source, a second gate and a second drain, the second gate coupled to the first gate, and the second drain coupled to the first drain. In one aspect, the electronic component also includes a second semiconductor device attached to the base and having: a logic circuit coupled to the second source and arranged to detect a magnitude of the current flow; and a driver circuit coupled to the first and second gates, the driver circuit arranged to control on and off states of the first and second GaN-based switches.

An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.

The invention relates to an integrated circuit, a processor and a computing device for data processing. The integrated circuit comprises a data storage circuit and a matrix operation circuit. The data storage circuit is configured to store matrix data. The matrix operation circuit includes: a control logic circuit configured to: read a first matrix and a second matrix from a data storage circuit based on a specified data format indicating that elements in the first matrix are floating point type data and elements in the second matrix are integer type data; and the arithmetic logic circuit is configured to convert elements in the first matrix and the second matrix into elements of a target floating point type according to the data types of the elements indicated by the specified data format, and determine result matrixes corresponding to the first matrix and the second matrix based on the converted elements of the first matrix and the second matrix. The integrated circuit is helpful for improving the matrix operation efficiency and reducing the occupation of storage space and the data transmission quantity.

The invention provides a system and a method for detecting and preventing early explosion of an electronic detonator chip. The method comprises the following steps: S1, detecting a current charging voltage; s2, selecting a reference voltage, comparing the reference voltage with the current charging voltage, and obtaining a comparison result based on a comparator; and S3, taking an early explosion prevention measure according to a comparison result. According to the invention, the multi-gear reference circuit and the comparator are used, high-precision detection of voltage change of the energy storage capacitor is realized, and the digital control logic circuit is matched to detect that the voltage of the energy storage capacitor drops abnormally and rapidly, so that an early explosion symptom is identified; by arranging the bypass switch, the energy storage capacitor is short-circuited to the ground when an early explosion symptom is recognized, so that energy of the energy storage capacitor is not released through the ignition element, early explosion is prevented, and good practicability is achieved.

The invention discloses a superconducting transistor device and a preparation method thereof, and belongs to the field of superconducting electronics, and the superconducting transistor device comprises a first grid electrode and / or a second grid electrode, a superconducting nanowire, a first electrode and a second electrode. Wherein the first grid electrode and the second grid electrode are located on the two sides of the superconducting nanowire respectively, or the first grid electrode or the second grid electrode is located on the side edge of the superconducting nanowire; two ends of the superconducting nanowire are respectively connected with the first electrode and the second electrode; the first grid electrode and / or the second grid electrode, the first electrode and the second electrode are used for being connected with an external electrode. The superconducting transistor device with a logic function is obtained through construction of the superconducting nanowires and the grid electrodes, the structure of a superconducting logic circuit is simplified, the integration level and expansibility of the device are improved, the preparation difficulty and the requirement for magnetic shielding are greatly reduced, and a new technical route is provided for development of superconducting integrated circuits.

A quantum logic circuit comprising: a plurality of quantum logic gates configured in a nested structure comprising layers; wherein each of the layers operates on a number of qubits to encode F features from at least one data point, wherein the number of qubits in a preceding layer is higher than the number of qubits in a subsequent layer, and wherein the F features are coherently aggregated in each subsequent layer without measurement thereby reducing the number of qubits required to encode the F features for processing.

The present disclosure provides a memory device and a control method for the memory device. The memory device includes a memory array and a control logic circuit. The memory array includes memory cell rows. The control logic circuit comprises a counter and a reset circuit. The counter counts the number of accesses performed on the memory cell rows to generate a count value corresponding to the memory cell row accessed among the memory cell rows, and sets the count value to a random value when the count value is equal to a predetermined value and when the accesses are performed. The reset circuit resets the count value to a predetermined value in response to a refresh command. When the count value reaches a threshold value, the control logic circuit arranges a memory cell row near the accessed memory cell row into a mitigation operation.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

A semiconductor device (300A) includes a first layer (20) and a second layer (30) over the first layer. The first layer includes a logic circuit portion (23). The second layer includes a level shifter portion (24) and a pixel circuit (51). The logic circuit portion has a function of supplying a first signal for operating the level shifter portion to the level shifter portion. The level shifter portion has a function of supplying a second signal with a larger amplitude than the first signal to the pixel circuit. The logic circuit portion includes a transistor including silicon in a semiconductor layer where a channel is formed. Each of the level shifter portion and the pixel circuit includes a transistor including a metal oxide in a semiconductor layer where a channel is formed.