2563 results about "Logic circuitry" patented technology

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

The invention provides a circuit logic synthesis method for FPGA mapping based on reinforcement learning, and aims at solving the problem that in a traditional netlist optimization method, a circuit is not seen in model optimization, and the capacity is insufficient. The method comprises the following steps: firstly, constructing a logic comprehensive data set, and then preprocessing the data set to obtain statistical characteristics and a graph structure of a circuit; then, a logic comprehensive model based on reinforcement learning and aiming at FPGA mapping is constructed, pre-training is conducted through the preprocessed data set, and finally logic optimization is conducted on a circuit through the pre-trained logic comprehensive model based on reinforcement learning and aiming at FPGA mapping. According to the circuit feature extraction module, a GNN module is adopted to analyze a logic circuit and a netlist structure to obtain graph embedding, statistical features of the logic circuit and the netlist are analyzed through an FCN module, the features of the two parts are spliced to obtain an accurate enhanced representation state of the circuit, and the understanding capacity of a reinforcement learning model on different circuits is improved.

A hardware sampling device (200) and related method for generating observations of arbitrary random variables from probabilistic bits are disclosed. The sampling device comprises a programming unit (250) for adjusting the mean value of probabilistic bits generated by each one of a plurality of probabilistic bit generators (271a-h), a binary selection tree structure (210) comprising a plurality of nodes, and a detection logic circuit (240) for detecting a tie condition for each depth stage of the binary selection tree (210). Each node comprises a selector circuit (213) connected between a pair of input terminals (211a-b) and an output terminal (212). The and configured to randomly admit one of the two input signals to the output terminal if a tie condition is detected, or else admit the input signal which represents a logical '1'. The position index bit related to the admitted input signal is supplied to the output terminal of the node and concatenated with a sequence of previously transmitted position index bits.

A control circuit for a switching converter includes a compensation circuit, a ramp generation circuit, a comparison circuit and a logic circuit. The compensation circuit is configured to generate a compensation signal in response to a feedback signal and a reference signal. The ramp generation circuit is configured to generate a ramp signal. The comparison circuit is configured to provide a comparison signal in response to the compensation signal and the ramp signal. The logic circuit is configured to provide the PWM control signal to the switching converter. The PWM control signal is at a first voltage level when a value of the ramp signal reaches a value of the compensation signal. The PWM control signal is at a second voltage level in response to the clock signal.

The invention relates to the technical field of monolithic integration, in particular to a monolithic three-dimensional integration implementation method and device for a hybrid precision in-memory computing architecture, and the method comprises the steps: obtaining a silicon-based CMOS technology and a subsequent integration technology in a monolithic three-dimensional integration technology; manufacturing a control logic circuit on the computing architecture in the mixed precision memory by adopting a silicon-based CMOS (Complementary Metal Oxide Semiconductor) process; a plurality of functional layers are vertically stacked on a logic circuit by adopting a back-end integration process, communication among the functional layers is realized through interlayer dielectric via holes in the vertical direction, an analog in-memory array, a digital in-memory array and a cache are arranged on the functional layers, the analog in-memory array realizes matrix and vector multiplication with fixed weight, and the digital in-memory array realizes matrix and vector multiplication with fixed weight. And the array in the digital memory realizes matrix multiplication of refresh weight. Therefore, the problems that an in-memory computing architecture usually needs to occupy a relatively large part of chip area, the computing efficiency is relatively low and the like in related technologies are solved.

The present application belongs to the technical field of wireless communications and radar systems. Disclosed are a dual-band fusion and multiplexing frequency source, chips, a radio-frequency transceiver, a system, and a device. The system comprises: a full-function millimeter-wave CMOS 4+1 phased array chip, which is connected to an antenna end, and is used for realizing signal processing and frequency conversion between a millimeter-wave signal and a C-band intermediate-frequency signal, performing phase control and gain adjustment on the millimeter-wave signal, and providing an internal frequency source and a calibration function; a C-band front end, which is connected to the antenna end, and is used for receiving or transmitting a C-band signal; a C-band / intermediate-frequency transceiver multiplexing chip, which is used for performing frequency conversion between a C-band or intermediate-frequency signal and a baseband signal in a multiplexing manner, and performing signal processing and gain control on the C-band intermediate-frequency signal; a dual-band fusion and multiplexing frequency source, which is used for providing a local oscillator signal; and an all-digital control logic circuit, which is used for providing a control instruction. The present application improves the efficiency and performance of dual-band joint communications.

A network interface module for coupling a host device to a switched network as a network node is described. The network interface module comprises a single half-duplex port for communicatively coupling to a shared bus of the switched network, at least one frame queue sized to store one multicast read frame received via the shared bus, and logic circuitry. The logic circuitry is configured to decode a read command for the interface module included in a payload of the multicast read frame that includes multiple read commands for other network nodes of the switched network, and transmit a response frame including read data on the shared bus when detecting the shared bus is available for transmitting.

The invention relates to the technical field of quantum compilation, and discloses an error suppression compilation optimization method for a quantum computer, which comprises the following steps of: capturing a physical quantum gate operation error rate and a hardware topological structure of a quantum processor for executing a mapping task, and constructing a hardware feature matrix; capturing gate interaction attributes of a to-be-compiled quantum logic circuit, and constructing a circuit characteristic matrix; according to the constructed hardware feature matrix and circuit feature matrix, establishing a mapping scheme representation model and a corresponding overhead function; solving the overhead function by using a genetic algorithm, and searching a mapping scheme which minimizes the overhead function value under the condition of meeting the resource constraint of the quantum processor; applying the optimized mapping scheme to the quantum logic circuit to be compiled, and compiling and optimizing the quantum logic circuit to be compiled; according to the method, the problems of poor adaptability, insufficient error rate optimization and the like of a quantum bit allocation scheme in the prior art are solved, and low-error and reliable quantum circuit mapping processing is realized.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

The utility model discloses a digital auxiliary simulation LDO circuit without an off-chip capacitor. A simulation main loop of the circuit comprises an error amplifier, a buffer stage circuit, a simulation power stage circuit and a VG voltage detection circuit. The digital auxiliary loop includes a digital control logic circuit, a ring oscillator circuit, and a digital power stage circuit. By introducing the digital power adjusting tube, the parasitic capacitance of the grid electrode of the analog power tube is reduced, the pole of the grid electrode is located at high frequency, and on the basis, the super source follower is added to push the pole to higher frequency, so that the circuit has better loop stability. In a steady state, the digital auxiliary loop is forbidden, and the analog main loop can ensure strict adjustment, low quiescent current and no switching noise at the output end; when a load current suddenly changes, a ring oscillator in the digital auxiliary loop is called to generate a clock signal, and the number of conducted digital power tubes is changed, so that response time is not limited by a clock period, dependence on an external clock is avoided, meanwhile, voltage precision and rapid transient response are guaranteed, and static power consumption of the circuit is reduced.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

The invention discloses a time domain and security attribute joint modeling method based on RTL information flow, belongs to the technical field of hardware security, and solves the problems of how to model time domain attributes from the perspective of information flow to design security behaviors and detect time sequence channel attacks. The security behavior is modeled and designed by the security attribute and the time domain attribute from the angle of information flow, the additional time domain attribute tracking logic circuit is used for capturing data flow and the updating time of a signal in the process, the security attribute and the time domain attribute of RTLIFT are modeled in a dual mode, and the security behavior is modeled and designed by analyzing propagation of a time label. According to the method, how the input change affects the output time change can be determined, so that the model can capture and analyze the time difference caused by the imbalance of the execution path, and the hardware time side channel possibly causing sensitive information leakage can be effectively identified.

An electronic component. The electronic component includes a base; a first semiconductor device attached to the base and having: a first Gallium nitride (GaN)-based switch having a first gate, a first source and a first drain, the first gate arranged to control a current flow between the first source and the first drain; a second GaN-based switch having a second source, a second gate and a second drain, the second gate coupled to the first gate, and the second drain coupled to the first drain. In one aspect, the electronic component also includes a second semiconductor device attached to the base and having: a logic circuit coupled to the second source and arranged to detect a magnitude of the current flow; and a driver circuit coupled to the first and second gates, the driver circuit arranged to control on and off states of the first and second GaN-based switches.

An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.

The invention provides a system and a method for detecting and preventing early explosion of an electronic detonator chip. The method comprises the following steps: S1, detecting a current charging voltage; s2, selecting a reference voltage, comparing the reference voltage with the current charging voltage, and obtaining a comparison result based on a comparator; and S3, taking an early explosion prevention measure according to a comparison result. According to the invention, the multi-gear reference circuit and the comparator are used, high-precision detection of voltage change of the energy storage capacitor is realized, and the digital control logic circuit is matched to detect that the voltage of the energy storage capacitor drops abnormally and rapidly, so that an early explosion symptom is identified; by arranging the bypass switch, the energy storage capacitor is short-circuited to the ground when an early explosion symptom is recognized, so that energy of the energy storage capacitor is not released through the ignition element, early explosion is prevented, and good practicability is achieved.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

A DC / DC converter includes a converter stage to receive an input voltage and to provide an output voltage from the input voltage in accordance with a modulated drive signal. The converter stage further provides a feedback voltage representing the output voltage. A controller circuit includes an error amplifier to receive the feedback voltage and a reference voltage and to provide an error signal based on the feedback voltage and the reference voltage. A PWM modulator receives a clock signal and the error signal and generates a modulated signal based on the clock signal and the error signal, and a logic circuit receives the modulated signal and generates the drive signal for the converter stage based on the modulated signal so that the drive signal has the same duty cycle as the modulated signal, when the duty cycle of the modulated signal is not smaller than a minimum duty cycle value.

Aspects of this disclosure are directed to methods and apparatuses involving the characterization of livestock feeding functions. As may be implemented as or with one or more embodiments herein, networked cameras are configured to capture images of a livestock feed area and machine-vision logic circuitry characterizes, based on the captured images, an amount of available feed and the presence of livestock in the livestock feed area depicted in the captured image over time. Feed-control logic circuitry may assign time-based condition values each respective feed area characterized by the cameras based on the characterized amount of available feed and the characterized presence of livestock provided via the machine-vision logic circuitry. An instruction characterizing the presentation of feed in the feed area may be output based on the assigned time-based condition values and a current time. Such an output may be used to control the presentation amount, timing and / or other feeding characteristics.

A cascoded power switch includes a high-side (HS) switch between an output node and a first voltage supply terminal and a low-side switch. The HS switch includes a first, second, and third transistor in series between the first voltage supply terminal and the output node, and a fourth, fifth, and sixth transistor in series between the first voltage supply terminal and the output node. The first and fourth transistors are in parallel, the second and fifth transistors are in parallel, and the third and sixth transistors are in parallel. A HS driver circuit begins turning on the first transistor in response to assertion of a first control signal and delays turning on the fourth transistor until both the first and second controls signal are asserted. A voltage monitoring circuit includes logic which asserts the second control signal in response to a rise of an output voltage at the output node.

There are provided a gaming machine and method that utilize game-logic circuitry and a graphical user interface configured to present a plurality of symbol-bearing reels, an array and a modifier. The symbols include base symbols, value-bearing symbols and at least one catalyst symbol. The value-bearing symbols may bear credit amounts or be associated with a progressive or non-progressive jackpot. The reels are animated to spin and land symbols from the reels in the array. Winning combinations of the base symbols are paid according to a paytable. If the landed symbols include a catalyst symbol but no value-bearing symbols, the modifier is changed. If the landed symbols include value-bearing symbols and a catalyst symbol, an award based on values borne by the landed value-bearing symbols is modified by the modifier and presented. The modifier is then set to a reset value.

The invention relates to the field of integrated circuits, in particular to a drive control circuit with dead-time control and voltage change rate interference resistance, which comprises a logic circuit, a high-side drive circuit and a low-side drive circuit, and is characterized in that the logic circuit is used for processing input high-low-side PWM (Pulse Width Modulation) control signals and high-low-side logic signals fed back in the circuit; interlocking between high and low side signals is realized; the high-side driving circuit is used for realizing level shift from a low-voltage logic signal to high-voltage driving, generating dead time and inhibiting anti-voltage change rate interference generated when a low-side power tube is conducted; the low-side driving circuit is used for generating dead time and suppressing anti-voltage change rate interference generated when the high-side power tube is conducted; the drive control circuit designed by the invention has the capabilities of dead time control and voltage change rate interference resistance, and the integration level of the circuit is improved while the reliability of the circuit is ensured.

A level shifter according to an embodiment and a display device including the same are disclosed. A level shifter includes a first logic circuit configured to receive a mode selection signal of a first voltage level for selectively driving first and second light-emitting elements that emit light at different viewing angles of a pixel circuit from a timing controller and transmit the mode selection signal; and a second logic circuit configured to convert the mode selection signal of the first voltage level into a mode selection signal of a second voltage level higher than the first voltage level and output the converted mode selection signal of the second voltage level to the pixel circuit.

The invention relates to the technical field of software simulation operation simulation, and discloses a software logic simulation operation control method and system in an audio processor. The control method is applied to logic simulation operation control equipment and specifically comprises the following steps that S101, an audio processor simulation operation request sent by a user side is received, a graphical user interface is generated according to the operation request, and the graphical user interface comprises a logic module list area, a design editing area, an attribute bar and an information display area; and the user side drags an icon of a logic circuit element from the logic module list area to the design editing area. Through a highly integrated graphical interface and intelligent interactive design, the design and simulation efficiency of an audio processor logic circuit is remarkably improved, and by adopting a'drag-and-generate 'module instantiation mechanism, an attribute bidirectional real-time synchronization technology and visual connection and signal type inspection, the reliability of the audio processor logic circuit is greatly improved. Therefore, the user can intuitively and quickly construct the complex circuit topology, and the professional threshold is greatly reduced.

A memory device standby procedure can include idling a first memory device in a low-power standby mode, the first memory device coupled to a memory interface that couples multiple memory devices to a host and includes a command line (CA) and a standby exit line (EX), and the first memory device can include a primary die coupled to multiple secondary dies using an intra-package bus. At the first memory device, the procedure can include waking receiver circuitry on the primary die in response to a state change on the standby exit line, and sampling the command line using logic circuitry on the primary die. When a wakeup message on the command line comprises a chip identification that corresponds to the first memory device, the procedure can include initiating a standby exit procedure for the first memory device.

An integrated circuit includes logic circuits and a network-on-chip in a region of the integrated circuit. The network-on-chip is configurable to transmit at least two of user data, configuration data, and emulation data to the logic circuits. The network-on-chip is configurable to transmit the user data to and from the logic circuits during a user mode of the integrated circuit. The network-on-chip is configurable to transmit the configuration data to the logic circuits for configuring the logic circuits during a configuration mode of the integrated circuit. The network-on-chip is configurable to transmit the emulation data to and from the logic circuits during an emulation mode of the integrated circuit.

The super capacitor charging module in the multi-path power supply standby power logic circuit for the novel Internet of Things meter comprises a resistor module, a diode D1 and a capacitor C1, wherein the resistor module, the diode D1 and the capacitor C1 are connected in series and are formed by connecting resistors R1 and R2 in parallel; the input ends of the resistors R1 and R2 which are connected in parallel are connected with + 5.2 V; one end of the capacitor C1 is grounded, and the other end is respectively connected with the diodes D1 and D2; + 5.2 V is respectively connected with the clock battery power supply AVBAT network and the VIN end of the voltage stabilizer U1 through a diode D3, and the output end of the diode D3 is also grounded through a capacitor C6; one path of network battery current ABATT is grounded through a capacitor C2 and a resistor R4 which are connected in parallel, and the other path of network battery current ABATT is connected with a resistor R3; the output end of the resistor R3 is respectively connected with diodes D4 and D6 and a resistor R5; the output end of the diode D4 is connected to the output end of the diode D3; the resistor R5 is connected with a power supply E1, and the power supply E1 is connected with a capacitor C3 in parallel; the output end of the diode D6 is connected with the output end of a diode D5; the structure is compact and use is convenient.

The invention discloses a path prediction circuit, method and device for a multi-path group connection cache and a processor, and belongs to the field of processors. The circuit prediction circuit comprises an operational circuit unit, a read logic circuit unit, a plurality of counting lookup tables and a judgment circuit unit, the multi-path group connection cache comprises a plurality of cache groups, each cache group comprises a plurality of cache paths, the plurality of cache paths are in one-to-one correspondence with the plurality of counting lookup tables, and each counting lookup table in the plurality of counting lookup tables has a plurality of entries; the operational circuit unit is used for generating an index value corresponding to the memory access address based on the memory access address; the read logic circuit unit is used for accessing an entry corresponding to the index value in each counting lookup table to obtain a plurality of count values, and the ith count value of the plurality of count values indicates the number of cache lines matched with the index value in the ith cache path; and the judgment circuit unit is used for respectively judging the relationship between the plurality of count values and zero. The path prediction circuit reduces the power consumption of the access cache.

A computer-implemented method for testing an instruction cache logic circuit of an integrated circuit, comprising: storing in the cache logic circuit a sequence of instructions including M instructions; reading an initial counter value of a cache access counter; executing the sequence of instructions and, for each instruction executed from the cache logic circuit, incrementing the current counter value of the counter; reading a final counter value of the counter; blocking an execution of instructions unintended by the test for a period lasting from reading the initial counter value until reading the final counter value; subtracting the initial counter value from the final counter value, and comparing the result of said subtraction with the value M.

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.