1174 results about "Logic circuitry" patented technology

A network interface module for coupling a host device to a switched network as a network node is described. The network interface module comprises a single half-duplex port for communicatively coupling to a shared bus of the switched network, at least one frame queue sized to store one multicast read frame received via the shared bus, and logic circuitry. The logic circuitry is configured to decode a read command for the interface module included in a payload of the multicast read frame that includes multiple read commands for other network nodes of the switched network, and transmit a response frame including read data on the shared bus when detecting the shared bus is available for transmitting.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention relates to an analog quantity selection method and system based on a Boolean switch, in particular to the field of industrial automation, and aims to directly realize signal mapping by adopting a pure hardware combinational logic circuit and thoroughly eliminate instruction execution time, so that the state change of a Boolean switch signal can be instantaneously reflected on analog quantity output; according to the method, real zero-delay switching is achieved, meanwhile, program adjusting algorithms in any form are avoided, disturbance phenomena such as overshoot or undershoot are completely eradicated from the principle, and high stability and accuracy of output signals are ensured. Finally, according to the technology, the control instruction can be accurately and synchronously issued without delay, and the response speed and the synchronization precision of the whole control system in a high dynamic response industrial scene are remarkably improved.

Logic may generate or detect a communication as a punctured block of orthogonal frequency division multiplex (OFDM) symbols on a carrier with a channel bandwidth of 5 megahertz or less, the punctured block having a first set of highest frequency resource blocks (RBs) of the OFDM symbols punctured or having a second set of highest frequency RBs and lowest frequency RBs punctured. The punctured block may comprise a physical downlink control channel (PDCCH) block, a synchronization signal / physical broadcast channel (SS / PBCH) block, or a downlink bandwidth part (DL BWP) on a carrier with a channel bandwidth of 3 MHz, 5 MHz, or other channel bandwidth less than 5 MHz. And logic may cause transmission of or demodulate and decode the punctured block.

The invention provides a relay zero-crossing time-delay calibration circuit and electrical equipment. The relay zero-crossing time-delay calibration circuit comprises a sampling circuit, a comparison module, a logic circuit and an output interface used for an external control equipment port, the sampling circuit is respectively connected with a static contact and a movable contact of the relay and is used for sampling voltage values of the static contact and the movable contact of the relay, outputting the voltage value of the static contact through a first output end of the sampling circuit and outputting the voltage value of the movable contact through a second output end of the sampling circuit; the comparison module is respectively connected with the first output end and the second output end, and the output end is connected with the logic circuit; the comparison module is used for outputting an effective driving signal to the logic circuit under the condition that the static contact voltage value is equal to the movable contact voltage value; and the logic circuit is connected with the output interface and is used for pulling up or pulling down the potential of the output interface when the effective driving signal is received.

A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

The invention relates to the technical field of electric digital data processing, and discloses a data processing system for message management, which comprises a look-ahead buffer unit for maintaining a sliding window with variable window size parameters and pre-reading a message sequence; the mapping logic circuit is used for converting the resource identifier into a resource request mask; the state register is used for storing a global occupancy bitmap for representing resource occupancy; the scheduling controller is used for distributing messages according to bit operation results, counting bitmap setting quantity based on the population counting instruction to generate a resource saturation index, and then adjusting window size parameters in a negative feedback mode. The resource contention entropy value is directly sensed by utilizing a hardware instruction, nanosecond-level self-adaptive breathing control of a scheduling window is realized, and the service life of the scheduling window is prolonged. The problem of physical computing power collapse caused by bitmap scanning jitter in a high-concurrency scene is solved.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

The invention relates to the technical field of chips, and provides a power-on control method and system, a chip, equipment and a storage medium, and the method comprises the steps: controlling a first power domain to be powered on, maintaining a second power domain to be in a power-off state, and driving a signal processing circuit to process an external input signal and output a target signal, the first power domain supplies power to the signal processing circuit, and the second power domain supplies power to a post-stage logic circuit; after determining that the target signal is in a stable state, controlling the second power domain to be powered on so as to start the post-stage logic circuit; wherein the started post-stage logic circuit carries out sampling processing on the target signal in a stable state. According to the invention, power domain division is carried out on the signal processing circuit and the post-stage logic circuit and time-sharing power-on of the signal processing circuit and the post-stage logic circuit is controlled, so that stable and effective signals can be always sampled by the post-stage logic circuit when the post-stage logic circuit is started, and the power-on reliability of a chip and the stability of a system are improved.

The invention relates to a display device, a display system and a method thereof. A display device includes: a plurality of tiles arranged in an array on a printed circuit board (PCB), the PCB configured to electrically couple the plurality of tiles, each tile including: a lighting die including at least one lighting element; a semiconductor device includes a lighting die, a first region of the lighting die, and a tiled backplane die, the tiled backplane die including pixel logic circuitry and input / output logic circuitry, where the lighting die is coupled to a front surface of the tiled backplane die such that a first region of the backplane die is aligned with at least one lighting element in the lighting die; each respective tile is coupled to the printed circuit board through a plurality of openings in a back surface of a respective tiled backplane die, the plurality of openings in the back surface being aligned with a second region of the backplane die.

A memory device has a memory array including a memory segment to store weight data, a weight buffer coupled to the memory segment and configured to hold new weight data to be updated in the memory segment, a logic circuit, and a computation circuit coupled to an output of the logic circuit. The logic circuit further has a first input coupled to the memory segment by a bit line, and a second input configured to receive input data. The logic circuit is configured to generate, at the output, intermediate data corresponding to the input data and the weight data read from the memory segment through the bit line. The computation circuit is configured to, based on the intermediate data, generate output data corresponding to a computation performed on the input data and the weight data read from the at least one memory segment.

The utility model provides a CAN parallel operation head and tail terminal resistor automatic closing system which comprises a plurality of parallel operation machines and parallel operation lines, the parallel operation machines are sequentially connected through the parallel operation lines, and each parallel operation machine is provided with a terminal resistor, a switching circuit and a logic circuit. The switching circuit is connected to the terminal resistor and is used for controlling the on-off of the parallel machine and the terminal resistor; and the logic circuit is connected to the parallel machine and the switching circuit, and is used for judging whether the parallel machine is a head-tail machine or not and controlling the switching circuit to connect or disconnect the terminal resistor. According to the utility model, the logic circuit is arranged to judge whether the parallel machine is the head-tail machine, and the switching circuit is controlled to connect or disconnect the terminal resistor and the parallel machine, so that the closing of the terminal resistor of the head-tail machine and the opening of the terminal resistor of the intermediate machine are realized, the operation of manually increasing the terminal resistor is avoided, and the working efficiency is improved. And the risk of manual misoperation is reduced.

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.

Provided is a display driving circuit, including at least one processor configured to generate a first gamma code corresponding to a first mode among a plurality of modes, a gamma voltage generator configured to generate a plurality of gamma voltages with respect to the first mode, a data driver configured to generate data signal corresponding to the first gamma code based on the first gamma code and the plurality of gamma voltages, and generate a first level data corresponding to a minimum gamma voltage among the plurality of gamma voltages based on the data signal, and a gamma control logic circuit configured to generate a gamma voltage control signal for controlling the gamma voltage generator based on the first level data.

The invention discloses a neural tissue stimulator, characterized in that the neural tissue stimulator comprises a multiple of microneedles and a chip comprising at least one comparator with adaptive level, sequence control circuit, at least one capacitor stack built by n capacitors and 2n switches, at least one buffer capacitor outside the at least one capacitor stack, at least two additional switches outside the at least one capacitor stack, a CMOS-Logic, wherein further, the neural tissue stimulator comprises an interposer layer comprising holes for the multiple of microneedles and a lid. The neural tissue stimulator is characterized in, that the chip is located on one surface of the interposer layer and that the lid and the interposer layer form a capsule for the chip. Further, the neural tissue stimulator is adapted to be electrically self-sufficient.

Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to techniques and apparatus for signal amplification. One example apparatus generally includes: a current sensor configured to sense a current associated with an amplifier; and a voltage sensor configured to sense a voltage associated with the amplifier. The apparatus may also include a logic circuit configured to: detect a first over-current condition associated with the amplifier based on the current; detect a first over-voltage condition associated with the amplifier based on the voltage; and adjust an amplification gain to yield a first adjusted gain level for an input signal based on detection of the first over-current condition and the first over-voltage condition, wherein the amplifier is configured to amplify the input signal based on the first adjusted gain level.

The invention discloses a digital circuit dependency analysis method, which comprises the following steps of: by analyzing the equality of a Boolean differential circuit, converting a dependency judgment problem of D on S into a problem of judging whether the Boolean differential circuit is constantly 0 or not; when whether the Boolean differential circuit is constantly 0 cannot be judged through X value simulation, logic negation is performed on the Boolean differential circuit, so that a dependency judgment problem is formally converted into a satisfiability problem, SAT solving is performed on the problem, whether D depends on S or not is judged according to a solving result, and if not, the Boolean differential circuit is judged to be zero. If the Boolean differential circuit is constrained, the satisfiability problem of the Boolean differential circuit is reconstructed, and the constrained Boolean differential circuit is subjected to SAT solution to further determine the dependency. According to the method, the digital circuit dependency analysis efficiency and accuracy are remarkably improved, the method is suitable for combinational logic circuit scenes of any scale and any complexity, the application range and efficiency of engineering application are greatly improved, and the method has remarkable industrial application value and popularization prospects.

The invention relates to a fully homomorphic logic circuit encryption method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a hardware description language and encrypted data of a client; converting the hardware description language into a gate-level circuit netlist, mapping the gate-level circuit netlist into a lookup table network, performing operator matching on each lookup table node in the lookup table network according to a truth table corresponding to each lookup table node, and determining an operator of each lookup table node; traversing all the lookup table nodes, merging the lookup table nodes meeting a preset merging condition to obtain an optimized network topology, performing ciphertext format conversion on the encrypted data to obtain encrypted data in a target format, and using the optimized network topology to obtain the encrypted data in the target format. And based on the operator of each lookup table node, carrying out operation on the encrypted data in the target format to obtain an operation result. Therefore, the problems that an encryption computing framework is low in computing efficiency and difficult to meet diversified application requirements are solved, and the computing efficiency of a logic circuit can be improved.

The present disclosure provides a single-inductor multiple-output voltage converter, a power supply chip, and an electronic device, where the single-inductor multiple-output voltage converter comprises an energy generation circuit, an energy distribution circuit, a peak-inductor-current detection circuit, a zero-inductor-current detection circuit, and a control logic circuit. The aforementioned converter can provide multiple different output voltages using a single inductor without multiple operational amplifiers, thereby avoiding excessive bandwidth demand associated with multiple operational amplifiers, thus reducing power consumption.

The invention discloses a hybrid precision in-memory computing accelerator for low-illumination image enhancement, and relates to the technical field of integrated circuits. A top controller is used for global control and data scheduling; the SRAM read-write circuit is used for completing pre-loading and updating of weight data; the row / column decoder and the input buffer are used for realizing line-by-line input of activation data; the in-memory computing array comprises a plurality of SRAM (Static Random Access Memory) storage units and corresponding in-memory logic circuits, and is used for completing multiplication of weights and activated data; the peripheral accumulation circuit is used for receiving a calculation result of the in-memory calculation array, and completing multiplication and accumulation operation of convolution and a full connection layer through inter-row accumulation and channel fusion; and the ReLU activation module is used for realizing ReLU activation operation in the low-illumination image enhancement network. According to the in-memory computing accelerator, low-bit-width parallel and high-bit-width serial are adopted, so that the delay is halved, and the throughput rate is remarkably improved.

A scan driver including stages, at least one stage including a logic circuit configured to control a voltage of a first node and a voltage of a second node based on an input signal, a first clock signal, and a second clock signal in a progressive driving period, an output circuit configured to receive the first clock signal and a concurrent driving signal, and to output a scan signal in response to the voltage of the first node and the voltage of the second node, and a concurrent driving circuit configured to control the voltage of the first node and the voltage of the second node in response to an inverted concurrent driving signal in a concurrent driving period such that the output circuit is configured to output the concurrent driving signal as the scan signal in the concurrent driving period.

A power supply control device, which is a main controller of a switching power supply, includes an error amplifier, a ramp signal generation circuit, a comparison signal generation circuit, a logic circuit, a switch drive circuit, a reverse current detection circuit, and a ramp signal holding circuit. The logic circuit adjusts an input offset of the comparison signal generation circuit, the error signal, or the ramp signal in a direction that reduces a difference between the error signal and the ramp signal in response to a predetermined trigger signal.

An aerosol delivery device is provided that includes a segmented heater including a plurality of heating elements that are separately powerable to heat and thereby vaporize components of an aerosol precursor composition, and a control component for the segmented heater. The control component includes a logic circuit with a data input and a plurality of outputs each output of which is coupled to a respective one of the plurality of heating elements of the segmented heater. A processor produces and provides a logic signal including at least a high voltage level to the data input of the logic circuit and causes the logic circuit to provide the high voltage level at one or more outputs of the plurality of outputs of the logic circuit, and thereby powers respective one or more heating elements of the plurality of heating elements of the segmented heater to heat and thereby vaporize components of the aerosol precursor composition.

A storage device includes a memory device that includes a plurality of memory cells, and a memory controller that controls the memory device. The memory device includes a memory cell array that includes the plurality of memory cells, a control logic circuit that writes data to the memory cell array or reads data from the memory cell array in response to a command received from the memory controller, and a page buffer that stores sensing data sensed from the plurality of memory cells. The control logic circuit includes an error detecting circuit that detects an error of first data stored in first memory cells of the memory cell array, and the control logic circuit writes the first data to second memory cells of the memory cell array, based on an error comparison result obtained by comparing the error of the first data with a preset value.

The invention discloses a laser radar analog front-end circuit with strong environmental adaptability, and solves the problem that change noise is difficult to filter in a correlation detection method in the prior art. The circuit comprises a synchronous clock active quenching reset circuit which outputs SPAD pulse signals; the time window configuration circuit generates a window signal with adjustable pulse width; the analog domain intensity integral circuit outputs analog integral voltage changing along with the SPAD pulse number within the period of validity of the window signal; the sampling holding and inter-frame reset circuit samples as a reference voltage and resets the integral circuit after the window is ended; the correlation detection logic circuit compares the analog integral voltage with the reference voltage within the period of validity of the window signal, and outputs a trigger signal when the analog integral voltage exceeds the reference voltage; by integrating the light intensity in real time and adaptively updating the threshold value, only effective target echoes are triggered in a complex light environment, the resource overhead and power consumption are reduced, and the system environment adaptability and the ranging reliability are improved.

The invention discloses a pixel unit circuit for a dynamic vision sensor. The pixel unit circuit comprises a photodiode, an IV conversion circuit, a switched capacitor amplifier, a comparison circuit and a pixel readout logic circuit, the switched capacitor amplifier comprises a first capacitor, a second capacitor, an operational amplifier and a reset switch tube, the first capacitor is connected between the output end of the IV conversion circuit and the inverted input end of the operational amplifier, the in-phase input end of the operational amplifier is connected with a reference power supply, and the output end of the operational amplifier serves as the output end of the switched capacitor amplifier; the operational amplifier is connected with the comparison circuit, the second capacitor is connected between the inverted input end and the output end of the operational amplifier, the drain electrode and the source electrode of the reset switch tube are connected with the inverted input end and the output end of the operational amplifier respectively, and the substrate of the reset switch tube is connected with the output end of the switched capacitor amplifier; the comparison circuit is used for outputting event signals; and the pixel read-out logic circuit is used for reading out the event signal and is connected with the grid electrode of the reset switch tube.

The invention relates to the technical field of computer hardware, and provides a peripheral starting control method, circuit and device, a medium and a program product, and the method comprises the steps: monitoring a power state signal and a received external reset signal; when it is monitored that the power state signal is in a stable state, generating an internal reset control signal for indicating reset release; and controlling the internal hardware logic circuit to release the reset according to an internal reset control signal for indicating the release of the reset so as to trigger the internal hardware logic circuit to execute an initialization starting operation before the external reset signal is released from the reset. Before the external reset signal is released, the stable state of the power supply state signal is utilized to trigger the initialization starting of the internal hardware logic circuit in advance, so that the starting moment of the external internal core logic and the releasing moment of the external reset signal are decoupled; and sufficient time is reserved for the initialization operation which consumes long time by starting in advance, so that the peripheral starting reliability is improved.

An example assembly for detecting opening events of an item includes: a wireless communications tag. A memory of the wireless communications tag is configured to store an opening indicator. A piezoelectric element is configured to be disposed between two mating portions of a closing structure of the item. The piezoelectric element is loaded when the two portions are mated and unloaded when the two portions of the closing structure are unmated. The piezoelectric element is configured to output an electric signal that can be used by the wireless communications tag, e.g., to cause a logic circuit of the wireless communications tag to update the opening indicator when the piezoelectric element is unloaded.