1894 results about "Logic circuitry" patented technology

The present application belongs to the technical field of wireless communications and radar systems. Disclosed are a dual-band fusion and multiplexing frequency source, chips, a radio-frequency transceiver, a system, and a device. The system comprises: a full-function millimeter-wave CMOS 4+1 phased array chip, which is connected to an antenna end, and is used for realizing signal processing and frequency conversion between a millimeter-wave signal and a C-band intermediate-frequency signal, performing phase control and gain adjustment on the millimeter-wave signal, and providing an internal frequency source and a calibration function; a C-band front end, which is connected to the antenna end, and is used for receiving or transmitting a C-band signal; a C-band / intermediate-frequency transceiver multiplexing chip, which is used for performing frequency conversion between a C-band or intermediate-frequency signal and a baseband signal in a multiplexing manner, and performing signal processing and gain control on the C-band intermediate-frequency signal; a dual-band fusion and multiplexing frequency source, which is used for providing a local oscillator signal; and an all-digital control logic circuit, which is used for providing a control instruction. The present application improves the efficiency and performance of dual-band joint communications.

A network interface module for coupling a host device to a switched network as a network node is described. The network interface module comprises a single half-duplex port for communicatively coupling to a shared bus of the switched network, at least one frame queue sized to store one multicast read frame received via the shared bus, and logic circuitry. The logic circuitry is configured to decode a read command for the interface module included in a payload of the multicast read frame that includes multiple read commands for other network nodes of the switched network, and transmit a response frame including read data on the shared bus when detecting the shared bus is available for transmitting.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

A DC / DC converter includes a converter stage to receive an input voltage and to provide an output voltage from the input voltage in accordance with a modulated drive signal. The converter stage further provides a feedback voltage representing the output voltage. A controller circuit includes an error amplifier to receive the feedback voltage and a reference voltage and to provide an error signal based on the feedback voltage and the reference voltage. A PWM modulator receives a clock signal and the error signal and generates a modulated signal based on the clock signal and the error signal, and a logic circuit receives the modulated signal and generates the drive signal for the converter stage based on the modulated signal so that the drive signal has the same duty cycle as the modulated signal, when the duty cycle of the modulated signal is not smaller than a minimum duty cycle value.

A cascoded power switch includes a high-side (HS) switch between an output node and a first voltage supply terminal and a low-side switch. The HS switch includes a first, second, and third transistor in series between the first voltage supply terminal and the output node, and a fourth, fifth, and sixth transistor in series between the first voltage supply terminal and the output node. The first and fourth transistors are in parallel, the second and fifth transistors are in parallel, and the third and sixth transistors are in parallel. A HS driver circuit begins turning on the first transistor in response to assertion of a first control signal and delays turning on the fourth transistor until both the first and second controls signal are asserted. A voltage monitoring circuit includes logic which asserts the second control signal in response to a rise of an output voltage at the output node.

The invention relates to the technical field of software simulation operation simulation, and discloses a software logic simulation operation control method and system in an audio processor. The control method is applied to logic simulation operation control equipment and specifically comprises the following steps that S101, an audio processor simulation operation request sent by a user side is received, a graphical user interface is generated according to the operation request, and the graphical user interface comprises a logic module list area, a design editing area, an attribute bar and an information display area; and the user side drags an icon of a logic circuit element from the logic module list area to the design editing area. Through a highly integrated graphical interface and intelligent interactive design, the design and simulation efficiency of an audio processor logic circuit is remarkably improved, and by adopting a'drag-and-generate 'module instantiation mechanism, an attribute bidirectional real-time synchronization technology and visual connection and signal type inspection, the reliability of the audio processor logic circuit is greatly improved. Therefore, the user can intuitively and quickly construct the complex circuit topology, and the professional threshold is greatly reduced.

An integrated circuit includes logic circuits and a network-on-chip in a region of the integrated circuit. The network-on-chip is configurable to transmit at least two of user data, configuration data, and emulation data to the logic circuits. The network-on-chip is configurable to transmit the user data to and from the logic circuits during a user mode of the integrated circuit. The network-on-chip is configurable to transmit the configuration data to the logic circuits for configuring the logic circuits during a configuration mode of the integrated circuit. The network-on-chip is configurable to transmit the emulation data to and from the logic circuits during an emulation mode of the integrated circuit.

A high-speed transmitter system using a common mode controlled serialization stage embedded in an output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using NMOS transistors. In addition, the logic circuit is configured to be a desired voltage value (e.g., the output circuit's common mode) such that a switching point of the NMOS gm stage can be decreased and the gm stage can be activated within a reduced time.

An apparatus includes a phase-locked loop (PLL) circuit and a logic circuit. The logic circuit may manage, via one or more programmable operating parameters of the PLL circuit, PLL bandwidth variation exhibited by the PLL circuit due to variations in its manufacturing process (P), supply voltage (V) or temperature (T), i.e., PVT variations exhibited by the PLL circuit.

The invention relates to an analog quantity selection method and system based on a Boolean switch, in particular to the field of industrial automation, and aims to directly realize signal mapping by adopting a pure hardware combinational logic circuit and thoroughly eliminate instruction execution time, so that the state change of a Boolean switch signal can be instantaneously reflected on analog quantity output; according to the method, real zero-delay switching is achieved, meanwhile, program adjusting algorithms in any form are avoided, disturbance phenomena such as overshoot or undershoot are completely eradicated from the principle, and high stability and accuracy of output signals are ensured. Finally, according to the technology, the control instruction can be accurately and synchronously issued without delay, and the response speed and the synchronization precision of the whole control system in a high dynamic response industrial scene are remarkably improved.

A high-speed transmitter system using a supply controlled serialization stage embedded in a PMOS output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using PMOS transistors. In addition, the logic circuit is connected to a low voltage supply such that its output can be adjusted to be close to a switching point of the PMOS based gm stage to speed up transmitter operations.

Logic may generate or detect a communication as a punctured block of orthogonal frequency division multiplex (OFDM) symbols on a carrier with a channel bandwidth of 5 megahertz or less, the punctured block having a first set of highest frequency resource blocks (RBs) of the OFDM symbols punctured or having a second set of highest frequency RBs and lowest frequency RBs punctured. The punctured block may comprise a physical downlink control channel (PDCCH) block, a synchronization signal / physical broadcast channel (SS / PBCH) block, or a downlink bandwidth part (DL BWP) on a carrier with a channel bandwidth of 3 MHz, 5 MHz, or other channel bandwidth less than 5 MHz. And logic may cause transmission of or demodulate and decode the punctured block.

A system may include a signal replica transmitter configured to generate a replica signal based on a first signal, and an echo canceller configured to remove crosstalk from a second signal. The echo canceller may include a first current mode logic (CML) circuit configured to receive a first set of input signals, and a second CML circuit configured to receive a second set of input signals, wherein a first output from the first CML circuit and a second output from the second CML circuit may be combined to remove the crosstalk from the second signal and generate an output signal from the echo canceller.

A control system and a method for controlling a direct current (DC) link voltage of a hybrid energy storage system (HESS) includes a fractional-order proportional integral (FOPI) controller receives a voltage difference between the DC link voltage and a predetermined reference voltage and generate a reference charging current based on the voltage difference, a hysteresis controller receives a current difference between the reference charging current and a charging current of the HESS and generate a control signal based on the current difference, and a logic circuit receives the control signal and manage charging and discharging procedures of the HESS based on the control signal, so that the DC link voltage of the HESS is constant at the predetermined reference voltage, where the FOPI controller has parameters based on a metaheuristic technique.

The invention provides a relay zero-crossing time-delay calibration circuit and electrical equipment. The relay zero-crossing time-delay calibration circuit comprises a sampling circuit, a comparison module, a logic circuit and an output interface used for an external control equipment port, the sampling circuit is respectively connected with a static contact and a movable contact of the relay and is used for sampling voltage values of the static contact and the movable contact of the relay, outputting the voltage value of the static contact through a first output end of the sampling circuit and outputting the voltage value of the movable contact through a second output end of the sampling circuit; the comparison module is respectively connected with the first output end and the second output end, and the output end is connected with the logic circuit; the comparison module is used for outputting an effective driving signal to the logic circuit under the condition that the static contact voltage value is equal to the movable contact voltage value; and the logic circuit is connected with the output interface and is used for pulling up or pulling down the potential of the output interface when the effective driving signal is received.

A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

The invention relates to the technical field of electric digital data processing, and discloses a data processing system for message management, which comprises a look-ahead buffer unit for maintaining a sliding window with variable window size parameters and pre-reading a message sequence; the mapping logic circuit is used for converting the resource identifier into a resource request mask; the state register is used for storing a global occupancy bitmap for representing resource occupancy; the scheduling controller is used for distributing messages according to bit operation results, counting bitmap setting quantity based on the population counting instruction to generate a resource saturation index, and then adjusting window size parameters in a negative feedback mode. The resource contention entropy value is directly sensed by utilizing a hardware instruction, nanosecond-level self-adaptive breathing control of a scheduling window is realized, and the service life of the scheduling window is prolonged. The problem of physical computing power collapse caused by bitmap scanning jitter in a high-concurrency scene is solved.

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

The invention discloses a museum cultural relic environment monitoring method and system based on a fusion technology. The method comprises the following steps: monitoring a cultural relic circuit in real time by using a graph convolutional neural network, extracting node features to construct a logic circuit directed graph, determining fault nodes, and obtaining a fault diagnosis result; obtaining fixed reference objects and environment perception data in the museum to form environment information, inputting the environment information into a multi-reference object system analysis model, and analyzing the influence of environment factors on fault nodes to obtain an environment analysis result; combining the two results to position a cultural relic associated equipment power device which needs to be optimized emphatically; carrying out refined segmentation, simulation and optimization adjustment on the devices by utilizing a simulation technology, and generating a targeted power regulation and control strategy; and outputting the strategy so as to carry out environment adjustment and equipment maintenance treatment according to the strategy. By implementing the method provided by the invention, collaborative linkage of cultural relic state monitoring, environmental risk assessment and equipment power regulation and control can be realized, and comprehensive guarantee is provided for safety of cultural relics in a museum.

The invention relates to the technical field of chips, and provides a power-on control method and system, a chip, equipment and a storage medium, and the method comprises the steps: controlling a first power domain to be powered on, maintaining a second power domain to be in a power-off state, and driving a signal processing circuit to process an external input signal and output a target signal, the first power domain supplies power to the signal processing circuit, and the second power domain supplies power to a post-stage logic circuit; after determining that the target signal is in a stable state, controlling the second power domain to be powered on so as to start the post-stage logic circuit; wherein the started post-stage logic circuit carries out sampling processing on the target signal in a stable state. According to the invention, power domain division is carried out on the signal processing circuit and the post-stage logic circuit and time-sharing power-on of the signal processing circuit and the post-stage logic circuit is controlled, so that stable and effective signals can be always sampled by the post-stage logic circuit when the post-stage logic circuit is started, and the power-on reliability of a chip and the stability of a system are improved.

The invention relates to a display device, a display system and a method thereof. A display device includes: a plurality of tiles arranged in an array on a printed circuit board (PCB), the PCB configured to electrically couple the plurality of tiles, each tile including: a lighting die including at least one lighting element; a semiconductor device includes a lighting die, a first region of the lighting die, and a tiled backplane die, the tiled backplane die including pixel logic circuitry and input / output logic circuitry, where the lighting die is coupled to a front surface of the tiled backplane die such that a first region of the backplane die is aligned with at least one lighting element in the lighting die; each respective tile is coupled to the printed circuit board through a plurality of openings in a back surface of a respective tiled backplane die, the plurality of openings in the back surface being aligned with a second region of the backplane die.

An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The digital discriminator may sample the status signal of the phase detector. The logic circuit may determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.

A memory device has a memory array including a memory segment to store weight data, a weight buffer coupled to the memory segment and configured to hold new weight data to be updated in the memory segment, a logic circuit, and a computation circuit coupled to an output of the logic circuit. The logic circuit further has a first input coupled to the memory segment by a bit line, and a second input configured to receive input data. The logic circuit is configured to generate, at the output, intermediate data corresponding to the input data and the weight data read from the memory segment through the bit line. The computation circuit is configured to, based on the intermediate data, generate output data corresponding to a computation performed on the input data and the weight data read from the at least one memory segment.

The utility model provides a CAN parallel operation head and tail terminal resistor automatic closing system which comprises a plurality of parallel operation machines and parallel operation lines, the parallel operation machines are sequentially connected through the parallel operation lines, and each parallel operation machine is provided with a terminal resistor, a switching circuit and a logic circuit. The switching circuit is connected to the terminal resistor and is used for controlling the on-off of the parallel machine and the terminal resistor; and the logic circuit is connected to the parallel machine and the switching circuit, and is used for judging whether the parallel machine is a head-tail machine or not and controlling the switching circuit to connect or disconnect the terminal resistor. According to the utility model, the logic circuit is arranged to judge whether the parallel machine is the head-tail machine, and the switching circuit is controlled to connect or disconnect the terminal resistor and the parallel machine, so that the closing of the terminal resistor of the head-tail machine and the opening of the terminal resistor of the intermediate machine are realized, the operation of manually increasing the terminal resistor is avoided, and the working efficiency is improved. And the risk of manual misoperation is reduced.

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.

Provided is a display driving circuit, including at least one processor configured to generate a first gamma code corresponding to a first mode among a plurality of modes, a gamma voltage generator configured to generate a plurality of gamma voltages with respect to the first mode, a data driver configured to generate data signal corresponding to the first gamma code based on the first gamma code and the plurality of gamma voltages, and generate a first level data corresponding to a minimum gamma voltage among the plurality of gamma voltages based on the data signal, and a gamma control logic circuit configured to generate a gamma voltage control signal for controlling the gamma voltage generator based on the first level data.

Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.