397 results about "Leakage power" patented technology

A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path. Finally, the addition of multiple threshold voltage gates allows for increased performance while limiting leakage power.

Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration memory cells, and so forth. Embodiments describe circuits and methods for implementing multiple supplies as sources of V_dd, multiple voltage thresholding V_t, signal level translators, and power gating of circuitry to deactivate portions of the circuit which are inactive. The supply voltage levels can be fixed, or programmable. Methods are described for performing circuit CAD in the routing and assignment process on FPGAs, in particular for optimizing FPGA use having the power reduction circuits taught. Routing methods describe utilizing slack timing, power sensitivity, trace-based simulations, and other techniques to optimize circuit utilization on a multi V_dd FPGA.

A method for determining full chip leakage power first estimates leakage power and dynamic power for each circuit macro. The power supply voltage to each macro is first assumed to be nominal. The power dissipation for each macro is modeled as a current source whose value is the estimated power divided by the nominal power supply voltage. The power distribution network is modeled as a resistive grids. The thermal environment of the IC and its electronic package are modeled as multi dimensional grids of thermal elements. Algebraic multi-grid (AMG) methods are used to calculate updated circuit macro voltages and temperatures. The macro voltages and temperatures are updated and updated leakage and dynamic power dissipation are calculated. Iterations are continued until leakage power converges to a final value.

The invention relates to a leakage source detecting device based on infrared thermal imaging processing, and the leakage source detecting device comprises an infrared thermal imaging camera and a microprocessor, wherein the microprocessor is used for analyzing, processing and judging damage conditions, leakage points, leakage zones and leakage degrees of walls of buildings or containers according to the thermal images, shot by infrared thermal imaging camera, of the walls or containers and relative input information, and the infrared thermal imaging camera is used for scanning a preprocessed detected object so as to obtain the temperature distribution information of the surfaces of the walls or the containers. The software of the microprocessor mainly comprises an infrared thermal imaging acquiring unit, an infrared thermal imaging preprocessing unit and a leakage quantitative detecting unit, and the software of the microprocessor analyzes the temperature field to the object to be detected through a digital image processing technology to judge whether the object to be detected has the defect of leakage or not. The leakage source detecting device provided by the invention can be used for not only rapidly detecting the existing of the leakage defect, but can also accurately detecting the leakage zone and degree and the influence scope. The leakage source detecting device provided by the invention provides an assessment method for leakage defects.

A system and method to reduce leakage power while minimizing performance penalties and noise is disclosed. In accordance with one embodiment of the invention, the system includes at least one sleep transistor operatively coupleable between a system power supply and at least one circuit powered by the system power supply to control the application of power to the circuit. The sleep transistor is also operatively coupleable to receive a sleep control signal to turn the sleep transistor on and off. A body bias voltage generator is operatively coupleable to a body of the at least one sleep transistor to substantially reduce leakage current when the sleep transistor is non-operational or idle and to improve the operational characteristics of the sleep transistor when the transistor is operational by reducing the performance penalty of the sleep transistor and by reducing impact of noise on the circuit and other devices.

A Static Random Access Memory (SRAM) cell having high stability and low leakage is provided. The SRAM cell includes a pair of cross-coupled inverters providing differential storage of a data bit. Power to the SRAM cell is provided by a read word line (RWL) signal, which is also referred to herein as a read control signal. During read operations, the RWL signal is pulled to a voltage level that forces the SRAM cell to a full-voltage state. During standby, the RWL signal is pulled to a voltage level that forces the SRAM cell to a voltage collapsed state in order to reduce leakage current, or leakage power, of the SRAM cell. A read-transistor providing access to the bit stored by the SRAM cell is coupled to the SRAM cell via a gate of the read transistor, thereby decoupling the stability of the SRAM cell from the read operation.

Behavior of an electrical circuit can be modeled using a trained neural network. For example, using one or more neural networks, power consumption, including leakage power and switching energy, can be estimated. Also, a profile of current versus time can be generated for the electrical circuit. A hierarchy of neural networks may be used to model the circuit at different levels. In one embodiment, a circuit behavior is modeled using one or more neural networks, cluster values, and cluster probabilities.

Methods and apparatus are provided for detecting a non-intended object of power reception by a power transmitter. Power transmission for communication is performed, when the load change is sensed that has a value greater than or equal to a predetermined threshold. It is determined whether a subscription request, for subscribing to a network is received within a predetermined time period. The power transmission for communication is stopped when the subscription request is not received within the predetermined time period. Power is transmitted to a power receiver that has transmitted the subscription request, when the subscription request is received within the predetermined time period. It is determined whether a leakage power value exceeds an allowable range, when the power state report is received from the power receiver. The transmission of the power to the power receiver is stopped, when the leakage power value exceeds the allowable range.

Various embodiments of methods and systems for dynamically adjusting a peak dynamic power threshold are disclosed. Advantageously, embodiments of the solution for peak dynamic power management optimize a peak dynamic power threshold based on estimations of real-time leakage current levels and/or actual power supply levels to a power domain of a system on a chip (“SoC”). In this way, embodiments of the solution ensure that a maximum amount of available power supply is allocated to dynamic power consumption for processing workloads at an optimum performance or quality of service (“QoS”) level without risking that the total power consumption (leakage power consumption+dynamic power consumption) for the power domain exceeds the power supply capacity.

A method and system for integrated circuit optimization to improve performance and to reduce leakage power consumption of an integrated circuit (IC). The original IC includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. The method creates an optimized standard-cell library from a standard-cell library. The standard-cell library includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. Further, an optimized IC is generated by using the optimized standard-cell library from the original IC. The optimized IC has an improved performance and reduced leakage power characteristics, as compared to the original IC.

In a distortion compensation device which uses distortion compensation coefficients to subject distortion compensation processing to an input signal and supply the result of the distortion compensation processing to a distorting device, calculates the distortion compensation coefficients based on the input signal before distortion compensation and the feedback signal fed back from the output side of the distorting device, and stores the calculated distortion compensation coefficients in association with the input signal, (1) the feedback signal is AD-converted; (2) the AD-converted output is subjected to fast Fourier transform (FFT) processing; (3) the FFT calculation result is used to calculate the value of either the signal-to-noise ratio SNR, or the adjacent channel leakage power ratio ACLR, or the noise level; (4) the delay time occurring in the distorting device and feedback loop is adjusted such that the difference between the above calculated value at the current time and the above calculated value at the immediately preceding time is either zero, or is equal to or less than a threshold value; and, (5) this adjustment processing is repeated to determine the accurate delay time, and based on this delay time the timing of each of the portions of the distortion compensation device is adjusted.

The present invention relates to integrated circuit with reduced leakage power and in particular to a methodology for retaining an operational state of at least a part of the integrated circuit while the part is in standby/low power mode. In detail, the inventive methodology is based on the use of scan chains being implemented in the integrated circuit for production testing purposes. Via the scan chains circuit-internal state-variable memory element content is read out and/or written in such that the operational state of for instance a specific part (power domain) of the integrated circuit may be captured on the basis of the circuit internal contents, retained in an adequately provided data storage and afterwards scanned into the specific part of the integrated circuit to restore the operational state thereof.

The invention relates to a stray energy power supplying method of an electrical equipment status monitoring wireless sensing system; a vibration power-generating device, or a temperature difference power-generating device or a flux leakage power-generating deice is adopted to lead mechanical vibration energy or heat energy or flux leakage energy which is generated in the operating process of the electrical equipment to be converted into electrical energy, and the electrical energy is transformed and adjusted by a transformation module, and the transformed electrical energy is stored in an energy storage device such as a rechargeable battery, a capacitor and the like, so as to supply power for the node of the electrical equipment status monitoring wireless sensor. A device applied to the stray energy power supplying method comprises a stray energy power-generating module such as vibration power generation, temperature difference power generation or flux leakage power generation, an electrical energy conversion module and an electrical energy storage module which are arranged on the electrical equipment. The invention can effectively utilize stray energy generated in the operating process of the electrical equipment to supply power for the node of the wireless sensor.

The invention provides a peak clipping system for pretreating discontinuous arrangement multicarrier and a method thereof. The system includes a figure up-conversion device having multilevel interpolation filter and a peak clipping device, wherein the peak clipping device is arranged between arbitrary two-stage interpolation filter. The method includes carrying through the medium frequency process on the baseband carrier, and processing peak clipping between arbitrary two stages with multilevel interpolation. The project of the invention realizes the single peak clipping on each baseband carrier, thereby the carrier frequency point can be arranged arbitrarily in a certain frequency range when mixing; the peak clipping device is in the middle of the up-conversion channel, with low data rate, wide signal bandwidth, easy design, which can preferably restrain the noise out of the signal range and ensure the near channel leakage power ration of the transmitter without great change.

An integrated circuit (IC) including unit power control, leakage reduction circuit for controllably reducing leakage power with reduced LdI/dt noise in the IC and, an activity prediction unit invoking active/dormant states in IC units. The prediction unit determines turn on and turn off times for each IC unit. The prediction unit controls a supply voltage select circuit selectively passing a supply voltage to a separate supply line at the predicted turn on time and selectively blocking the supply voltage at the predicted turn off time.

A leakage power recovery system and method, and a electronic design automation (EDA) tool incorporating either or both of the system and the method. In one embodiment, the timing signoff tool includes: (1) a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, the initial power recovery process including making first conditional replacements of cells in at least one path in a circuit design with lower leakage cells and estimating a delay and a slack of the at least one path based on the first conditional replacements and (2) a speed recovery module associated with the power recovery module and configured to carry out a speed recovery process in each of the multiple scenarios concurrently, the speed recovery process including determining whether the first conditional replacements cause a timing violation with respect to the at least one path and making second conditional replacements with higher leakage cells until the timing violation is removed.

An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V_SC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.