40 results about "Leakage power" patented technology

The invention, which belongs to the technical field of the plasma amplitude limiter, discloses a high-power ultra-wideband plasma amplitude limiter comprising an input window, a discharge gap, an output window and an amplitude limiting module. The plasma amplitude limiter is reliable in structure, ultra-wide in band and high in power capacity, is located at the front end of a receiver, and plays a role in protecting high-power microwave attacks. The plasma amplitude limiter disclosed by the invention can bear high-power microwave attack with the highest power magnitude of 10kW in the widest frequency band range of 10GHz, and a receiving access can be quickly switched off within 10ns, so that the aim of protecting the whole communication system is fulfilled; a coaxial ultra-wideband design technology is adopted, a full-hard welding structure is adopted, the structure is stable and reliable, and the frequency band range of the plasma amplitude limiter tube covers L, S, C, X and Ku wave bands; the multi-stage pointed-cone-shaped discharge gaps are adopted, leakage power is reduced stage by stage, and therefore safe work of the amplitude limiting chip is guaranteed, and finally the plasma amplitude limiter with high bearing power and short response time is achieved.

The purpose of the present invention is to provide a display device and an electronic apparatus that make it possible to suppress leakage power, for example.　Provided is a display device having a plurality of circuit blocks that operate at the time of display operation, the plurality of circuit blocks having a first circuit block for which a power supply is controlled to be off at the time of standby. The display device includes, for example, a switch provided between a power supply line of the power supply and the first circuit block, and a control unit for controlling the switch to be off when the standby state and the operation of the first circuit block are unnecessary.

The invention provides a serialized memory access and computing collaboration method, system, equipment and medium, which parses the same external command in parallel through two command parsers with the same structure to collaboratively generate address information for memory access and an operation instruction for computing control, and the address information and the operation instruction are complementary in function and synchronous in time sequence. Compared with a traditional scheme depending on an OST buffer and matched control logic thereof, the architecture does not need to additionally cache control information or an intermediate state, so that the OST buffer and related read-write logic are effectively omitted, and the chip area overhead of the AI accelerator is remarkably reduced; meanwhile, dynamic read-write power consumption and static leakage power consumption are eliminated, and the energy efficiency ratio of the system is remarkably increased. Besides, the triggering of the memory access operation does not depend on the capacity of a buffer area, so that the number of memory accesses supported by a single task is not limited by the scale of the OST any more, and the flexibility and the parallel capability of task processing are greatly enhanced.

Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static / leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

The present invention provides a method for quickly calculating adjacent channel interference, which includes the following steps: Step 1, determine the adjacent channel interference situation according to the bandwidth overlap between the interfering system and the interfered system; Step 2, discretize the effective range of adjacent channel interference to obtain a discretized value data table; Step 3, based on the method of discrete dimensionality reduction, calculate the adjacent channel leakage power ratio (ACLR) and the adjacent channel rejection ratio (ACRR) for the adjacent channel interference situation; Step 4, calculate the effective power of adjacent channel interference according to the ACLR and the ACRR. This method analyzes 7 situations where there is adjacent channel interference between stations, and respectively designs simple algorithms by using the method of discrete dimensionality reduction, significantly reducing the calculation complexity of adjacent channel interference. It is particularly suitable for terminals with limited computing resources such as small portable computers and tablet computers, and can meet the needs of interference coexistence analysis for complex electromagnetic environments or large-scale networks on small computing terminals.

The invention provides a memory operation method, a memory, a display and a computer program product. The memory comprises a plurality of memory units, a power adjusting unit and a control unit, the method comprises the following steps: determining the working state of the storage unit by the control unit; the control unit generates a power adjusting signal according to the working state and sends the power adjusting signal to the power adjusting unit; and adjusting the input power corresponding to the storage unit by the power adjusting unit in response to the power adjusting signal. According to the method, the corresponding power adjusting unit is controlled to adjust the power of the corresponding storage unit according to the working state of each storage unit, so that the electric leakage power consumption of the storage unit is reduced, and finally the power consumption of the operation of the memory is reduced.

Systems and techniques are provided for processing video data. A process can include obtaining a frame of video data associated with a plurality of Largest Coding Unit (LCU) rows and a plurality of LCU columns, and processing the frame of video data using a plurality of parallel processing pipelines, wherein each pipeline of the plurality of parallel processing pipelines is configured to process a corresponding subset of LCU rows of the plurality of LCU rows. An interrupt signal can be received from a particular pipeline of the plurality of parallel processing pipelines, indicating the particular pipeline has completed processing of a respective last LCU of the corresponding subset of LCU rows. A shut down of the particular pipeline can be caused based on receipt of the interrupt signal from the particular pipeline, wherein the shut down deactivates the particular pipeline.

The invention discloses a method for realizing time sequence and electric leakage power consumption coordinated optimization through critical path customization, and belongs to the field of signal processing. Extracting a key path which does not meet the time sequence constraint in the circuit; customizing the extracted critical path by selecting a low-threshold voltage and large-size transistor process library; and carrying out comprehensive simulation on the customized key path and other parts to confirm whether the time sequence constraint is met, and if not, repeating the previous step again. The low-threshold-voltage and large-size transistors are only adopted for critical paths, and the standard-threshold-voltage and standard-size transistors are adopted for other parts of the circuit, so that the number of the transistors with large electric leakage is reduced while the time sequence requirement is ensured, and the electric leakage power consumption is further reduced.

A network node, such as a gNB, determines an adjacent channel leakage power ratio (ACLR) requirement relaxation for a UE and transmits, to the UE, first information of the ACLR requirement relaxation

Various embodiments provide for grouping cells in a cell library based on iterative clustering, which can be used for pruning the cell library. In particular, various embodiments provide for grouping cells in a cell library based on iterative clustering in view of a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for grouping cells in a cell library based on iterative clustering in view of leakage power and then applying cell library pruning to optimize for cell leakage power.

An electric leakage protection circuit breaker comprises an electric leakage protection electrode and at least one circuit breaker electrode which are arranged side by side, the electric leakage protection electrode comprises a zero sequence current transformer, an electronic assembly board and an electric leakage release, and the electric leakage protection electrode is provided with an electric leakage power supply contact composed of a movable contact piece and a static contact piece. The driving piece is used for driving the movable contact piece to be in contact with or separated from the static contact piece, an electric leakage power supply contact formed by the movable contact piece and the static contact piece is connected in series in a power supply loop for supplying power to the electronic component board and / or the electric leakage tripper, and the driving piece is linked with a handle of the circuit breaker pole. When the main loop of the circuit breaker pole is disconnected, the driving piece is driven by the handle to drive the movable contact piece to be in contact with the static contact piece, and when the main loop of the circuit breaker pole is disconnected, the driving piece is driven by the handle to drive the movable contact piece to be separated from the static contact piece. And the leakage trip coil and the electronic component board are not burnt.

The present application relates to the technical field of photovoltaics. Disclosed are a solar cell and a photovoltaic module. By rationally setting a ratio relationship between a transmission resistance heating power (P1) corresponding to all conductive semiconductor portions included in the solar cell and a reverse electric-leakage power (P2) corresponding to the solar cell, a reverse breakdown voltage and a hot spot risk of the solar cell are effectively reduced. Each conductive semiconductor portion in the solar cell is at least partially located between a first doped semiconductor portion and a second doped semiconductor portion, and only part of the first doped semiconductor portion is electrically connected to part of the second doped semiconductor portion by means of at least one conductive semiconductor portion. The conductivity type of different regions of each conductive semiconductor portion in the lengthwise direction thereof is opposite to the conductivity type of one of the first doped semiconductor portion and the second doped semiconductor portion. The ratio A of P1 to P2 is greater than or equal to 2%, but less than or equal to 50%.

Described is a frequency selective limiter (FSL) module comprising a cascade of an FSL and a functional limiter (e.g. a conventional semiconductor limiter comprising a PIN diode) with steady state limiting and power threshold values selected such the FSL module provides suppression of a spike leakage power and while still enabling frequency selective limiting.

The invention relates to the technical field of latches, and discloses a high-performance low-overhead four-point reinforced latch based on dual modular redundancy, which comprises an input module, a storage module L1 and a storage module L2, the storage module L1 and the storage module L2 are connected with the input module, and the storage module L1 and the storage module L2 are connected with an output module; and the input module comprises a transmission gate TG1-a transmission gate TG10 which are connected with the storage module L1 and the storage module L2. According to the method, internal four-node overturning can be completely tolerated, and meanwhile, the method has a relatively high four-node overturning self-recovery rate and relatively high reinforcing performance and reliability; a double-input C unit stacking structure is adopted, the leakage power consumption is greatly reduced, and the clock control double-input C unit is utilized, so that the dynamic power consumption is reduced; only one transmission gate is arranged from the input end to the output end in a transparent mode, so that the latch has low time delay and can be widely applied to the fields of aerospace and the like with high requirements on reliability and low power consumption of the latch.

The present application relates to a leakage power consumption optimization method and device of a chip. The method comprises: finding a timing logic device whose threshold voltage is lower than a predetermined threshold voltage in a circuit to form an initial device set; determining a first feature and a second feature of the timing logic device, the first feature comprising a timing margin of the timing logic device, and the second feature comprising a judgment result of whether there exists a replaceable target timing logic device corresponding to the timing logic device in a device library, the target timing logic device having a same function type as the timing logic device and a threshold voltage higher than that of the timing logic device; selecting a replaceable timing logic device from the initial device set according to the first feature, the second feature and a leakage power consumption optimization strategy parameter; and replacing the replaceable timing logic device in the target circuit with the target timing logic device. The method effectively reduces the leakage power consumption of the chip and improves the energy efficiency ratio of the chip under the premise of ensuring the timing performance of the circuit.

Systems and techniques are provided for processing video data. A process can include obtaining a frame of video data associated with a plurality of Largest Coding Unit (LCU) rows and a plurality of LCU columns, and processing the frame of video data using a plurality of parallel processing pipelines, wherein each pipeline of the plurality of parallel processing pipelines is configured to process a corresponding subset of LCU rows of the plurality of LCU rows. An interrupt signal can be received from a particular pipeline of the plurality of parallel processing pipelines, indicating the particular pipeline has completed processing of a respective last LCU of the corresponding subset of LCU rows. A shut down of the particular pipeline can be caused based on receipt of the interrupt signal from the particular pipeline, wherein the shut down deactivates the particular pipeline.

The present invention discloses an Internet of Things leakage circuit breaker with a leakage power loss function and a method, which relates to the field of power equipment; an Internet of Things leakage circuit breaker with a leakage power loss function includes a control module, a leakage acquisition module, a leakage power loss module and a tripping module; the present invention realizes the remote precise control of the leakage function by means of a processor controlling a multi-way switch, improves the intelligent level and practicality of the Internet of Things leakage circuit breaker, and better meets the development needs of the new power system.

The utility model relates to the field of power junction box discloses an anti -electricity leakage power junction box, including the bottom plate, the inside of bottom plate is provided with the bolt hole, the inside installation of bolt hole has first hexagonal bolt, the upper surface fixed connection of bottom plate has junction box shell, the inside installation of junction box shell has the threaded rod, the outside screw thread connection of threaded rod has the nut, the inside installation of nut has second hexagonal bolt, the outside screw thread connection of threaded rod has the nut, the inside fixed connection of junction box shell has fixed establishment, fixed establishment includes fixed plate, the inside fixed connection of fixed establishment in junction box shell. In the utility model, through putting the power cord into the convex guide plate, the power cord is extruded to the convex guide plate, first spring and second spring produce the reaction force and extrude the convex guide plate at this moment, have realized the arrangement of power cord to make the power cord in junction box shell place neat.

Aspects of the subject disclosure address the traditional trade-off between performance and area, in relation to circuit and system design, together with power as an additional factor of consideration. Circuits and systems of this disclosure may realize a datapath of data in respect of memory state elements (e.g., registers, flops, etc.) that is dependent on multiple qualifiers. Aspects of this disclosure enhance (e.g., optimize) area and reduce leakage power associated with circuits and systems. Furthermore, aspects of this disclosure enable and enhance an insertion of clock-gating circuits or mechanisms to reduce dynamic-power consumption depending on states of the qualifiers.

The purpose of the present invention is to provide a display device and an electronic apparatus that make it possible to suppress leakage power, for example.　Provided is a display device having a plurality of circuit blocks that operate at the time of display operation, the plurality of circuit blocks having a first circuit block for which a power supply is controlled to be off at the time of standby. The display device includes, for example, a switch provided between a power supply line of the power supply and the first circuit block, and a control unit for controlling the switch to be off when the standby state and the operation of the first circuit block are unnecessary.

An electric leakage protection circuit breaker comprises an electric leakage protection electrode and at least one circuit breaker electrode which are arranged side by side, and the electric leakage protection electrode comprises a zero sequence current transformer, an electronic assembly board, an electric leakage tripper, an indicating mechanism and an electric leakage power supply contact piece set composed of a movable contact piece and a static contact piece. An electric leakage power supply contact piece group formed by the movable contact piece and the static contact piece is connected in series in a power supply loop for supplying power to the electronic component board and / or the electric leakage release; the circuit breaker pole comprises a handle, an operating mechanism, a moving contact and a static contact, the moving contact is connected with the operating mechanism, the indicating button drives the contact piece to make contact with the static contact piece when located at the first indicating position, and the electric leakage tripping iron core acts to trigger the operating mechanism of the circuit breaker pole to trip during electric leakage. Meanwhile, the electric leakage tripping iron core drives the indication button to be switched from the first indication position to the second indication position, when the indication button moves to the second indication position, the movable contact piece and the static contact piece are separated, and the electric leakage tripping device and the electronic assembly board can be prevented from being burnt out.

The present invention provides a method, a system, a computer device and a storage medium for testing the power consumption of a dual-cell terminal, which relates to the technical field of power consumption testing. The method includes: a test platform generates a test plan and generates a number of test instructions according to the test plan and sends them to a tester. One of the test instructions is used to indicate the testing of the leakage power consumption of the dual-cell terminal under test, and the remaining test instructions are used to indicate the testing of the operating power consumption of the dual-cell terminal under test; the tester respectively tests the leakage power consumption value and the operating power consumption value of the dual-cell terminal under test based on each test instruction, and feeds back the test results to the test platform; the test platform obtains the final power consumption value of the dual-cell terminal under test based on the operating power consumption value and the leakage power consumption value of the dual-cell terminal under test in the test results. The technical solution provided by the present invention fully considers the influence of the leakage current on the power consumption value of the dual-cell terminal, and can more accurately determine the actual power consumption of the dual-cell mobile terminal.

Amplifier circuit (300; 400) having the following features: a power amplifier (110) configured to amplify an RF input signal (105) based on a supply voltage to obtain an RF output signal (115); and an operating point controller (320; 420) configured to control an operating point of the power amplifier (110), wherein the operating point control (320; 420) has the following features: an impedance determination device (322; 422) configured to determine a measure of a load impedance of a load coupled to an output of the power amplifier (110); and a DC-DC converter (326; 430) configured to adjust the supply voltage of the power amplifier (110) characterized by the fact that the operating point controller (320; 420) further comprises a mapping unit (324) configured to map the measure of the load impedance to a mapped voltage such that the mapped voltage is based on a phase of a reflection factor determined by the load impedance; wherein the DC-DC converter (326; 430) is configured to adjust the supply voltage of the power amplifier (110) based on the mapped voltage; and wherein the mapping unit (324) is configured to provide the mapped voltage such that an adjacent channel leakage power ratio value of the RF output signal (115) is within a predetermined range for a plurality of load impedances resulting in reflection factors of equal magnitude.

According to an example aspect of the present invention, there is provided an apparatus in a user equipment configured to receive, from a network node, a first information of an error vector magnitude, EVM, target allowed for the apparatus; adjust one or more digital predistortion, DPD, settings based at least in part on the received first information of the EVM target allowed for the apparatus; and transmit, to the network node, at least one signal at an EVM level based at least in part on the adjusted DPD settings.

The utility model discloses an intelligent underground remote leakage test system, and relates to the technical field of electric leakage test, and the system comprises a 5G / 6G remote leakage test module, a 5G / 6G remote leakage communication module, a grounding resistance detection module, and a remote leakage power supply which are connected with each other and are installed in a 5G / 6G remote leakage explosion-proof housing, and are transmitted to a ground communication system through an underground communication system. And the remote leakage test module is connected with the anti-violation cloud system and the mobile phone terminal APP, and is connected with the shunt switch A through a three-phase low-voltage line, or is connected with the high-voltage power supply equipment through an insulation monitoring line.

The present specification relates to the field of chip design and manufacturing, and particularly to a chip leakage power consumption optimization method and device based on graph partitioning. The method comprises: judging whether there is timing path margin in a chip, wherein the chip has physical perception capability; if yes, identifying low threshold voltage devices in the chip according to a plurality of preset constraint conditions, and performing graph partitioning on the device layout of the chip; based on the processing result of the graph partitioning, determining target optimization devices from the low threshold voltage devices that meet the preset constraint conditions; replacing the target optimization devices with high threshold voltage devices to optimize the chip leakage power consumption containing the target optimization devices. The present application constructs an optimized leakage power consumption operation space based on a physically perceived engineering environment. Through graph partitioning and replacement constraints, the combined logic devices are analyzed, replaced and optimized in a limited range, the data scale is controllable, the chip layout is optimized in the chip design and implementation process, and the optimization efficiency is improved.

The present application relates to the technical field of computing power scheduling, in particular to a dynamic computing power scheduling method and system for AI training tasks, which realizes the quantification of node thermal risk by obtaining the thermal state pressure index through the weighted calculation of thermal margin and temperature rise trend; obtains the static leakage power consumption from the total power consumption by stripping the dynamic power consumption, obtains the electrical state pressure index by combining the leakage temperature coefficient, and accurately identifies the risk of node thermal-electric positive and negative feedback instability; captures the implicit collapse problem of long-term performance of the node by calculating the deviation accumulation state through the exponential moving average; calculates the expected cooling time based on the heat capacity, cooling heat dissipation rate and idle power consumption, locks the scheduling state through the time lock mechanism, and offsets the influence caused by the inertia of the cooling system; realizes multi-dimensional risk warning, and the warning dimension is more comprehensive and the prediction accuracy is higher; calculates the computing power loss factor through the thermal and electrical pressure index, corrects the nominal computing power to obtain the effective available throughput, so that the scheduling and distribution of the AI training operator are more suitable for the real running state of the node.

An electric leakage protection circuit breaker comprises an electric leakage protection electrode and a circuit breaker electrode, and the electric leakage protection electrode is provided with an electric leakage power supply contact composed of a movable contact piece and a static contact piece, and a driving piece used for driving the movable contact piece and the static contact piece to be in contact and separated. An electric leakage power supply contact formed by the movable contact piece and the static contact piece is connected in series in a power supply loop for supplying power to the electronic component board and / or the electric leakage tripper, the driving piece is linked with an operating mechanism of the circuit breaker pole, and when a main loop of the circuit breaker pole is conducted, the driving piece is driven by the operating mechanism to drive the movable contact piece to be in contact with the static contact piece so as to supply power to the electric leakage tripper. Switching on the power supply loop; when the main loop of the circuit breaker pole is disconnected, the driving piece is driven by the operating mechanism to drive the movable contact piece to be separated from the static contact piece, or the driving piece is driven by the operating mechanism to be away from the movable contact piece, the movable contact piece is reset to the position separated from the static contact piece, and the power supply loop is disconnected. Damage caused by reverse connection of the wire inlet end and the wire outlet end of the circuit breaker pole by mistake during wiring is avoided.

An apparatus, such as a network node or gNB, determines an error vector magnitude (EVM) target allowed for a user equipment (UE), transmits the EVM target to the UE, and receives a corresponding signa

The present application relates to the technical field of metrology, in particular to a kind of power measurement method and structure of cluster leakage power sensor.The present application includes: setting leakage power sensor on each power supply branch circuit, respectively access the data of each leakage power sensor into public leakage power sensing module;Series standard error ware on public leakage power sensing module or any leakage power sensor;The reading of standard error ware is used to correct the reading of each leakage power sensor, and the actual leakage power value of each leakage power sensor is obtained.The present application can connect the leakage power sensor of each power supply branch into public leakage power sensing module to form cluster leakage power sensor, and the leakage power of a large number of users is uniformly managed and monitored, which improves the convenience of power leakage monitoring.