20 results about "Leakage power" patented technology

The invention provides a serialized memory access and computing collaboration method, system, equipment and medium, which parses the same external command in parallel through two command parsers with the same structure to collaboratively generate address information for memory access and an operation instruction for computing control, and the address information and the operation instruction are complementary in function and synchronous in time sequence. Compared with a traditional scheme depending on an OST buffer and matched control logic thereof, the architecture does not need to additionally cache control information or an intermediate state, so that the OST buffer and related read-write logic are effectively omitted, and the chip area overhead of the AI accelerator is remarkably reduced; meanwhile, dynamic read-write power consumption and static leakage power consumption are eliminated, and the energy efficiency ratio of the system is remarkably increased. Besides, the triggering of the memory access operation does not depend on the capacity of a buffer area, so that the number of memory accesses supported by a single task is not limited by the scale of the OST any more, and the flexibility and the parallel capability of task processing are greatly enhanced.

Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static / leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

The invention discloses a method for realizing time sequence and electric leakage power consumption coordinated optimization through critical path customization, and belongs to the field of signal processing. Extracting a key path which does not meet the time sequence constraint in the circuit; customizing the extracted critical path by selecting a low-threshold voltage and large-size transistor process library; and carrying out comprehensive simulation on the customized key path and other parts to confirm whether the time sequence constraint is met, and if not, repeating the previous step again. The low-threshold-voltage and large-size transistors are only adopted for critical paths, and the standard-threshold-voltage and standard-size transistors are adopted for other parts of the circuit, so that the number of the transistors with large electric leakage is reduced while the time sequence requirement is ensured, and the electric leakage power consumption is further reduced.

A network node, such as a gNB, determines an adjacent channel leakage power ratio (ACLR) requirement relaxation for a UE and transmits, to the UE, first information of the ACLR requirement relaxation

Various embodiments provide for grouping cells in a cell library based on iterative clustering, which can be used for pruning the cell library. In particular, various embodiments provide for grouping cells in a cell library based on iterative clustering in view of a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for grouping cells in a cell library based on iterative clustering in view of leakage power and then applying cell library pruning to optimize for cell leakage power.

The present application relates to the technical field of photovoltaics. Disclosed are a solar cell and a photovoltaic module. By rationally setting a ratio relationship between a transmission resistance heating power (P1) corresponding to all conductive semiconductor portions included in the solar cell and a reverse electric-leakage power (P2) corresponding to the solar cell, a reverse breakdown voltage and a hot spot risk of the solar cell are effectively reduced. Each conductive semiconductor portion in the solar cell is at least partially located between a first doped semiconductor portion and a second doped semiconductor portion, and only part of the first doped semiconductor portion is electrically connected to part of the second doped semiconductor portion by means of at least one conductive semiconductor portion. The conductivity type of different regions of each conductive semiconductor portion in the lengthwise direction thereof is opposite to the conductivity type of one of the first doped semiconductor portion and the second doped semiconductor portion. The ratio A of P1 to P2 is greater than or equal to 2%, but less than or equal to 50%.

The present application relates to a leakage power consumption optimization method and device of a chip. The method comprises: finding a timing logic device whose threshold voltage is lower than a predetermined threshold voltage in a circuit to form an initial device set; determining a first feature and a second feature of the timing logic device, the first feature comprising a timing margin of the timing logic device, and the second feature comprising a judgment result of whether there exists a replaceable target timing logic device corresponding to the timing logic device in a device library, the target timing logic device having a same function type as the timing logic device and a threshold voltage higher than that of the timing logic device; selecting a replaceable timing logic device from the initial device set according to the first feature, the second feature and a leakage power consumption optimization strategy parameter; and replacing the replaceable timing logic device in the target circuit with the target timing logic device. The method effectively reduces the leakage power consumption of the chip and improves the energy efficiency ratio of the chip under the premise of ensuring the timing performance of the circuit.

The utility model relates to the field of power junction box discloses an anti -electricity leakage power junction box, including the bottom plate, the inside of bottom plate is provided with the bolt hole, the inside installation of bolt hole has first hexagonal bolt, the upper surface fixed connection of bottom plate has junction box shell, the inside installation of junction box shell has the threaded rod, the outside screw thread connection of threaded rod has the nut, the inside installation of nut has second hexagonal bolt, the outside screw thread connection of threaded rod has the nut, the inside fixed connection of junction box shell has fixed establishment, fixed establishment includes fixed plate, the inside fixed connection of fixed establishment in junction box shell. In the utility model, through putting the power cord into the convex guide plate, the power cord is extruded to the convex guide plate, first spring and second spring produce the reaction force and extrude the convex guide plate at this moment, have realized the arrangement of power cord to make the power cord in junction box shell place neat.

Aspects of the subject disclosure address the traditional trade-off between performance and area, in relation to circuit and system design, together with power as an additional factor of consideration. Circuits and systems of this disclosure may realize a datapath of data in respect of memory state elements (e.g., registers, flops, etc.) that is dependent on multiple qualifiers. Aspects of this disclosure enhance (e.g., optimize) area and reduce leakage power associated with circuits and systems. Furthermore, aspects of this disclosure enable and enhance an insertion of clock-gating circuits or mechanisms to reduce dynamic-power consumption depending on states of the qualifiers.

According to an example aspect of the present invention, there is provided an apparatus in a user equipment configured to receive, from a network node, a first information of an error vector magnitude, EVM, target allowed for the apparatus; adjust one or more digital predistortion, DPD, settings based at least in part on the received first information of the EVM target allowed for the apparatus; and transmit, to the network node, at least one signal at an EVM level based at least in part on the adjusted DPD settings.

The utility model discloses an intelligent underground remote leakage test system, and relates to the technical field of electric leakage test, and the system comprises a 5G / 6G remote leakage test module, a 5G / 6G remote leakage communication module, a grounding resistance detection module, and a remote leakage power supply which are connected with each other and are installed in a 5G / 6G remote leakage explosion-proof housing, and are transmitted to a ground communication system through an underground communication system. And the remote leakage test module is connected with the anti-violation cloud system and the mobile phone terminal APP, and is connected with the shunt switch A through a three-phase low-voltage line, or is connected with the high-voltage power supply equipment through an insulation monitoring line.

The present specification relates to the field of chip design and manufacturing, and particularly to a chip leakage power consumption optimization method and device based on graph partitioning. The method comprises: judging whether there is timing path margin in a chip, wherein the chip has physical perception capability; if yes, identifying low threshold voltage devices in the chip according to a plurality of preset constraint conditions, and performing graph partitioning on the device layout of the chip; based on the processing result of the graph partitioning, determining target optimization devices from the low threshold voltage devices that meet the preset constraint conditions; replacing the target optimization devices with high threshold voltage devices to optimize the chip leakage power consumption containing the target optimization devices. The present application constructs an optimized leakage power consumption operation space based on a physically perceived engineering environment. Through graph partitioning and replacement constraints, the combined logic devices are analyzed, replaced and optimized in a limited range, the data scale is controllable, the chip layout is optimized in the chip design and implementation process, and the optimization efficiency is improved.

The present application relates to the technical field of computing power scheduling, in particular to a dynamic computing power scheduling method and system for AI training tasks, which realizes the quantification of node thermal risk by obtaining the thermal state pressure index through the weighted calculation of thermal margin and temperature rise trend; obtains the static leakage power consumption from the total power consumption by stripping the dynamic power consumption, obtains the electrical state pressure index by combining the leakage temperature coefficient, and accurately identifies the risk of node thermal-electric positive and negative feedback instability; captures the implicit collapse problem of long-term performance of the node by calculating the deviation accumulation state through the exponential moving average; calculates the expected cooling time based on the heat capacity, cooling heat dissipation rate and idle power consumption, locks the scheduling state through the time lock mechanism, and offsets the influence caused by the inertia of the cooling system; realizes multi-dimensional risk warning, and the warning dimension is more comprehensive and the prediction accuracy is higher; calculates the computing power loss factor through the thermal and electrical pressure index, corrects the nominal computing power to obtain the effective available throughput, so that the scheduling and distribution of the AI training operator are more suitable for the real running state of the node.

An electric leakage protection circuit breaker comprises an electric leakage protection electrode and a circuit breaker electrode, and the electric leakage protection electrode is provided with an electric leakage power supply contact composed of a movable contact piece and a static contact piece, and a driving piece used for driving the movable contact piece and the static contact piece to be in contact and separated. An electric leakage power supply contact formed by the movable contact piece and the static contact piece is connected in series in a power supply loop for supplying power to the electronic component board and / or the electric leakage tripper, the driving piece is linked with an operating mechanism of the circuit breaker pole, and when a main loop of the circuit breaker pole is conducted, the driving piece is driven by the operating mechanism to drive the movable contact piece to be in contact with the static contact piece so as to supply power to the electric leakage tripper. Switching on the power supply loop; when the main loop of the circuit breaker pole is disconnected, the driving piece is driven by the operating mechanism to drive the movable contact piece to be separated from the static contact piece, or the driving piece is driven by the operating mechanism to be away from the movable contact piece, the movable contact piece is reset to the position separated from the static contact piece, and the power supply loop is disconnected. Damage caused by reverse connection of the wire inlet end and the wire outlet end of the circuit breaker pole by mistake during wiring is avoided.

An apparatus, such as a network node or gNB, determines an error vector magnitude (EVM) target allowed for a user equipment (UE), transmits the EVM target to the UE, and receives a corresponding signa

The invention relates to the technical field of power banks, in particular to an electric leakage power bank screening method and device, a storage medium and a power bank. The method comprises the following steps: inputting an upgrading program to a to-be-screened power bank and a qualified power bank, enabling the to-be-screened power bank to obtain a first power-down voltage of a battery of the to-be-screened power bank based on the upgrading program, displaying the first power-down voltage, enabling the qualified power bank to obtain a second power-down voltage of the battery of the to-be-screened power bank based on the upgrading program, and displaying the second power-down voltage of the battery of the to-be-screened power bank; displaying the second power-down voltage; obtaining a displayed first power-down voltage and a displayed second power-down voltage, and comparing the first power-down voltage with the second power-down voltage; and judging whether the to-be-screened charge pal is an electric leakage charge pal or not according to a comparison result. Under the condition that the charge pal is not disassembled and damaged, the electric leakage charge pal can be stably and effectively screened out, the loss is reduced, and the risk that the electric leakage charge pal flows into the market is reduced.

The invention discloses a distribution box with an electric leakage alarm detection function, and relates to the technical field of distribution boxes. According to the invention, the zero sequence current transformer is matched with the signal processing unit, the single-chip microcomputer and the audible and visual alarm, so that the zero sequence current transformer can conveniently monitor the electric leakage condition of the line in real time, and then the zero sequence current transformer is matched with the signal processing unit and the single-chip microcomputer, so that the leakage distribution box can be accurately positioned. The positioning efficiency of an electric leakage fault in a complex power distribution scene is improved; by analyzing the magnitude, duration and variation trend of the leakage current in real time, dynamically correcting scores based on historical data and outputting multi-stage warning signals, a worker can take differentiated emergency measures according to the severity of leakage, and the pertinence and efficiency of emergency response are improved; through monitoring four dimensions of data abnormity, alarm behaviors, state parameters and historical consistency, a real-time fault rate is calculated in combination with a dynamic weight, and once a detection module has a fault, a system can send out a fault alarm in time.

The disclosed techniques provide a method for creating a system-on-chip (SoC) integrated circuit (IC). The method includes, for each chiplet, determining a tested leakage power consumption of cores on the chiplet. The pre-binning also includes categorizing the chiplets into categories. The categories are based on the tested leakage power consumption of the chiplets. The categories include a first category and a second category, such that each chiplet that is categorized in the first category has a tested leakage power consumption that is less than a nominal leakage power consumption, and such that each chiplet that is categorized in the second category has a tested leakage power consumption that is greater than the nominal leakage power consumption. The method also includes creating the SoC IC such that the SoC IC includes at least one chiplet from the first category and at least one chiplet from the second category.

According to an example aspect of the present invention, there is provided an apparatus in a user equipment configured to receive, from a network node, a first information a first information of adjacent channel leakage power ratio, ACLR, requirement relaxation for the apparatus; and transmit, to the network node, at least one signal with a relaxed ACLR requirement based on the received first information.

This application discloses a method, apparatus, and storage medium for eliminating input voltage in an energy conversion system. The energy conversion system includes a boost circuit. The method includes: determining that there is no energy input at the input terminal; obtaining the maximum leakage power of the diode in the boost circuit; and adjusting the frequency or duty cycle of the drive signal of the switching transistor in the boost circuit so that the input power at the input terminal is less than or equal to the maximum leakage power. The voltage elimination method of this application can avoid power loss and significant temperature increases in the energy-consuming resistor, reduce the size of the equipment, and improve the reliability of the system.