High-performance low leakage power consumption master-slave type D flip-flop

Abstract

The invention discloses a high-performance low leakage power consumption master-slave type D flip-flop. The high-performance low leakage power consumption master-slave type D flip-flop is characterized by comprising a clock signal inverter circuit, a master latch circuit, a slave latch circuit, an N-channel metal oxide semiconductor (NMOS) pipe power control switch, a P-channel Metal Oxide Semiconductor (PMOS) pipe power control switch and a maintaining inverter. The clock signal inverter circuit is connected with the master latch circuit, the clock signal inverter circuit is connected with the slave latch circuit, the master latch circuit is connected with the slave latch circuit, the slave latch circuit is connected with the maintaining inverter, the maintaining inverter is connected with the PMOS pipe power control switch, the clock signal inverter circuit, the master latch circuit and the slave latch circuit are all connected with the NMOS pipe power control switch, and the maintaining inverter is connected with the PMOS pipe power control switch. The high-performance low leakage power consumption master-slave type D flip-flop has the advantages of being simple in circuit structure, small in the number of transistors, simple in timing sequence switching of a normal working state and a sleep mode, good in working performance, low in dynamic power consumption and leakage power consumption, and suitable for being used as a standard cell of a digital circuit to be applicable to the design of a low power consumption integrated circuit in deep submicron complementary metal-oxide-semiconductor transistor (CMOS) process.

Description

technical field [0001] The invention relates to a D flip-flop, in particular to a master-slave D flip-flop with high performance and low leakage power consumption. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the scale and complexity of existing integrated circuits are increasing day by day, and the problem of power consumption of integrated circuits is becoming more and more prominent. Power consumption has become a factor in addition to speed and area in integrated circuit design Another important constraint problem of IC, so the low-power design technology of integrated circuits has become an important research hotspot in the field of integrated circuit design. The power consumption of CMOS digital integrated circuits is mainly composed of dynamic power consumption, short-circuit power consumption and leakage current power consumption. In the CMOS technology above 0.13μm, the dynamic power consumption accounts f...

AI Technical Summary

Problems solved by technology

However, the disadvantage of this circuit is that the clock inverter is still active, and additional control signals are required to enter the sleep and active states, resulting in complex operation timing; the memory unit is always active, which increases the dynamic power consumption of the flip-flop. Moreover, the use of more transistors increases the silicon area of ​​the flip-flop, thereby increasing the manufacturing cost

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