472 results about "Standard cell" patented technology

The invention provides a logic synthesis cutting delay prediction method based on a graph neural network, which comprises the following steps of: firstly, constructing a cutting (Cut) delay prediction data set of a logic synthesis circuit, then extracting structural and functional features of nodes in a cutting sub-graph, constructing a heterogeneous cutting level graph taking a cutting super node as a center, and finally, carrying out segmentation on the heterogeneous cutting level graph. And packaging into a graph neural network input format. Then, a delay prediction model is constructed, the delay prediction model comprises a graph neural network module and a multi-layer perceptron module, the graph neural network module extracts circuit structure features and pointer attention mechanism dynamic association standard cell library features through SAGE convolution, and enhanced cutting representation is formed; and finally, carrying out delay prediction on cutting in a new circuit by utilizing the trained model. According to the method, the cutting structure modeling capability and the delay prediction precision are effectively improved, the method can be used for optimizing a cutting selection strategy in a synthesizer, and the logic comprehensive quality is improved.

The invention belongs to the technical field of semiconductor design automation, and provides a standard cell physical layout generation method and related equipment. The method comprises the steps of obtaining design data of a standard unit to be designed and multi-patterning process constraint parameters under a target process; according to the design data and the multi-patterning process constraint parameters, a transistor in a to-be-designed standard cell is arranged, in the arrangement process, folding and / or source-drain sharing are / is dynamically carried out on the transistor in the to-be-designed standard cell, and the feasibility of a gate cutting process and a contact through hole cutting process is synchronously detected; and after the layout of the transistors in the standard unit to be designed is completed, wiring is carried out on the standard unit to be designed by adopting a multi-network synchronous optimization strategy so as to generate a standard unit physical layout, and in the wiring process, sign-off data is fused so as to optimize wiring. Through the technical scheme provided by the invention, the generation efficiency of the standard cell physical layout can be improved.

The invention belongs to the technical field of integrated circuit design automation, and discloses an anti-radiation standard unit automatic layout method, which adopts a two-stage reinforcement learning strategy: in the first stage, training a device layout strategy model, extracting MOS device information by analyzing a CDL file, and constructing a circuit diagram structure as state representation; generating a preliminary device layout result by using a dynamic action mask mechanism; and in the second stage, independently training the guard band insertion strategy model, and optimizing the guard band insertion position and sequence based on the candidate insertion point set so as to meet the anti-radiation design rule and reduce the wiring difficulty. The two stages both adopt a Maskable PPO algorithm, encourages gate alignment, source-drain proximity and shortest connection path through a reward function, and punishes layout conflicts and DRC violations. According to the invention, by means of the two-stage design of division of labor and cooperation, the layout efficiency and compliance of the anti-radiation standard unit are significantly improved, and the method has the characteristics of high efficiency, self-adaption and high engineering practicability.

The invention provides a power consumption feature extraction method and system for a static random access memory standard cell library, electronic equipment and a storage medium, and the method comprises the steps: S1, reading a standard cell model file, a standard cell netlist and a standard cell time sequence path of a static random access memory, and constructing and generating an excitation waveform description file; s2, establishing a simulation file of the static random access memory standard unit, simulating the static random access memory standard unit, and respectively obtaining electrical characteristic data of an input pin and an output pin of the static random access memory standard unit; s3, analyzing the electrical characteristic data of the static random access memory standard unit, and obtaining a short-circuit power consumption time sequence path and a switching power consumption time sequence path existing in the static random access memory standard unit; and S4, respectively calculating power consumption values of each switching power consumption time sequence path and each short-circuit power consumption time sequence path. According to the method, the power consumption characteristics of the SRAM standard cell are extracted in the design stage of the standard cell library, and the precision and efficiency of power consumption analysis can be improved.

A semiconductor structure includes a substrate; a first column of active regions over the substrate; a second column of active regions over the substrate; and a dummy padding disposed between the first and the second columns from a top view. The dummy padding includes multiple dummy regions. A first dummy region of the multiple dummy regions is disposed between a first active region in the first column of active regions and a second active region in the second column of active regions. An outer boundary line tracing an edge of the first active region, an edge of the first dummy region, and an edge of the second active region includes at least two substantially 90-degree bends from a top view. The first and the second active regions include a semiconductor material doped with a same dopant.

The invention discloses an automatic generation method for a standard cell layout with a switchable power consumption area, and relates to an LELE (Lithography-Etching-Lithography-Etching) technology, which is used for carrying out data preprocessing on a circuit netlist; respectively performing source-drain sharing operation on NMOS (N-channel Metal Oxide Semiconductor) tubes and PMOS (P-channel Metal Oxide Semiconductor) tubes in the preprocessed circuit netlist to obtain a layout with an optimal area; performing gate pairing operation on NMOS (N-channel Metal Oxide Semiconductor) transistors and PMOS (P-channel Metal Oxide Semiconductor) transistors in the preprocessed circuit netlist to form MOS (Metal Oxide Semiconductor) transistor pairs, and performing source-drain sharing operation on the MOS transistor pairs to obtain a layout with optimal power consumption; grid modeling is carried out based on design rule parameters of the process library, and a grid point canvas is established; and adding the layout with the optimal area and the layout with the optimal power consumption into the lattice point canvas, and simulating manual wiring through an A star algorithm to obtain a layout with the optimal index. According to two independent layout strategies, the grid layout is created in combination with a process design rule, and manual wiring is simulated by using an algorithm, so that the feasibility of the whole process of layout and wiring is realized.

A dynamic grid allocation system for power distribution in the development of integrated circuits in the sub-five-nanometer range, wherein the system comprises the following: a placement processor unit configured to receive a synthesized netlist comprising a variety of standard cells and macros, each associated with switching activity data derived from simulation or synthesis activity profiles, and to generate a spatial cell placement arrangement by grouping cells into microzones based on activity correlation, time sensitivity, and connection proximity; a power density calculation unit coupled to the placement processor unit and configured to calculate the local power density and instantaneous current demand for each microzone based on the spatial distribution of switching operations, capacity load, and effective switching frequencies; a dynamic network generation unit coupled to the power density calculation unit and configured to generate a multilayer power distribution network with variable network topology, where the width, spacing, via density and metal layer assignment of the power network are adaptively determined as continuous functions of the localized power density and power demand calculated for each microzone; a topology control processor configured to monitor voltage drop and electromigration data obtained from signoff analyses or predictive models in real time and dynamically adjust the power grid topology parameters to ensure compliance with predefined reliability thresholds for voltage drop and electromigration; a predictive current modeling unit configured to receive historical switching and voltage data, train a predictive model for transient current peaks, and provide predictive power boost instructions to the dynamic grid generation unit before power integrity violations occur; and A feedback synchronization controller is communicatively connected to the placement processor unit and the topology control processor, whereby the feedback synchronization controller continuously exchanges updated power density information and placement constraints, so that cell placement and network topology adapt together in real time, thereby minimizing routing congestion, ensuring a uniform voltage distribution, and guaranteeing compliance with electromigration and IR drop regulations under various activity conditions.

The invention discloses a method for testing short-circuit current of a solar cell. The method comprises the following steps: acquiring a first corresponding relation between the photoluminescence intensity of a standard cell under standard illumination intensity and the electroluminescence intensity of the standard cell under open-circuit voltage; providing a battery piece to be tested; irradiating partial areas of the first surface of the to-be-measured battery piece through a plurality of light sources with different wavelengths, and measuring to obtain bright area luminous intensity of a light receiving area and dark area luminous intensity of a non-light receiving area under the irradiation of the light sources with different wavelengths; according to the first corresponding relation and the luminous intensity of each bright area, obtaining basic electroluminescence intensity corresponding to the luminous intensity of each bright area; obtaining the equivalent external quantum efficiency under the irradiation of each wavelength light source according to the basic electroluminescence intensity and the dark space luminescence intensity corresponding to each wavelength light source; constructing a wavelength-equivalent external quantum efficiency curve; carrying out integral calculation on the wavelength-equivalent external quantum efficiency curve to obtain short-circuit current density, and calculating the short-circuit current of the battery piece to be measured according to the area of the first surface.

The invention discloses a standard unit aging test circuit and a test control method, and the method comprises the steps: enabling a state machine to precisely control the aging stress application and test action switching of each monitor module through a cooperative architecture of the state machine, a difference frequency counting module and the monitor modules, a standard unit to be measured continuously bears stress during non-measurement and rapidly generates stress frequency during measurement, the difference frequency counting module converts frequency difference caused by aging into a quantitative result by comparing the stress frequency with reference frequency, high-precision data is provided for aging evaluation, and the accuracy of aging evaluation is improved. The method realizes deep fusion of the difference frequency principle and the aging measurement process of the standard unit, improves the accuracy of the aging test of the standard unit, and meanwhile, more accurately monitors the temperature information of the standard unit through the frequency difference between the stress frequency signal and the reference frequency signal in combination with the pre-calibrated frequency-temperature characteristic curve.

A high performance (HP) standard cell architecture for logic cells used in a semiconductor device or product. An example semiconductor device includes a plurality of cells surrounded by a cell boundary, and a backside power delivery network (PDN) routed to the plurality of cells. At least one cell of the plurality of cells has an arrangement of transistors within the cell boundary, the arrangement of transistors coupled together to generate an output signal at an output signal node. There is a metal 0 layer above the arrangement of transistors, the metal 0 layer includes one or more input signal traces and an output signal trace. The output signal trace and the input signal traces are substantially parallel inside the cell boundary and have a first width near the cell boundary; the output signal trace has a region of a wider metal 0 inside the cell boundary.

The invention discloses a method for generating a standard cell library K library, belongs to the field of integrated circuit design, solves the fundamental defects of flow disorder, module tight coupling and difficulty in expansion and maintenance in the prior art, and is a basis for realizing the characteristics of high efficiency and flexibility. The method comprises the following specific steps: front-end analysis and configuration; an SPICE simulation script is generated; sPICE simulation is executed in parallel; simulation result analysis and data processing; and generating a file in a Liberty format.

The invention discloses a conversion circuit for measuring time sequence arc delay of a standard unit, which belongs to the field of integrated circuits and comprises a time sequence arc delay clock generation circuit of the standard unit, a clock frequency dividing circuit, a control module and an IO output module. The standard unit time sequence arc delay clock generation circuit connects a plurality of same standard units in series to form a test chain, delays the time sequence arc of a single standard unit, and outputs the time sequence arc in a stable-frequency clock form; the clock frequency division circuit performs frequency division on the stable clock generated by the standard unit time sequence arc delay clock generation circuit through an algorithm, so that the stable clock can be detected by a machine table; the control module selects a plurality of standard cell types from the control signal, selects a time sequence arc, selects a cascade stage number, and controls the output of the clock frequency dividing circuit; and the IO output module outputs the frequency-divided clock generated on the chip through an IO port so as to be detected by a machine. According to the invention, extra power consumption, area and design complexity caused by an extra on-chip high-frequency clock can be effectively avoided.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

The invention relates to the technical field of electronic design automation, and discloses a standard cell layout legalization method and system based on a graph theory constraint graph, and the method comprises the steps: building a bidirectional directed constraint graph based on an existing layout and a design rule, and building a directed edge between adjacent graph edges according to the design rule; traversing the constraint graph, detecting whether a directed edge which does not meet a constraint condition exists, and if so, identifying the directed edge as a constraint violation edge; for two end points of each constraint violation edge, searching a key path based on a depth-first search algorithm, and determining a maximum movable distance in combination with a greedy strategy; moving the endpoint to a legal position according to the critical path and the maximum movable distance, and updating the position of a related node in the constraint graph; and mapping the position changes of the nodes in the constraint graph back to the corresponding graph edges in the layout, and outputting the legalized layout, so that efficient and automatic repair of design rule violation is realized through the method, and the layout compliance rate and the area optimization effect are remarkably improved.

The invention relates to the technical field of chip verification, in particular to a front-end low-power-consumption verification environment generation method, electronic equipment and a medium, and the method comprises the steps: S1, obtaining register transfer level code information An and unified power consumption format information Bn of a chip; s2, acquiring a target configuration file; s3, analyzing the target configuration file, if Cn is set as a first identifier, adding A1n and B1n into a target compiling file list, and if Cn is set as a second identifier, adding A2n and B2n into the target compiling file list; s4, screening the standard cell library information file corresponding to at least one process corner from each standard cell library information file, and adding the standard cell library information file into a target compiling file list; and S5, compiling and generating a front-end low-power-consumption verification environment based on the target compiling file list. According to the invention, the generation efficiency and accuracy of the front-end low-power-consumption verification environment are improved.

The invention provides an integrated circuit collaborative layout method, device and equipment, which are applied to the technical field of integrated circuit design, and are characterized in that a proper net model is selected through a net relationship, and a matrix and a vector of quadratic programming layout are constructed according to the net model, so that an initial unit layout is efficiently solved; a batch processing strategy is adopted to carry out overlapping optimization on a standard cell and a macro cell to generate a legalized layout solution, an interaction force between anchor point simulation units is introduced, the layout is continuously iterated and refined until the line length converges, and a final high-quality layout solution is obtained, so that the overall performance of a chip is improved, the power consumption is reduced, and the overall performance of the chip is improved. And the macro cells and the standard cells are distributed to different chips in the three-dimensional stacked structure, so that the requirement that different chip layers adopt different design processes is met, and the production cost is effectively reduced.

The invention provides a method and device for optimizing the layout of a digital logic circuit and a storage medium, and the method comprises the steps: determining a first layout of the digital logic circuit, the first layout comprises a plurality of macro cells and a plurality of standard cells, determining channels formed between the adjacent macro cells, and optimizing the layout of the digital logic circuit based on an optimization target of the digital logic circuit, according to the positions of the standard unit and the channel, the target step length parameter of the standard unit is determined, the optimization target comprises at least one of a line length target, a density target and a time sequence target, and the standard unit is adjusted based on the target step length parameter so as to optimize the layout of the digital logic circuit. By means of the method, automatic layout optimization of the digital logic circuit can be achieved, the influence of a channel on layout optimization is reduced, and the performance of a chip is further improved.

The invention provides a DFT resource configuration prediction method and device, electronic equipment and a storage medium, and belongs to the technical field of electronic design automation, and the method comprises the steps: determining a reference device density based on a process node of a target chip; determining an effective digital logic layout area based on the chip planning area of the target chip and the estimated non-digital logic function region; according to a utilization rate factor corresponding to the physical design constraint of the target chip, correcting the effective digital logic layout area to obtain an available standard cell layout capacity; according to the standard unit layout capacity and the reference device density, generating a time sequence element number prediction interval of the target chip through a logic depth mapping model; and according to the time sequence element number prediction interval, generating testability design DFT architecture configuration parameters of the target chip. The number of chip registers can be quickly and accurately predicted and the DFT architecture configuration parameters can be generated in the early stage of chip design.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

Some aspects utilize an iterative process to synthesis a logic network within an ASIC using lookup table (LUT) optimization techniques. The logic network may be represented by an And-Inverter graph (AIG), as described in more detail below. On each iteration, the current AIG representation of the logic network is mapped to a network of k-LUTs. A k-LUT is a lookup table that can represent any function of k variables. This network may then be improved using LUT optimization techniques. The improved network of k-LUTs is decomposed into a trial AIG representation, which may be further improved for example by applying Boolean-based optimization techniques. The current AIG representation may then be updated in accordance with the quality of the trial AIG representation produced by the current iteration. The final AIG representation from the iterations is synthesized to a netlist of standard cells.

The invention discloses an electroplating intermediate stability evaluation method based on machine learning, particularly relates to the field of electroplating process quality analysis, is used for solving the problem that aging stability of an intermediate is difficult to reflect and early warning is difficult, and comprises the following steps: collecting electrochemical curves of different aging times under a standard cell configuration condition, and constructing a sample sequence arranged according to the aging times; extracting a time normalization electrochemical attenuation index and an aging form offset feature, forming a simplified input feature vector in combination with the key electrochemical feature value, and learning a corresponding relation between an electrochemical behavior and a stability level by using a stability sensitivity judgment model and an electroplating intermediate stability evaluation model; and outputting an electroplating intermediate stability prediction result according to the real-time electrochemical curve on a production site, and continuously updating the model in combination with the actual use condition.

The invention discloses a standard cell library delay test system and a test method thereof, the test system comprises a primary pulse generator, the clock input end of the primary pulse generator receives a test enable signal and generates a start pulse signal; the clock input end of each stage of trigger is connected to the output end of the previous stage of trigger, and the clock input end of the first stage of trigger receives an operation result of a starting pulse signal and an output signal of the last stage of trigger through a logic OR gate; the test system further comprises a feedback control module including a first phase inverter and a logic AND gate, the first phase inverter negates an output signal of any one trigger in the first three stages of the delay chain and then performs logic AND operation with a global reset signal, and a dynamic reset signal is generated and connected to the reset end of the primary pulse generator. According to the technical scheme, the trigger delay chains connected in series in multiple stages and the feedback control module are designed, an additional reference clock path is not needed, and the circuit area is reduced.

A standard cell layout that may be implemented in FinFET devices or nanosheet FET devices is disclosed. The standard cell layout includes power supply connections from both a topside metal layer and a backside metal layer. A device in the standard cell may be connected to both the topside metal layer and the backside metal layer. Source / drain regions of the device may be connected the metal layers using via contacts within the standard cell layout. Connections to power supply rails from the topside metal layer and the backside metal layer may also be included in the standard cell layout. The rails may be connected to a power supply such that the power supply provides power to the device through both the topside and backside metal layers.

The invention discloses a viscoelastic boundary verification method, device and equipment based on isoparametric elements and a medium, and the method comprises the steps: building a three-dimensional geometric model of a target structure according to geometric dimensions and material attributes, discretizing the three-dimensional geometric model into initial three-dimensional subunits, and then building an initial finite element mesh model; after identifying a target boundary surface to be applied with an artificial viscoelastic boundary, assigning boundary parameters to obtain each three-dimensional subunit and form a finite element model; all the three-dimensional subunits are mapped to a standard unit through equal-parameter coordinate transformation, an equivalent stiffness coefficient matrix and an equivalent damping coefficient matrix are obtained through calculation and then stacked and assembled, and an overall stiffness matrix and an overall damping matrix are formed; and calculating displacement response data based on the overall stiffness matrix and the overall damping matrix. According to the embodiment of the invention, by introducing the isoparametric coordinate transformation, the irregular boundary form can be directly processed without introducing an additional boundary unit, and the calculation requirement of an actual complex engineering model is met.

The invention provides a macro-cell layout evaluation optimization method based on a large language model, and belongs to the field of electronic design automation. According to the method, a large language model is introduced to assist layout generation, a current initial layout is improved in combination with connection weight analysis, on the other hand, an improved result is judged and continuously iterated according to natural language feedback of an experience manual or an expert, and closed-loop optimization is formed; carrying out weight quantization on direct and indirect signal paths among macro units, constructing a logic association strength matrix, and realizing accurate identification and priority ranking of key time sequence paths; the availability score of each candidate layout scheme is calculated through a layout availability scoring module, dynamic measurement is carried out on surrounding standard unit resources, the resource distribution state is evaluated in real time, the position of a macro unit is actively adjusted, and resource congestion or waste is avoided; the method is deeply integrated with an open source EDA tool, the dependence on a commercial tool is reduced, the tool chain deployment and iteration period is shortened, and the transportability and usability of the method are guaranteed.

The invention provides a circuit energy efficiency automatic optimization method. The method comprises the following steps: firstly, modeling a circuit gate-level netlist into a directed graph; extracting a key path by using a static time sequence analysis tool, and extracting a context sensing key sub-graph containing the path and a first-order neighborhood node of the path; thirdly, feature coding is conducted on the key sub-graphs through a graph neural network, and state vectors representing the local state of the circuit are generated; the state vector is input to a reinforcement learning policy network to decide a drive capability adjustment action for a particular standard cell. And the system modifies the netlist according to the action, calls the static time sequence analysis tool again to evaluate the modified performance, power consumption and area indexes, and generates a reward signal to iteratively optimize the strategy network. By constructing the closed-loop optimization process, the problems of low manual optimization efficiency and unbalanced power consumption and area balance are solved, automatic and intelligent collaborative optimization of circuit energy efficiency is realized, and the design quality and efficiency are remarkably improved.

An integrated circuit includes plural standard cells performing a same function. The standard cells include a first standard cell and a second standard cell, and the first standard cell and the second standard cell are to the same as each other in terms of an arrangement of internal conductive patterns and are different from each other in terms of a position of a via formed over a gate line through which an input signal is input.

The invention relates to a unit statistical time sequence prediction method based on a graph neural network, and the method comprises the steps: S1, obtaining a standard unit netlist, extracting all transistors and other elements in the standard unit netlist as a first type of nodes and a second type of nodes, building a first edge based on the connection relation between the other elements and the transistors, and building a second edge based on the connection relation between the first edge and the second edge; constructing an initial heterogeneous graph; s2, according to the basic principle of a circuit, simplifying the initial graph by using a redundant parasitic deletion method, restoring the first type of nodes deleted in the simplification process, and constructing virtual edges for the first type of nodes without direct connection elements to connect the nearest other first type of nodes to obtain a simplified heterogeneous graph; s3, according to element types corresponding to two nodes connected with each edge in the simplified heterogeneous graph, establishing an adjacent matrix for each type of connection, and constructing a corresponding feature matrix; and S4, inputting the constructed adjacency matrix and the feature matrix into the trained heterogeneous graph attention network to obtain a statistical delay prediction result. Compared with the prior art, accurate and efficient statistical time sequence representation can be carried out on the standard cell library.

The invention relates to the technical field of chip simulation, in particular to a chip simulation method, a chip simulation device, chip simulation equipment and a medium, the method comprises the following steps: in a comprehensive logic stage of a chip, performing comprehensive logic simulation after reading an actual layout plan to obtain a comprehensive netlist, the comprehensive netlist comprises interconnection line delay data and time sequence library information, the layout planning comprises specific position information of a hard core and a standard unit of the chip; generating a standard delay format file according to the interconnection line delay data and the time sequence library information; the integrated netlist and the standard delay format file are read into a static time sequence analysis tool for integration post-simulation, and a time sequence report is obtained; and determining whether a time sequence problem exists or not according to the time sequence report, and if so, repairing the path with the time sequence problem. According to the method, the accurate delay problem can be obtained through quick simulation.

The application discloses a circuit pre-training method and device based on a graph neural network and electronic equipment, comprising the following steps: for a large-scale circuit, a circuit network graph is constructed, a random walk road is generated, and the road is used as a sample for model training; a node2vec model is trained using the road sample; a model with the minimum loss function value is selected as an optimal model; and the optimal model is loaded, and representation vectors of all nodes are output and saved. In the application, the node2vec pre-training model of the graph neural network is used, the information of a long-distance standard unit is fully absorbed to absorb local circuit structure features, deep representation of nodes is automatically learned from the circuit structure, and tedious manual feature engineering is avoided, thereby providing high-quality representation vectors for a downstream model. The node representation learned by the node2vec model is a task-independent general feature, can be flexibly applied to various downstream tasks, and provides support for subsequent circuit analysis and optimization design work.