305 results about "Standard cell" patented technology

The invention belongs to the technical field of integrated circuit design automation, and discloses an anti-radiation standard unit automatic layout method, which adopts a two-stage reinforcement learning strategy: in the first stage, training a device layout strategy model, extracting MOS device information by analyzing a CDL file, and constructing a circuit diagram structure as state representation; generating a preliminary device layout result by using a dynamic action mask mechanism; and in the second stage, independently training the guard band insertion strategy model, and optimizing the guard band insertion position and sequence based on the candidate insertion point set so as to meet the anti-radiation design rule and reduce the wiring difficulty. The two stages both adopt a Maskable PPO algorithm, encourages gate alignment, source-drain proximity and shortest connection path through a reward function, and punishes layout conflicts and DRC violations. According to the invention, by means of the two-stage design of division of labor and cooperation, the layout efficiency and compliance of the anti-radiation standard unit are significantly improved, and the method has the characteristics of high efficiency, self-adaption and high engineering practicability.

The invention provides a power consumption feature extraction method and system for a static random access memory standard cell library, electronic equipment and a storage medium, and the method comprises the steps: S1, reading a standard cell model file, a standard cell netlist and a standard cell time sequence path of a static random access memory, and constructing and generating an excitation waveform description file; s2, establishing a simulation file of the static random access memory standard unit, simulating the static random access memory standard unit, and respectively obtaining electrical characteristic data of an input pin and an output pin of the static random access memory standard unit; s3, analyzing the electrical characteristic data of the static random access memory standard unit, and obtaining a short-circuit power consumption time sequence path and a switching power consumption time sequence path existing in the static random access memory standard unit; and S4, respectively calculating power consumption values of each switching power consumption time sequence path and each short-circuit power consumption time sequence path. According to the method, the power consumption characteristics of the SRAM standard cell are extracted in the design stage of the standard cell library, and the precision and efficiency of power consumption analysis can be improved.

A dynamic grid allocation system for power distribution in the development of integrated circuits in the sub-five-nanometer range, wherein the system comprises the following: a placement processor unit configured to receive a synthesized netlist comprising a variety of standard cells and macros, each associated with switching activity data derived from simulation or synthesis activity profiles, and to generate a spatial cell placement arrangement by grouping cells into microzones based on activity correlation, time sensitivity, and connection proximity; a power density calculation unit coupled to the placement processor unit and configured to calculate the local power density and instantaneous current demand for each microzone based on the spatial distribution of switching operations, capacity load, and effective switching frequencies; a dynamic network generation unit coupled to the power density calculation unit and configured to generate a multilayer power distribution network with variable network topology, where the width, spacing, via density and metal layer assignment of the power network are adaptively determined as continuous functions of the localized power density and power demand calculated for each microzone; a topology control processor configured to monitor voltage drop and electromigration data obtained from signoff analyses or predictive models in real time and dynamically adjust the power grid topology parameters to ensure compliance with predefined reliability thresholds for voltage drop and electromigration; a predictive current modeling unit configured to receive historical switching and voltage data, train a predictive model for transient current peaks, and provide predictive power boost instructions to the dynamic grid generation unit before power integrity violations occur; and A feedback synchronization controller is communicatively connected to the placement processor unit and the topology control processor, whereby the feedback synchronization controller continuously exchanges updated power density information and placement constraints, so that cell placement and network topology adapt together in real time, thereby minimizing routing congestion, ensuring a uniform voltage distribution, and guaranteeing compliance with electromigration and IR drop regulations under various activity conditions.

The invention discloses a conversion circuit for measuring time sequence arc delay of a standard unit, which belongs to the field of integrated circuits and comprises a time sequence arc delay clock generation circuit of the standard unit, a clock frequency dividing circuit, a control module and an IO output module. The standard unit time sequence arc delay clock generation circuit connects a plurality of same standard units in series to form a test chain, delays the time sequence arc of a single standard unit, and outputs the time sequence arc in a stable-frequency clock form; the clock frequency division circuit performs frequency division on the stable clock generated by the standard unit time sequence arc delay clock generation circuit through an algorithm, so that the stable clock can be detected by a machine table; the control module selects a plurality of standard cell types from the control signal, selects a time sequence arc, selects a cascade stage number, and controls the output of the clock frequency dividing circuit; and the IO output module outputs the frequency-divided clock generated on the chip through an IO port so as to be detected by a machine. According to the invention, extra power consumption, area and design complexity caused by an extra on-chip high-frequency clock can be effectively avoided.

The invention relates to the technical field of electronic design automation, and discloses a standard cell layout legalization method and system based on a graph theory constraint graph, and the method comprises the steps: building a bidirectional directed constraint graph based on an existing layout and a design rule, and building a directed edge between adjacent graph edges according to the design rule; traversing the constraint graph, detecting whether a directed edge which does not meet a constraint condition exists, and if so, identifying the directed edge as a constraint violation edge; for two end points of each constraint violation edge, searching a key path based on a depth-first search algorithm, and determining a maximum movable distance in combination with a greedy strategy; moving the endpoint to a legal position according to the critical path and the maximum movable distance, and updating the position of a related node in the constraint graph; and mapping the position changes of the nodes in the constraint graph back to the corresponding graph edges in the layout, and outputting the legalized layout, so that efficient and automatic repair of design rule violation is realized through the method, and the layout compliance rate and the area optimization effect are remarkably improved.

The invention provides a DFT resource configuration prediction method and device, electronic equipment and a storage medium, and belongs to the technical field of electronic design automation, and the method comprises the steps: determining a reference device density based on a process node of a target chip; determining an effective digital logic layout area based on the chip planning area of the target chip and the estimated non-digital logic function region; according to a utilization rate factor corresponding to the physical design constraint of the target chip, correcting the effective digital logic layout area to obtain an available standard cell layout capacity; according to the standard unit layout capacity and the reference device density, generating a time sequence element number prediction interval of the target chip through a logic depth mapping model; and according to the time sequence element number prediction interval, generating testability design DFT architecture configuration parameters of the target chip. The number of chip registers can be quickly and accurately predicted and the DFT architecture configuration parameters can be generated in the early stage of chip design.

Some aspects utilize an iterative process to synthesis a logic network within an ASIC using lookup table (LUT) optimization techniques. The logic network may be represented by an And-Inverter graph (AIG), as described in more detail below. On each iteration, the current AIG representation of the logic network is mapped to a network of k-LUTs. A k-LUT is a lookup table that can represent any function of k variables. This network may then be improved using LUT optimization techniques. The improved network of k-LUTs is decomposed into a trial AIG representation, which may be further improved for example by applying Boolean-based optimization techniques. The current AIG representation may then be updated in accordance with the quality of the trial AIG representation produced by the current iteration. The final AIG representation from the iterations is synthesized to a netlist of standard cells.

The invention discloses an electroplating intermediate stability evaluation method based on machine learning, particularly relates to the field of electroplating process quality analysis, is used for solving the problem that aging stability of an intermediate is difficult to reflect and early warning is difficult, and comprises the following steps: collecting electrochemical curves of different aging times under a standard cell configuration condition, and constructing a sample sequence arranged according to the aging times; extracting a time normalization electrochemical attenuation index and an aging form offset feature, forming a simplified input feature vector in combination with the key electrochemical feature value, and learning a corresponding relation between an electrochemical behavior and a stability level by using a stability sensitivity judgment model and an electroplating intermediate stability evaluation model; and outputting an electroplating intermediate stability prediction result according to the real-time electrochemical curve on a production site, and continuously updating the model in combination with the actual use condition.

A standard cell layout that may be implemented in FinFET devices or nanosheet FET devices is disclosed. The standard cell layout includes power supply connections from both a topside metal layer and a backside metal layer. A device in the standard cell may be connected to both the topside metal layer and the backside metal layer. Source / drain regions of the device may be connected the metal layers using via contacts within the standard cell layout. Connections to power supply rails from the topside metal layer and the backside metal layer may also be included in the standard cell layout. The rails may be connected to a power supply such that the power supply provides power to the device through both the topside and backside metal layers.

The invention discloses a viscoelastic boundary verification method, device and equipment based on isoparametric elements and a medium, and the method comprises the steps: building a three-dimensional geometric model of a target structure according to geometric dimensions and material attributes, discretizing the three-dimensional geometric model into initial three-dimensional subunits, and then building an initial finite element mesh model; after identifying a target boundary surface to be applied with an artificial viscoelastic boundary, assigning boundary parameters to obtain each three-dimensional subunit and form a finite element model; all the three-dimensional subunits are mapped to a standard unit through equal-parameter coordinate transformation, an equivalent stiffness coefficient matrix and an equivalent damping coefficient matrix are obtained through calculation and then stacked and assembled, and an overall stiffness matrix and an overall damping matrix are formed; and calculating displacement response data based on the overall stiffness matrix and the overall damping matrix. According to the embodiment of the invention, by introducing the isoparametric coordinate transformation, the irregular boundary form can be directly processed without introducing an additional boundary unit, and the calculation requirement of an actual complex engineering model is met.

The invention provides a circuit energy efficiency automatic optimization method. The method comprises the following steps: firstly, modeling a circuit gate-level netlist into a directed graph; extracting a key path by using a static time sequence analysis tool, and extracting a context sensing key sub-graph containing the path and a first-order neighborhood node of the path; thirdly, feature coding is conducted on the key sub-graphs through a graph neural network, and state vectors representing the local state of the circuit are generated; the state vector is input to a reinforcement learning policy network to decide a drive capability adjustment action for a particular standard cell. And the system modifies the netlist according to the action, calls the static time sequence analysis tool again to evaluate the modified performance, power consumption and area indexes, and generates a reward signal to iteratively optimize the strategy network. By constructing the closed-loop optimization process, the problems of low manual optimization efficiency and unbalanced power consumption and area balance are solved, automatic and intelligent collaborative optimization of circuit energy efficiency is realized, and the design quality and efficiency are remarkably improved.

The application discloses a circuit pre-training method and device based on a graph neural network and electronic equipment, comprising the following steps: for a large-scale circuit, a circuit network graph is constructed, a random walk road is generated, and the road is used as a sample for model training; a node2vec model is trained using the road sample; a model with the minimum loss function value is selected as an optimal model; and the optimal model is loaded, and representation vectors of all nodes are output and saved. In the application, the node2vec pre-training model of the graph neural network is used, the information of a long-distance standard unit is fully absorbed to absorb local circuit structure features, deep representation of nodes is automatically learned from the circuit structure, and tedious manual feature engineering is avoided, thereby providing high-quality representation vectors for a downstream model. The node representation learned by the node2vec model is a task-independent general feature, can be flexibly applied to various downstream tasks, and provides support for subsequent circuit analysis and optimization design work.

This invention relates to a single-event latch-up evaluation method for advanced process technologies, comprising: constructing a high-energy particle incident model using the Geant4 Monte Carlo simulation tool; constructing and calibrating a three-dimensional basic device model using the TCAD simulation tool; constructing a standard cell circuit containing parasitic effects, extracting the parasitic thyristor structure of the standard cell circuit, and identifying sensitive regions of the parasitic thyristor structure; performing transient effect simulation on the identified sensitive regions based on the high-energy particle incident model to confirm whether latch-up is triggered; introducing anti-latch-up hardening measures for the sensitive regions, and performing simulation verification on the hardened standard cell circuit under the high-energy particle incident model; if the hardened standard cell circuit does not trigger latch-up, the anti-latch-up hardening measures are deemed effective. This method provides a systematic and automated solution that can fundamentally characterize the complex parasitic effects of advanced devices.

The invention provides an efficient air heat exchanger of a heavy oil piston engine. The efficient air heat exchanger comprises a shell and a core body installed in the shell. The core body is formed by arranging a plurality of TPMS cells, the core body is divided into two regions which are not communicated by the curved wall surfaces of all the TPMS cells, the two regions are respectively a high-temperature region and a low-temperature region, the high-temperature region comprises a plurality of high-temperature runners which are communicated with one another, and the low-temperature region comprises a plurality of low-temperature runners which are communicated with one another; the high-temperature runners and the low-temperature runners are arranged in parallel at intervals, so that the high-temperature runners and the low-temperature runners are crossed and wound; on the basis of a standard cell, the TPMS cell used by the core body is stretched to be three times of the length of the standard cell in the length direction of the high-temperature runner / low-temperature runner, and the curved wall surface of the TPMS cell is biased, so that the volume ratio of the high-temperature runner to the low-temperature runner is changed from 1: 1 of the standard cell to 3: 1. The cooling device is used for cooling high-temperature compressed air at the outlet of the air compressor of the heavy oil piston engine and can reduce the flow resistance of high-temperature fluid.

The invention provides a design method and device of an integrated circuit, the integrated circuit and electronic equipment, and the method comprises the steps: distributing pins of a plurality of standard units to a plurality of nets in a net list according to a preset net design rule; the wire net is used for representing a logic connection relationship among the plurality of standard units; according to the initial net distribution proportion, determining a front net distributed on the front surface of the integrated circuit and a back net distributed on the back surface of the integrated circuit in the plurality of nets; the front wire net and the back wire net are different wire nets; the initial wire net distribution proportion is the number ratio of front wire nets to back wire nets in the integrated circuit; splitting the netlist into a front netlist and a back netlist; front nets are distributed in the front netlist, and back nets are distributed in the back netlist; and respectively wiring the front wire net and the back wire net. According to the invention, the process difficulty of an integrated circuit with a double-sided interconnection function can be reduced.

The application provides a semiconductor device, a preparation method, a memory and an electronic device. The semiconductor device comprises: a first semiconductor structure, a first isolation layer and a second semiconductor structure which are sequentially stacked along a first direction; wherein the first direction is perpendicular to the first isolation layer; the first semiconductor structure comprises at least one first standard unit, each first standard unit comprises two sub-units, and each sub-unit comprises two first transistors; the second semiconductor structure comprises at least one second standard unit, each second standard unit comprises two second transistors; a power supply track is located between the two first transistors of each sub-unit, and the power supply track is connected with a first source-drain structure of the first transistor; and a conductive channel is located in the second semiconductor structure, a first end of the conductive channel is connected with a power supply metal structure in the second semiconductor structure, and a second end of the conductive channel extends along the first direction and is connected with the power supply track through the first isolation layer.

The present invention relates to a circuit layout technique for automatically generating analog and hybrid signals, and in particular, to a modular MOS transistor layout structure having a standard cell, and a usage method. The objective of the present invention is to solve the problem of failing to realize automatic layout generation, placement and routing because existing automatically generated MOS transistor layouts lack a standard structure and therefore cannot be abutted. The main solution comprises an MOS transistor layout design for a standard cell-modular structure. Each standard cell includes two pieces of dummy polysilicon, a placement and routing boundary, a power supply rail and a ground rail, and is regular in terms of shape and size, can be abutted to the same type of standard cell in any direction, and can be recognized by an EDA tool, thereby adapting to the EDA tool and improving the placement efficiency. In addition, further provided in the present invention is a usage method. Automatic placement and routing is performed by means of an EDA tool. First, automatic placement and routing is performed on a circuit consisting of NMOS transistors, so as to form an NMOS module; then, automatic placement and routing is performed on a circuit consisting of PMOS transistors, so as to form a PMOS module; and finally, automatic routing is performed on a connection relationship between the two modules. Therefore, automatic generation of a circuit structure layout consisting of MOS transistors in analog and hybrid circuits is realized, thereby improving the layout generation efficiency.

This invention discloses a method for predicting standard cell transistor placement sequences based on a Transformer model, an electronic device, and a storage medium. Step 1: Construct training samples based on standard cell netlist information and corresponding existing placement results; train the placement model using these training samples to obtain a trained placement model. Step 2: Obtain the standard cell netlist information to be placed and the current placement MOS sequence, and construct the feature encoding of the current state. Step 3: Input the feature encoding of the current state and the decision space into the placement model to obtain the next standard cell transistor to be placed, and place it. Step 4: Repeat steps 2-3 until all standard cell transistors have been placed. This invention improves the efficiency, accuracy, and versatility of placement, while reducing design time and cost.

This invention discloses a high-speed, high-precision voltage descent monitoring circuit, solving the problem of accurate and timely monitoring of voltage descent phenomena in large-scale integrated circuits, belonging to the fields of digital integrated circuit design and power management. This invention provides an optimized design method for ring oscillator point circuits, using standard cell type, threshold, drive capability, and power consumption as variables to find the ring oscillator circuit design with the highest voltage sensitivity, improving the resolution of the voltage descent monitoring circuit; it provides a one-fold, compact ring oscillator layout design to ensure load balance between nodes; it provides a Nyquist counter design to count the number of times nodes flip over a period of time, improving the voltage monitoring range and solving the metastable sampling problem of traditional counters; and it provides a high-speed voltage quantization circuit that processes coarse and fine quantization in parallel, improving the maximum sampling rate and quantization rate of the voltage descent monitoring circuit.

A standard cell and an integrated circuit including the same are is provided. The standard cell is provided in first and second rows. The standard cell includes: a first circuit region provided in the first row and including a plurality of first transistors; a second circuit region provided in the second row and including a plurality of second transistors; a first input pin provided in the first circuit region and configured to receive a first input signal; and a second input pin provided in the second circuit region and configured to receive a second input signal. The first input signal is input to gate terminals of each of the plurality of first transistors, and the second input signal is input to gate terminals of each of the plurality of second transistors. The first circuit region is symmetric with respect to a second horizontal direction and the second circuit region is symmetric with respect to the second horizontal direction.

The application discloses an aging-aware precision reconfigurable logic synthesis method and system, and belongs to the technical field of integrated circuit EDA. The application aims to solve the problems of limited optimization space, introduced error from the beginning and lack of aging modeling in the existing aging-aware synthesis. The application constructs an aging standard cell library, iteratively applies constant replacement to the original circuit to generate multiple approximate candidate circuits, and then constructs a precision reconfigurable circuit composed of reconfigurable modules, which dynamically switches between accurate mode and approximate mode. Through aging-aware timing modeling, a power function model of gate delay with running time is established, and the aging continuity during mode switching is processed. The accurate mode life and the approximate mode remaining life are predicted, and the circuit with the highest score is automatically selected according to the score function. The application can improve the circuit life by about 9.5 times with an additional area overhead of about 3.72% under the premise of meeting the error constraint, which significantly enhances the long-term reliability of digital circuits.

1. The name of the design product: standard cell. 2. The use of the design product: standard cell is a kind of electromotive force standard device, which can save and transfer electromotive force standard. It can be used as a reference standard of potentiometer or for calibration of digital voltmeter. 3. The design points of the design product: in shape. 4. The picture or photo that best shows the design points: perspective view.

The invention discloses a standard cell library with various square resistance values, a manufacturing method and application thereof, and the manufacturing method comprises the following steps: designing a layout containing a plurality of standard cells, each standard cell being a minimum complete structure capable of independently reflecting a specific square resistance value, the layout comprises patterns of two metal silicide barrier layers arranged on the polycrystalline silicon surfaces of the standard units and a distance between the two metal silicide barrier layers, the distance is used for controlling the generation area of metal silicide, and the square resistance value of each standard unit is adjusted by adjusting the distance; a plurality of standard units are manufactured based on the layout, and the standard units form a standard unit library. On the premise of keeping the absolute advantages of simple process and low cost, the invention provides a standard cell library with various square resistance values, successfully realizes the manufacturing and flexible adjustment of the polycrystalline silicon resistor, and has extremely high application value.

The invention discloses a digital back-end netlist conversion and physical verification method and system, a computer and a medium, and the method comprises the steps: exporting a GDS file after layout and wiring from a digital back-end, and completing layout information by fusing standard unit data in a process design suite; exporting a Verilog netlist file from a digital back end; the Verilog netlist file is subjected to netlist format conversion, and a CDL file is obtained; manually calibrating the CDL file, and establishing electrical equivalence of the module-level power supply network and the standard power supply network; and configuring an LVS verification rule, using the calibrated CDL file as a schematic diagram netlist, using an SP netlist generated by the GDS as a layout netlist, explicitly setting a power supply network name, and finally executing LVS verification. According to the method, the electrical connection consistency of the CDL file and the GDS layout can be realized through a standardized power supply network naming mapping mechanism, the LVS verification passing rate is improved, and the manual debugging cost is reduced.

A semiconductor design system and a method for designing a semiconductor device using the system include a design tool configured to: determine a target circuit block to designed; select a standard cell configured to perform a function of the target circuit block; determine a detailed configuration of the target circuit block according to a power characteristic and an input / output characteristic of the target circuit block; based on circuit block information including the detailed configuration of the target circuit block, a device type to which the target circuit block is applied, and an integration location for the target circuit block, select an alt-standard cell among a plurality of alt-standard cells associated with the selected standard cell, for which the alt-standard cell has circuit block information that most closely matches the circuit block information for the target circuit block; and lay out the target circuit block by loading the selected alt-standard cell.

A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.

This invention proposes a voltage allocation method for a dual-track standard cell library, comprising: a sensitivity-based coarse cell replacement, which calculates the replacement sensitivity of each cell based on its delay and power consumption, and replaces some high-voltage cells in the circuit with low-voltage cells in descending order of replacement sensitivity, resulting in a target chip where the estimated delay margin value for each path is the minimum positive value; and a path-based fine cell adjustment, which classifies each path and the cells in each path in the target chip, and then performs cell replacement adjustment, eliminating timing violations while further reducing the occurrence of low-voltage cells driving high-voltage cells, resulting in a target chip where the accurate delay margin value for each path is the minimum positive value, while minimizing circuit power consumption.

A semiconductor die includes manually designed full-custom logic circuits implemented at transistor level and performing digital computation without use of standard-cell libraries or automated synthesis. The die lacks bond pads, wire-bond terminals, or through-silicon vias and operates only when bonded to another die or carrier through dense hybrid-bonded or microbump conductive interconnects. In related embodiments, a system includes such a compute die and a peripheral die providing power, clock, and communication functions. The architecture enables pad-less full-custom compute dies operating solely through inter-die bonding for all external connectivity.

A carbon-based standard unit circuit and integrated circuit includes at least one carbon nanotube transistor unit. The carbon nanotube transistor unit comprises two or more carbon nanotube transistors connected in series. Each carbon nanotube in the unit contains different carbon nanotubes, and all carbon nanotubes in the unit have the same carrier conductivity type. The gates of all carbon nanotube transistors are connected. By setting two or more carbon nanotube transistors connected in series within the same unit, the number of carbon nanotubes within the unit is increased. Since each carbon nanotube contains different carbon nanotubes but has the same carrier conductivity type, the carbon nanotubes in each unit exhibit different intrinsic material properties. This reduces the probability that all carbon nanotubes in the unit contain metallic carbon nanotubes, thereby reducing the probability of the carbon nanotube transistor unit malfunctioning.

An integrated circuit including a first standard cell placed continuously on a row having a first height and a row having a second height different from the first height. The integrated circuit also includes a second standard cell continuously placed on a row having the first height and a row having the second height, a plurality of first power lines formed on boundaries of the plurality of rows and configured to supply a first supply voltage to the standard cells, and a plurality of second power lines formed on boundaries of the plurality of rows and configured to supply a second supply voltage to the standard cells. A placement sequence of the power lines supplying a voltage to the first standard cell being different from a placement sequence of the power lines supplying a voltage to the second standard cell.