17results about How to "Reduce chip area" patented technology

The invention relates to a composite communication circuit which comprises a first register unit, a second register unit, a timer unit and a state machine circuit. The first register unit is electrically connected to the timer unit, receives a clock signal of the timer unit, and receives and stores external data; the second register unit is electrically connected with the first register unit, receives the data in the first register unit, stores the data and sends the data to the outside; the state machine circuit sends state signals to the first register unit, the second register unit and the timer unit; when the timer unit sends out an overflow signal, the first register unit, the second register unit and the timer unit carry out data processing. The circuit is flexible in configuration, the state machine circuit adjusts the working state of the circuit in real time, switching and combination of different communication protocols are achieved, and hardware resource waste caused by the fact that a traditional MCU supports multiple protocols is avoided.

This invention provides a circuit and method for sampling and transmitting telemetry data from a cochlear implant, belonging to the field of telemetry technology for cochlear implants. The method amplifies the analog signal under test using a programmable gain amplifier, converts the signal into a pulse width signal using a voltage ramp generator and comparator, and then generates a short-duration step signal on the coil via an output driver to form a ringing pattern. An external device detects the interval between the step signals to reconstruct the signal magnitude. This invention eliminates the need for an analog-to-digital converter, significantly reducing power consumption and chip area, and improving data transmission efficiency. It is suitable for telemetry systems in various implantable medical devices such as cochlear implants. This invention significantly reduces the power consumption and layout area of ​​the implanted chip and shortens the single data transmission time to 48μs, improving efficiency by approximately 10 times, making it suitable for low-power implantable devices such as cochlear implants.

The invention discloses a time-to-digital converter based on a vernier double-chain structure, and relates to the technical field of integrated circuits. The converter comprises a signal holding circuit, a vernier double-chain rough measurement module, a data selector, a special time amplifier module and a digital coding unit, the vernier double-chain rough measurement module is composed of a main delay chain and a vernier delay chain, and 10ps-level rough measurement is achieved by adjusting the width-to-length ratio of an MOS tube of a phase inverter to control the delay difference of a unit. The data selector gates a residual time difference signal to the special time amplifier module, and the special time amplifier module is matched with a transmission gate through an RC network to realize 11mV / ps high-linearity time-voltage conversion; the digital coding unit integrates the rough measurement result and the accurate measurement result, and finally the 3.0 ps system resolution is achieved. A'rough measurement-fine measurement 'two-stage measurement architecture is adopted, a single-amplifier time division multiplexing design is adopted, a measurement dead zone is effectively eliminated, the chip area and power consumption are greatly reduced, and the device is particularly suitable for high-precision time measurement application such as laser radar and quantum calculation.

The present invention provides an analog-to-digital conversion circuit and an image sensor, wherein a ramp generator outputs a ramp voltage, wherein the ramp voltage decreases at a preset rate over time; a plurality of comparators are electrically connected to a column circuit of a pixel array and the ramp generator, wherein the pixel voltage of the column circuit is input to an inverting input terminal of the comparator, and the ramp voltage is input to a non-inverting input terminal of the comparator; a comparator bias circuit is electrically connected to the comparator, and provides a first bias voltage and a second bias voltage to the comparator, wherein the comparator completes the comparison between the ramp voltage and the pixel voltage under the first bias voltage and the second bias voltage; and a plurality of counters, wherein the counters are electrically connected to the comparators, and the counters count the number of flips of a system clock signal until the ramp voltage drops to be equal to the input of the pixel voltage; wherein when the ramp voltage and the pixel voltage are equal, the output of the comparator flips, and the flip of the output of the comparator triggers the flip of an enable signal of the counter, and the counter stops counting.

A switchable combiner and / or splitter circuit comprising at least two Wilkinson elements is suggested. The switchable circuit comprises one first terminal and for each Wilkinson element one pair of second terminals associated with the corresponding Wilkinson element. Each Wilkinson element connects the first terminal with the associated pair of second terminals. Each Wilkinson element includes a switchable component enabling selectively activating the associated pair of second terminals. The proposed solution combines a Single-Pole-Double-Through switch and a Wilkinson element and, thus, reduces the chip area required for integrating the circuit.

The present application relates to an in-memory calculation method for floating-point numbers, an in-memory calculation architecture, and an in-memory calculation chip, the in-memory calculation method comprising: calculating the inference accuracy loss of a target convolutional neural network for a test set under different convolution magnitude combinations, the target convolutional neural network being used to extract feature information from an image through multiple convolution operations; determining a convolution magnitude combination as a target convolution magnitude combination from at least one convolution magnitude combination corresponding to a loss of inference accuracy less than a target value, the target convolution magnitude combination comprising a reference magnitude for each convolution operation; for any convolution operation of the target convolutional neural network, the corresponding reference magnitude is used to implement floating-point number calculations for the convolution operation. The present invention obtains a reference magnitude adapted to the target convolutional neural network through testing in advance at the software network level. This not only improves the in-memory calculation efficiency of floating-point numbers, but also reduces the chip area and power consumption of the memory.

The embodiment of the present invention relates to the field of electronic technology, and discloses a radio frequency amplification module and a communication terminal. In the present invention, the radio frequency amplification module includes: an input balun, an output balun and a power amplifier module; the input balun and the output balun are implemented by an integrated passive device process; the power amplifier module is arranged on a substrate, and the input balun is electrically connected to the output balun through the power amplifier module. The input balun and the output balun of the present invention are implemented by an integrated passive device process, so that the cost of the radio frequency amplification module is reduced, and the processing technology of the integrated passive device process is more refined, and the area of ​​the integrated balun module can be made very small, which ultimately reduces the area of ​​the radio frequency amplification module.

The present invention discloses a RAID engine and a RAID bridge chip. In order to reduce the design and integration difficulty of the off-chip memory to the bridge chip, the RAID engine of the present invention includes an on-chip memory; data is transmitted between the RAID processor and the on-chip memory through a first data interface; data is transmitted between the SATA core and the on-chip memory through a second data interface. The present invention solves the technical problem of high difficulty in designing and integrating the bridge chip, reduces the chip design and integration difficulty in the bridge chip, and avoids the cost of the off-chip memory. The present invention is suitable for the field of integrated circuits.

The disclosure provides an arbitrarily bendable metasurface waveguide structure and a design method thereof. The metasurface waveguide structure comprises a plurality of bendable structure units arranged without gaps in sequence, which are obtained by conformal transformation of linear structure units. The linear structure unit comprises a first dielectric column and two second dielectric columns, which are symmetrically arranged on both sides of the first dielectric column and form a circular arc interface. The bending radius and bending angle of the metasurface waveguide structure can be arbitrarily adjusted, and the equivalent refractive index can be kept unchanged after bending. Further, by adjusting the height, length, width, major axis and minor axis of the bendable structure unit, the metasurface waveguide structure can have lower transmission loss. The disclosure can improve the degree of freedom of the metasurface waveguide and realize more complex structures and devices on a chip.

A chip having integrated thereon a circuit (100) that comprises a first port (P1), a second port (P2) and a tapped transformer (110) comprising a first winding (111) and a second winding (112). Each winding comprises a first terminal, a second terminal and a number of taps connected at different positions between the first and second terminals. The circuit (100) further comprises a first programmable capacitor (C1) connected in shunt with the first winding (111) and a second programmable capacitor (C2) connected in shunt with the second winding (112), a first set of switches (S1) connected between the number of taps on the first winding (111) and a terminal of the first port (P1), and a second set of switches (S2) connected between the number of taps on the second winding (112) and a terminal of the second port (P2).

The invention relates to an in-memory calculation method, an in-memory calculation architecture and an in-memory calculation chip of a floating-point number, and the in-memory calculation method comprises the steps: calculating the inference precision loss of a target convolutional neural network for a test set under different convolution magnitude combinations, the target convolutional neural network being used for extracting feature information from an image through multiple convolution operations; determining one convolution magnitude combination as a target convolution magnitude combination in the convolution magnitude combinations corresponding to the at least one inference precision loss smaller than the target value, wherein the target convolution magnitude combination comprises the reference magnitude of each convolution operation; and for any convolution operation of the target convolutional neural network, floating-point number calculation of the convolution operation is realized by adopting the corresponding reference magnitude. According to the method, the reference magnitude adaptive to the target convolutional neural network is obtained in advance through testing on the software network level; the in-memory calculation efficiency of the floating-point number is improved, and the chip area and the power consumption of the memory are reduced at the same time.

The invention provides a filter shaping circuit applied to an enable port, a low dropout regulator and a power management unit, and relates to the technical field of integrated circuit design, the output end of a first phase inverter is connected with the input end of a NOR gate, and the grid electrode of a second NMOS tube is connected with the input end of a NAND gate through a second phase inverter; the grid electrode of the first NMOS tube is connected with the output end of the NOR gate, and the drain electrode is connected with power supply voltage through a grid voltage adjusting circuit; the drain electrode of the second NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode and the grid electrode of the first PMOS tube are respectively connected with a power supply voltage and a grid voltage adjusting circuit; two ends of the charging and discharging device are respectively connected with a power supply voltage and a drain electrode of the first PMOS tube; the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube and connected with the grid electrode of the third NMOS tube through a third phase inverter. The output end of the third inverter is connected with the input end of the NOR gate and the input end of the NAND gate. The beneficial effect is that burr signals are effectively filtered.

The invention provides an in-situ light sensing probability calculation system and a photoelectric hybrid calculation method thereof.The system comprises a light signal projection front end, a photoelectric probability bit array, a driving module, a reading module and a micro-control unit which are tightly coupled, and the photoelectric probability bit array comprises a plurality of photoelectric probability bit units; the driving module comprises a decoder and a grid voltage generator, the reading module comprises a comparator group and a reference voltage source corresponding to the comparator group, and the micro-control unit is a digital logic circuit; the photoelectric sensing function and the probability calculation function are integrated in the same unit, an optical signal serves as external excitation to directly determine the initial activation probability of neurons, in-situ loading of image data is achieved, an electric signal serves as internal excitation to bear weight and bias information, the voltage of an electric control grid is adjusted, and operation updating of a neural network is achieved; the method realizes direct conversion from light intensity to random bit stream, has ultrahigh photoelectric sensitivity and true randomness, and is suitable for high sensitivity of probabilistic reasoning in a complex environment.

The present invention relates to a multi-cell lithium battery voltage detection circuit, the detection circuit comprises a high-precision comparator, two groups of split capacitors, a control switch and a lithium battery pack, the lithium battery pack is formed by connecting m (m≥2) lithium batteries in series, wherein the lithium battery pack is connected to the positive input end of the high-precision comparator through a group of split capacitors, and the high-precision basic voltage of the circuit content is connected to the negative input end of the high-precision comparator through another group of split capacitors.

The invention discloses a load current calculation device for a SIMO DC converter. The system includes a current sensor, an averaging circuit and an output current integrator. The current sensor mirrors the transient current of a pull-up switch tube S_HS and outputs a sensing voltage Vsen, which is proportional to the inductor current IL during the S_HS conduction time; the averaging circuit first samples the peak value and the valley value of Vsen respectively, and then adds the two to obtain an average sensing voltage Vsen_avg, which is proportional to the average inductor current; the output current integrator multiplies Vsen_avg with each output tube control signal PWM<1:n> respectively to calculate the equivalent voltage VC<1:n> of each load current, and VC<1:n> is proportional to each load current Iload1‑n. Different from the traditional multi-channel output current sensing technology (each channel is connected in series with a sensing resistor or each channel uses a current mirror detection circuit), the device of the present invention can use the pull-up tube current (required for current mode converter) and the output power tube control signal to directly calculate the output load current of each channel. It has a simple structure and reduces the chip area without affecting the efficiency of the converter.

The application provides a level conversion circuit for converting from a high level to a low level, the level conversion circuit comprising: a voltage dividing circuit configured to divide an input voltage to output an output voltage from an output node; an acceleration circuit configured to quickly switch the output voltage when the input voltage switches by quickly switching a first transistor to be turned on through a first capacitor; and a clamping protection circuit configured to prevent the output voltage from jumping up when the input voltage switches.

The application relates to a radio frequency switch unit, a radio frequency switch circuit, an integrated circuit chip and an electronic device. The radio frequency switch unit comprises a first inductor pair, a first switch module, a second switch module and a first absorption circuit, the first inductor pair comprises a first inductor and a second inductor, a first end of the first inductor is connected with a first node, a second end of the first inductor is connected with a second end of the second inductor, a first end of the second inductor is connected with a second node; a first end of the first switch module is connected with the second end of the first inductor and the second end of the second inductor, a second end of the first switch module is grounded; a first end of the second switch module is connected with the second node, a second end of the second switch module is connected with a first end of the first absorption circuit, a second end of the first absorption circuit is grounded; and the first absorption circuit comprises a first resistor and a first capacitor in parallel. Through the embodiment of the application, the chip area occupied by the radio frequency switch unit can be small, and the chip cost can be reduced.