196results about How to "Reduce chip area" patented technology

A multi-chip module is implemented by connecting a plurality of connection pads provided on, for example, two semiconductor chips via a plurality of conductive connecting members. To carry out a test for determining the quality of the connection between the two semiconductor chips, the multi-chip module is further provided with a plurality of switch elements so that the plurality of connecting members can be electrically conducted in a serial manner via the connection pads of the semiconductor chips. During the connection test, all the switch elements are turned on, and the impedance between both ends of the line including the plurality of connecting members conducted in a serial manner is measured using two probing pads.

An exemplary embodiment of the present disclosure illustrates a method for auto-refreshing memory cells in a semiconductor memory device with an open bit line architecture, wherein the semiconductor memory device comprises M memory banks, and each of the M memory banks has two particular sectors with a same index and L remained sectors with different indices. Two word lines of the two particular sectors with the same index in the memory bank and (M−1) word lines of the L remained sectors respectively in the other (M−1) memory banks are selected in one cycle. Then, memory cells of the selected word lines are refreshed.

A multi-word line refresh-type semiconductor device may have a plurality of memory banks and performs a refresh operation simultaneously with respect to a plurality of word lines for each of the banks in a self-refresh mode. The semiconductor device includes an address controller for receiving a normal address and a refresh address and selectively outputting the received refresh address in a refresh mode, a fuse circuit for receiving the refresh address, determining whether the received refresh address corresponds to a word line to be repaired and outputting a redundancy word line enable signal and a first control signal according to a result of the determination, a first signal generator for, in response to a bit value for block selection of the refresh address and the first control signal, outputting a second control signal which defines a multi-word line refresh period, a refresh address generator for generating the refresh address in response to the second control signal, and a row controller for receiving the refresh address, second control signal and redundancy word line enable signal and controlling the refresh operation with respect to a memory core.

The invention provides a miniaturized MEMS switch-line phase shifter, comprising an MEMS switch, a reference phase shifting transmission line, a phase delay transmission line, a switch offset line, a back surface grounding layer, a medium liner, a microwave grounding terminal, and a micro-mechanical through hole. The invention has the advantages of keeping low insertion loss of a transmission passage and reducing the chip area of a large phase shifting unit bit transmission line of the phase shifter by distribution-typed elements with high resistance and a phase delay transmission network formed by the microwave grounding of a collecting element and the micro-mechanical through hole, reducing the chip area of a small phase shifting unit bit delay line of the phase shifter, reducing the area of the chip, minimizing the chip area occupied by the MEME switch by selecting miniaturized MEMS switches such as a built-in cantilever MEMS switch, keeping the broad band performance of the MEMS switch and the phase shifter and minimizing the chip area occupied by the MEMS switch offset circuit by separating a microwave signal from a switch driving signal, and leading to simple and convenient design of microwave grounding of the chip and reducing the area of the chip to the most extent by the micro-mechanical through hole technology.

An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.

Stacked capacitor memory is realized, wherein a capacitor stores data and a diode serves as an access device instead of MOS transistor, the first terminal is connected to a word line, the second terminal is connected to the first electrode of the capacitor which serves as a storage node while the second electrode is connected to a plate line, the third terminal is floating, and the fourth terminal is connected to a bit line. When write, the storage node is charged or not, depending on the conducting state of the diode which is controlled by the bit line. When read, the diode also serves as a sense amplifier to detect whether the storage node is forward bias or not, and it sends binary data to a latch device wherein includes a current mirror and a feedback loop which cuts off the current path after latching, thus it reduces active current, minimizes data pattern sensitivity, and also rejects coupling noise. And dummy rows and columns generate replica delay signals which guarantee timing margin and reduce cycle time. And its applications are extended to single port, multi port and content addressable memory. In addition, the memory cells are formed in between the routing layers, which memory cells can be stacked over the transistor or another capacitor memory cell.

Disclosed is a dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

System and method for routing data packets in an Ethernet switch. A preferred embodiment comprises receiving a data frame at a first port, wherein the data frame comprises a header portion and payload portion. The header portion is analyzed to determine a destination port for the data frame. A destination status is added to the header portion to create a modified header portion. The modified header portion is stored in an on-chip memory. The payload portion is stored in an off-chip memory. An on-chip CPU instructs a DMA controller how to route the data frame.

An object is to provide a semiconductor device mounted with memory which can be driven in the ranges of a current value and a voltage value which can be generated from a wireless signal. Another object is to provide write-once read-many memory to which data can be written anytime after manufacture of a semiconductor device. An antenna, antifuse-type ROM, and a driver circuit are formed over an insulating substrate. Of a pair of electrodes included in the antifuse-type ROM, the other of the pair of the electrodes is also formed through the same step and of the same material as a source electrode and a drain electrode of a transistor included in the driver circuit.

The power IC includes an output transistor MO which controls a current flowing into an L load, a dynamic clamp circuit which clamps an overvoltage, and a clamp control circuit which controls the operation of the dynamic clamp circuit. The clamp control circuit activates the dynamic clamp circuit, which is normally inactive, upon detection of a back EMF by the L load.

Logic circuits that support the addition of three binary numbers using hardwired adders are described. In one embodiment, this is accomplished by using a 3:2 compressor (i.e., a Carry Save Adder method), using hardwired adders to add the sums and carrys produced by the 3:2 compression, and sharing carrys data calculated in one logic element (“LE”) with the following LE. In such an embodiment, with the exception of the first and last LEs in a logic array block (“LAB”), each LE in effect lends one look-up table (“LUT”) to the LE below (i.e., the following LE) and borrows one LUT from the LE above (i.e., the previous LE). The LUT being lent or borrowed is one that implements the carry function in the 3:2 compressor model. In another aspect, an embodiment of the present invention provides LEs that include selectors to select signals corresponding to the addition of three binary numbers mode.

The invention discloses an infrared focal plane array detector unit with a non-uniform correction function, an infrared imaging system and a non-uniform correction method thereof. The infrared focal plane array detector unit comprises a pixel and a blind pixel which are made of the same thermistor material; the pixel responds to incident infrared radiation, while the blind pixel does not respond to the incident infrared radiation; the pixel and the blind pixel are connected in series, and are electrically connected with the inverted input end of an integrated amplifier, and the other end of the blind pixel, which is opposite to the end electrically connected with the pixel, is electrically connected with a compensating blind pixel; like the blind pixel, the compensating pixel does not respond to the incident infrared radiation; and the compensating pixel is used for compensating the blind pixel and indirectly compensating and correcting the nonuniformity of the corresponding pixel. The invention can effectively compensate the nonuniformity of the resistance of the pixel, thus broadening the dynamic range of the effective output of a focal plane array and decreasing noise-equivalent temperature difference.

A highly integrated DRAM is provided. A circuit for driving a memory cell array is formed over a substrate, a bit line is formed thereover, and a semiconductor region, word lines, and a capacitor are formed over the bit line. Since the bit line is located below the semiconductor region, and the word lines and the capacitor are located above the semiconductor region, the degree of freedom of the arrangement of the bit line is high. When an open-bit-line DRAM is formed, an area per memory cell less than or equal to 6F², or when a special structure is employed for a cell transistor, an area per memory cell less than or equal to 4F² can be achieved.

A method of fabricating an electrical guard structure for providing signal isolation is provided. The method includes providing a substrate having a mounting surface comprising a first area for hosting at least one electronic component. The method further comprises synthesizing a plurality of thread-like structures over the substrate to collectively form one or more electrically conductive projections extending transverse to the mounting surface. The one or more electrically conductive projections include one or more wall-like structures which are elongate parallel to the mounting surface. The electrically conductive projections can be transferred to another surface such as a major surface of a second substrate. There are further provided a support structure and a guard structure having the wall-like electrically conductive projections which are electrically grounded when in use to provide signal isolation.

A reflex coupler has an organic light emitter for generating a light signal and an inorganic photodetector with a detector area. The organic light emitter and the detector area are optically coupled as a result of radiation returned from an object onto which the light signal impinges, and the organic light emitter and the inorganic photodetector are integrated in one device.

The invention relates to a phase-locked loop circuit including a phase detector, loop filter and an oscillator. The loop filter is implemented digitally instead of by means of analog components. The chip area required for such a digital loop filter is substantially smaller than an analog equivalence and can be implemented on a single integrated circuit die together with an oscillator, phase detector and possible counters. There is thus no need for the use of external components, greatly simplifying the design and manufacture of the circuit, and having reduced assemblage costs. Further, by means of the digital filter the loop dynamics are also easily changed.

A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to ''a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.

In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire and the lower cell power-supply wire are connected by two vias. The supplementary power-supply wire and the upper power-supply wire are connected by a single via. Current from the supplementary power-supply wire is divided by the two vias and then supplied to the lower cell power-supply wire. Therefore, when power is supplied from the upper power-supply wire to the lower cell power-supply wire, current concentration at the connection points of the lower cell power-supply wire to the vias is decreased, thereby reducing wire breaks caused by EM (electro migration).

An integrated RF front-end circuit comprising a balun, a receiver amplifier, a power amplifier, and a selector circuit is provided. The balun comprises a center-tapped inductor having a first node, a center-tap switchlessly coupled to a fixed voltage, and a second node. The balun receives a single-ended signal through the first node to produce a differential signal at the first and second nodes. The differential signal is provided to balanced input lines of the receiver amplifier. Balanced output lines of the power amplifier provide a differential signal to the first and second nodes. The balun converts the differential signal to a single-ended signal. The single-ended signal is available at the first node of the center-tapped inductor. The selector circuit activates the receiver amplifier and deactivates the power amplifier, and vice versa. The power amplifier may comprise only a single-ended output line connected to either the first or the second node.

A low-differential-loss low-phase-shift high-integration-level five-level marching type ultra-wide-band numerical control attenuator is formed by a single signal channel which comprises a transmission line TL0, an 8dB attenuation module of a pai-type structure, an inductor L1, a 0-7dB combined attenuation module of a T type-bridge T type combined structure, an inductor L2, a 16dB attenuation module of a pai-type structure and a transmission TL1 in a cascaded mode in sequence based on the RF CMOS technology. An MOS tube is used as a control switch, five independent control ends controls three attenuation modules to work, an inducting network is used for phase compensation, working frequency range is Ku wave band within the attenuation range of 0-31 dB with marching length of 1dB, and 32-state low-differential-loss low-phase-shift signal amplitude attenuation can be achieved. The attenuator has the advantages of being low in differential loss, low in additional phase shift, low in production cost, small in chip area and compatible with a digital processing module, and the attenuator can be used for single-chip ultra-wide-band communication system integration.

The invention discloses a SAR ADC adopting a low resolution DAC capacitor array and an application method thereof. The ADC comprises two DAC arrays, three preamplifiers, five comparators and a SAR control logic circuit. An interpolation structure is arranged between the two DAC arrays. Compared to the prior art, by using the ADC in the invention, one interpolation comparator is inserted between the two adjacent preamplifiers so that the number of capacitance digital-analog arrays can be reduced. A solution scheme of weighing a bandwidth and the resolution is provided for a multi-bit/periodic SAR ADC. By using the ADC and the method, there are the following advantages that for a high-precision SAR ADC design, usage of a large-scale DAC array can be avoided so that a capacitor DAC array only needs to satisfy thermal noise restraining demand.

An integrated circuit (IC) with high electron mobility transistors, such as enhancement mode pseudomorphic high electron mobility transistors (E-pHEMTs) and method for fabricating the IC utilizes an increased gate-to-drain etch recess spacing in some of the high electron mobility transistors to provide on-chip electrostatic discharge protection. The use of the increased gate-to-drain etch recess spacing allows smaller high electron mobility transistors to be used for ancillary low speed applications on the IC, which reduces the chip area occupied by these ancillary transistors.

A radio-frequency CMOS low noise amplifier of dual-band inductance multiplexing belongs to the technical field of radio-frequency low noise amplifiers. Based on a dual-band low noise amplifier in the prior art, the pattern of amplifying a 5.2 GHz signal is changed into a common-gate amplification mode; an inductor is dislodged; a 5.2 GHz enable circuit consisting of MOS transistors is added; and a 5.2 GHz output signal is output from a 5.2 GHz signal output terminal separated from a 2.4 GHz signal output terminal. The amplifier has the advantages of low noise, low power consumption, small area and the like, and is especially suitable for serving as a front-end amplifier in a wireless communication device.

The invention provides a method for storing hybrid automatic repeat request (HARQ) data, the method including: when receiving new data of a coded block, a HARQ processor writing the new data into a high rate buffer memory (Cache) and a channel decoder; the Cache writing the new data into a data memory of the Cache or an external memory; and when receiving retransmitted data of the coded block, the HARQ processor obtaining a previous data corresponding to the retransmitted data from the data memory of the Cache or the external memory through the Cache, combining the retransmitted data and the previous data, and writing the combined data to the Cache and the channel decoder; the Cache writing the combined data into the data memory of the Cache or the external memory. The invention also provides a HARQ combiner.

The present invention discloses a universal serial bus (USB) control circuit, and more particularly, a USB control circuit with an automatic route-switching function. The USB control circuit comprises: a plurality of USB pads, connecting a plurality of USB devices; a plurality of USB transceivers, each connected to a corresponding USB pad; at least one USB controller, each connected to at least one corresponding USB transceivers, so as to control and drive the USB devices connected to the corresponding USB pads by using the corresponding USB transceivers; a plurality of port routing controllers, each connected to a corresponding USB transceiver; at least one enhanced USB transceivers, each connected to each of the USB pads and each of the port routing controllers; an enhanced USB controller, connected to each of the enhanced USB transceivers, so as to control and drive the enhanced USB devices connected to the corresponding USB pads by using the corresponding enhanced USB transceivers; and an enhanced device routing controller, connected to each of the port routing controllers, so as to automatically switch a USB pad that connects enhanced USB devices to the enhanced USB transceivers to be controlled by the enhanced USB controller.

The invention relates to a BCD semiconductor device and a manufacturing method thereof. The BCD semiconductor device comprises a high voltage nLIGBT device (1), a first type of high voltage nLDMOS device (2), a second type of nLDMOS device (3), a third type of nLDMOS device (4), a low voltage NMOS device (5), a low voltage PMOS device (6) and a low voltage NPN device (7), wherein n-type drift region wells (21, 22) of the high voltage nLIGBT device (1) and of the first type of high voltage nLDMOS device (2) are respectively introduced with n-type heavily-doped layers (201, 202), and p-type reduced-field layers (301, 302) are respectively arranged below the n-type heavily-doped layers (201, 202) and are surrounded by the n-type drift region wells (21, 22). A smaller conduction resistance is realized while chip areas are the same, or a smaller chip area is realized while conduction capabilities are the same. The BCD semiconductor device has advantages of simple manufacturing method and relatively less difficult technology.

The invention relates to the design field of chips and particularly discloses an image enhancement processing system and method based on a camera image processing chip. When a large-sized image is treated, image data is firstly uploaded to a system memory, then dividing along a line direction according to a back level processing capability and dividing a frame of large-sized image into a plurality of smaller images with equal height, wherein each line block is matched with synchronization signals so as to form isolated virtual frames; and then corresponding image enhancement treatment is implemented to each virtual frame. Trough the method for changing the chip area by time, the size of the module level cache can be greatly reduced, the chip area can be decreased and the design cost of the chip can be reduced.

Timing difference division circuit with a high operating speed and a small area, assuring broadband operation. The circuit includes a logic circuit L1 generating a first gate signal and a second gate signal based on a first input signal and a second input signal, a first switch element connected across a first power source and an inner node and having a control terminal to which is fed the first gate signal, a first series circuit made up of a second switch element and a first constant current source and a second series circuit made up of a third switch element and a second constant current source. The first and second series circuits are connected in parallel across the inner node and the second power source. The first and second gate signals are connected to control terminals of the second and third switches, respectively. The circuit also includes a plurality of MOS capacitors, connection of which to the inner node is separately controlled by a control signal, and a buffer circuit an input end of which is connected to the inner node and the value of an output signal of which is determined based on the relative magnitude of the potential of the inner node and a threshold voltage. An overlap period during which the first and second gate signals output from the logic circuit are both activated to turn on the second and third switch elements is set to an optional value.

In the present invention, one-time programmable memory includes a diode as an access device and a capacitor as a storage device, the diode includes four terminals, wherein the first terminal is connected to a word line, the second terminal is connected to one plate of the capacitor, the third terminal is floating, and the fourth terminal is connected to a bit line, and the capacitor includes two electrodes, wherein one of the capacitor plate serves as a storage node which is connected to the second terminal of the diode, and another plate of the capacitor is connected to a plate line, and the plate line is asserted to programming voltage which is higher than the regular supply voltage of the decoders and data latches, in order to breakdown the insulator of the capacitor when programming, but the plate line is connected to the regular supply voltage when read. And during read, the diode also serves as a sense amplifier to detect whether the storage node is forward bias or not, and it sends binary data to a latch device wherein includes a current mirror and a feedback loop, which cuts off the current path after latching. And dummy columns generate replica delay signals which guarantee timing margin and reduce cycle time. In addition, the memory cells are formed in between the routing layers, which memory cells can be stacked over the transistor or another capacitor memory cell.