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196results about How to "Reduce chip area" patented technology

Miniature MEMS switching line phase shifter

ActiveCN101202369ALow insertion loss performanceReduce chip areaWaveguide type devicesAntennasHigh resistanceEngineering
The invention provides a miniaturized MEMS switch-line phase shifter, comprising an MEMS switch, a reference phase shifting transmission line, a phase delay transmission line, a switch offset line, a back surface grounding layer, a medium liner, a microwave grounding terminal, and a micro-mechanical through hole. The invention has the advantages of keeping low insertion loss of a transmission passage and reducing the chip area of a large phase shifting unit bit transmission line of the phase shifter by distribution-typed elements with high resistance and a phase delay transmission network formed by the microwave grounding of a collecting element and the micro-mechanical through hole, reducing the chip area of a small phase shifting unit bit delay line of the phase shifter, reducing the area of the chip, minimizing the chip area occupied by the MEME switch by selecting miniaturized MEMS switches such as a built-in cantilever MEMS switch, keeping the broad band performance of the MEMS switch and the phase shifter and minimizing the chip area occupied by the MEMS switch offset circuit by separating a microwave signal from a switch driving signal, and leading to simple and convenient design of microwave grounding of the chip and reducing the area of the chip to the most extent by the micro-mechanical through hole technology.

Timing difference division circuit and signal controlling method and apparatus

Timing difference division circuit with a high operating speed and a small area, assuring broadband operation. The circuit includes a logic circuit L1 generating a first gate signal and a second gate signal based on a first input signal and a second input signal, a first switch element connected across a first power source and an inner node and having a control terminal to which is fed the first gate signal, a first series circuit made up of a second switch element and a first constant current source and a second series circuit made up of a third switch element and a second constant current source. The first and second series circuits are connected in parallel across the inner node and the second power source. The first and second gate signals are connected to control terminals of the second and third switches, respectively. The circuit also includes a plurality of MOS capacitors, connection of which to the inner node is separately controlled by a control signal, and a buffer circuit an input end of which is connected to the inner node and the value of an output signal of which is determined based on the relative magnitude of the potential of the inner node and a threshold voltage. An overlap period during which the first and second gate signals output from the logic circuit are both activated to turn on the second and third switch elements is set to an optional value.

One-time programmable memory

In the present invention, one-time programmable memory includes a diode as an access device and a capacitor as a storage device, the diode includes four terminals, wherein the first terminal is connected to a word line, the second terminal is connected to one plate of the capacitor, the third terminal is floating, and the fourth terminal is connected to a bit line, and the capacitor includes two electrodes, wherein one of the capacitor plate serves as a storage node which is connected to the second terminal of the diode, and another plate of the capacitor is connected to a plate line, and the plate line is asserted to programming voltage which is higher than the regular supply voltage of the decoders and data latches, in order to breakdown the insulator of the capacitor when programming, but the plate line is connected to the regular supply voltage when read. And during read, the diode also serves as a sense amplifier to detect whether the storage node is forward bias or not, and it sends binary data to a latch device wherein includes a current mirror and a feedback loop, which cuts off the current path after latching. And dummy columns generate replica delay signals which guarantee timing margin and reduce cycle time. In addition, the memory cells are formed in between the routing layers, which memory cells can be stacked over the transistor or another capacitor memory cell.
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