105 results about "Timing margin" patented technology

Die or chip interconnect clock skew compensation can be performed for a multi -IC (Integrated Circuit) module. A timing margin or eye-width parameter (for example, a setup or hold time) for each of one or more interconnect lanes may be measured at a first die or chip of the multi - IC module that is receiving data and clock signals from a second die or chip of the multi -IC module. Compensation information can be determined based on the measured timing margin or eye-width parameter for each of one or more interconnect lanes. Compensation for clock skew can then be based on the determined compensation information.

Various solutions for physical random access channel (PRACH) timing advance operation and PRACH configurations with respect to user equipment and network apparatus are described. An apparatus may determine a propagation delay between the apparatus and a network node. The apparatus may determine a pre-compensation timing margin. The apparatus may perform a timing advance pre-compensation according to the propagation delay and the pre-compensation timing margin. The apparatus may transmit an uplink signal by applying the timing advance pre-compensation.

Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an integrated circuit has a logic path formed in the integrated circuit. A monitor circuit is formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to determine a condition of the integrated circuit based on the diagnostic code sequence, and to initiate a remedial action in response to the condition of the integrated circuit.

The invention discloses a time sequence convergence method and device based on a clock tree, and relates to the technical field of circuit design. The method comprises the following steps: performing automatic layout on devices; determining a time sequence path needing to be optimized in the one-to-many structure time sequence path; performing establishment time sequence margin optimization, and determining a setting pattern of useful clock skew adjustment based on the optimized establishment time sequence margin; determining the number of buffers based on the setting pattern of useful clock skew adjustment and the optimized setup time sequence margin, and generating a clock tree; on the basis of the generated clock tree, determining whether the time sequence violation of the retention time of the time sequence path needing to be optimized meets a preset requirement or not, and if the preset requirement is not met, adjusting the setting pattern of the useful clock skew adjustment, and returning to the step of generating the clock tree; and completing automatic wiring based on the clock tree meeting the predetermined requirement. According to the invention, the problem of power consumption increase caused by restoration of Hold time sequence violation can be solved.

The invention relates to the technical field of integrated circuits, and provides a self-adaptive frequency modulation and voltage regulation chip control circuit and method, the circuit comprises a time sequence monitoring module which comprises a critical path replication sub-module and a daisy chain delay sub-module which are connected, and the critical path replication sub-module is used for simulating an actual critical data path in a chip; the daisy chain delay sub-module is used for applying a configurable delay amount on a time sequence to the output data signal; the time sequence performance after different time points is simulated; the first trigger is used for transmitting data signals; the sampling trigger module is used for sampling the data signal output by the time sequence monitoring module; the comparison logic module is used for generating a multi-bit time sequence margin indication code according to a comparison result; the time sequence margin indication code is used for adaptively adjusting the working frequency or the working voltage of the chip. According to the invention, through accurate monitoring and self-adaptive adjustment of a chip time sequence, all design margins can be utilized, and the energy utilization efficiency is improved, so that extreme low power consumption is realized.

The invention discloses a time sequence optimization method and device for clock tree synthesis and a computer readable storage medium, belongs to the field of chip design, and aims to solve the problem that register omission can be avoided by analyzing receiving registers as objects one by one, and time sequence optimization is performed according to violation degree evaluation value sorting of the receiving registers. According to the method and the device, omission of violation paths with deep violation degrees can be avoided, so that the sum of the time margins of the violation paths containing the receiving register can be determined as the violation degree evaluation value of the receiving register for any receiving register in the target chip; according to the sequence of absolute values of violation degree evaluation values from large to small, all receiving registers with violation paths are sorted, time sequence optimization is conducted on the violation paths of the receiving registers according to the sequence, sorting can be conducted according to the violation degree evaluation values, optimization is conducted one by one from heavy to light, the optimization comprehensiveness can be improved, and the optimization efficiency is improved. Therefore, the time sequence optimization efficiency is improved.

The invention discloses a time sequence and congestion collaborative optimization-oriented GPU (Graphics Processing Unit) parallel acceleration global wiring method, which comprises the following steps of: according to a given netlist, dividing a super-large network by adopting a Kruskal algorithm in combination with a lookup set, and constructing a time sequence propagation path of the super-large network; performing network decomposition based on the timing margin estimation of the pins; calculating the time sequence weight of the two-pin network by adopting a time sequence weight calculation method based on an Elmore delay model; performing path cost calculation by adopting a cost function which comprehensively considers the time sequence and the congestion cost; executing two-level GPU parallel kernel acceleration mode wiring; optimizing the network topology by adopting a delay-aware pin connection improvement technology; the invention relates to a congestion-driven GPU (Graphics Processing Unit) accelerated routing and routing strategy for executing non-critical networks. According to the method, a high-quality wiring result with balanced time sequence congestion can be quickly obtained, the time sequence performance is effectively improved, and the requirement of a current super-large-scale high-performance circuit design wiring stage can be met.

Systems and methods are disclosed for phase calibration between clock and data lanes at a data link receiver. In calibration mode, matching signals are transmitted over the clock and data lanes, and a phase offset is measured at the receiver. A phase shifter in one signal path is adjusted to a first phase to obtain a desired phase offset. For operation mode, the phase shifter is set based on the first phase. Embodiments measure phase offset using an XOR gate and use a phase interpolator as the phase shifter. Embodiments with multiple data lanes apply coarse calibration to a shared clock lane relative to a first data lane, and similar fine calibration to other data lanes. Calibration provides optimum signal-to-noise ratio or timing margin, enabling high transmission speeds at relatively low power. Variations are disclosed.

Die or chip interconnect clock skew compensation can be performed for a multi-IC (Integrated Circuit) module. A timing margin or eye-width parameter (for example, a setup or hold time) for each of one or more interconnect lanes may be measured at a first die or chip of the multi-IC module that is receiving data and clock signals from a second die or chip of the multi-IC module. Compensation information can be determined based on the measured timing margin or eye-width parameter for each of one or more interconnect lanes. Compensation for clock skew can then be based on the determined compensation information.

The invention discloses a time sequence optimization method of a clock tree and a computer readable storage medium, and relates to the technical field of clock tree synthesis and time sequence optimization. The method comprises the steps that a to-be-processed time sequence path is obtained, time sequence optimization is conducted on the to-be-processed time sequence path from the to-be-processed time sequence path, and time sequence optimization comprises the steps that a register with the minimum time sequence margin is determined as a to-be-processed register; determining a target fan-in end timing margin according to the plurality of fan-in end timing margins of the to-be-processed register; and / or determining a target fan-out end timing margin according to the plurality of fan-out end timing margins of the register to be processed; calculating a clock offset according to the target fan-in end timing margin and / or the target fan-out end timing margin; adjusting the time sequence margin of each fan-in end of the register to be processed and / or the time sequence margin of each fan-out end of the register to be processed according to the clock offset; and updating the to-be-processed time sequence path until a set ending condition is met.

A specific logic circuitry of a semiconductor Integrated Circuit (IC) is measured by a sensor. The sensor includes: a signal splitter that splits a signal from the specific logic circuitry into two test paths; a delay element that receives and applies a delay to a first test path, the delay based on a predetermined timing margin that is selected from a group of discrete timing margin values comprising a shortest timing margin value and at least one longer timing margin value; a comparison circuit that compares the delayed first test path and a second test path and provides a measurement output according to the comparison for an instance of measuring; and a controller that sets the predetermined timing margin such that, over the instances of measuring, a frequency of selection of the shortest timing margin value is higher than a frequency of selection of each longer timing margin value.

A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path_failure_signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.

The invention provides a circuit aging monitoring device and method based on a double-section delay chain and signal upset detection. The circuit aging monitoring device comprises a data upset detection module, a double-section buffer delay chain, a rising edge sampling logic module, a signal comparison module and a falling edge anti-burr judgment output logic module. The data flipping detection module monitors flipping of the input signal and generates an enabling control signal; the double-section buffer delay chain applies two-stage configurable delay to an input signal and outputs signals with different delay degrees; the rising edge sampling logic module is used for sampling and latching each path of signal; the signal comparison module compares the sampling signals and generates a time sequence margin intermediate signal; and the falling edge anti-burr judgment output logic module latches the intermediate signal at the falling edge of the clock and updates the output state only when the enabling is effective.

The application discloses a kind of synchronization methods of multi-channel high-speed digital-analog conversion module, comprising: reference clock source generates reference clock;Trigger controller generates trigger signal, trigger signal is used to inform each DAC board to start the digital quantity transmission of new waveform;Master chip PLL is multiplied to preset operating frequency by reference clock, and the feedback path of master chip PLL is removed to DAC board, and the delay of voltage-controlled oscillator output master chip IO's wiring is consistent and position is close;DAC PLL is multiplied to the sampling clock frequency of DAC by reference clock, and the output phase of DAC PLL can be adjusted, to ensure the timing margin when DAC reads digital quantity;Master chip is triggered under trigger signal, and at preset time, the digital quantity of several waveforms to be converted is sent to DAC by isochronous transmission path, and DAC converts digital quantity into analog waveform, realizes that all DAC completes digital quantity to analog quantity conversion at the same time, and realizes the high-precision synchronous conversion of DAC.

According to the time sequence path analysis method and system provided by the invention, the time sequence allowance of each time sequence source point is calculated, the path analysis is carried out from the time sequence source point with the minimum time sequence allowance to find out the key paths, and when the number of the key paths reaches the number required by a user, the analysis is stopped, so that the analysis of a lot of useless paths is reduced, and the user experience is improved. The analysis time is saved, when the number of the paths meets the requirement, the paths are critical paths, compared with the prior art that all the paths need to be analyzed to find out the critical paths, the analysis time is greatly shortened, and the effect is very obvious especially when the number of devices is large.

This invention provides a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. A sensor array is deployed along the critical signal path to simultaneously acquire high-frequency crosstalk spectrum and timing eye diagram parameters, generating a crosstalk intensity matrix (CIM) and a timing margin heatmap (TMM) to achieve multi-dimensional quantitative characterization of signal integrity. Based on the CIM, the main interference source is located, and the impedance of the affected line is dynamically adjusted and a reverse compensation current is injected to cancel high-frequency crosstalk at its source. The margin attenuation is predicted using a pre-trained model, and the clock phase of the affected line is fine-tuned to compensate for timing deviations. The optimized efficiency index per unit energy consumption after compensation is calculated, triggering a dynamic update or re-compensation mechanism for the strategy library. This invention achieves dynamic synergy between crosstalk suppression and timing optimization based on a closed-loop architecture composed of monitoring data, neural network prediction, dual-loop compensation, energy efficiency verification, and strategy learning.

The invention discloses a logic replication decision-making method and device, equipment and a storage medium. Comprising the following steps: extracting key parameters of each copy unit, and calculating the revenue density of each copy unit according to the key parameters; generating a copy unit list based on the revenue density, and selecting candidate combinations from the copy unit list; and calculating a cost value of each candidate combination to determine an optimal copy unit combination. The key parameters of the copy unit are extracted through the script tool, the key parameters comprise the multiplexing frequency, the time sequence margin lifting amount and the resource overhead, and errors and low efficiency caused by manual extraction are avoided. The replication value is quantified through a revenue density function, a list is generated, then the area cost and the time sequence loss are fused, the comprehensive optimization cost of the candidate combinations is quantified, the dimension difference of different dimension indexes is eliminated, and the advantages and disadvantages of the candidate combinations have the comparable basis. The dynamic balance of the area and the time sequence is realized, the problem that the copy area is out of control or the critical path coverage is incomplete is avoided, and the logic copy optimization effect is guaranteed.

This invention discloses a time-to-digital converter and its time margin extraction circuit, comprising multiple time margin extraction units; a first OR gate, with multiple input terminals receiving first output signals from the multiple time margin extraction units respectively, and an output terminal providing a second start signal; a second OR gate, with multiple input terminals receiving second output signals from the multiple time margin extraction units respectively, and an output terminal providing a second stop signal; each time margin extraction unit includes a first flip-flop, with its input terminal connected to a first input signal and a set terminal of a first pseudo-flip-flop, and its set terminal connected to the first stop signal and the input terminal of a second pseudo-flip-flop; a second flip-flop, providing a first output signal based on the output signal of the first flip-flop and the first input signal; and a third flip-flop, providing a second output signal based on the output signal of the first flip-flop and the second input signal, thereby improving the measurement accuracy of the time-to-digital converter and its continuous measurement capability.

Integrated circuit (IC) design based on timing slack according to an example includes accessing physical design data for an IC layout, wherein the physical design data comprises a netlist including active metal shapes of a metal shapes infrastructure forming signal path nets connecting different parts of the IC layout. Timing-based design rule checking of the physical design data is performed to identify slack stealing information for the signal path nets. Shape-based density design rule checking of the metal shapes infrastructure is performed, based on the slack stealing information, to perform fill insertion of metal fill shapes to satisfy density requirements in the IC layout.

Described herein is a User Equipment, UE, comprising: at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the UE at least to: determine a start time and an end time of a first time window comprising at least a second time window with uplink scheduling restrictions; and if, based on the determining, a time that remains before the start time of the first time window is equal to or smaller than a pre-configured time margin, perform triggering of a Delay Status Report, DSR.

The application relates to the technical field of integrated circuits, and provides a chip control circuit and method for adaptive frequency modulation and voltage modulation, which comprises a timing monitoring module, a critical path replication submodule and a daisy chain delay submodule connected to the timing monitoring module, the critical path replication submodule is used for simulating an actual critical data path in a chip, the daisy chain delay submodule is used for applying a configurable delay amount on the timing of an output data signal, so as to simulate the timing performance after different time points, a first flip-flop is used for transmitting the data signal, a sampling flip-flop module is used for sampling the data signal output by the timing monitoring module, a comparison logic module is used for generating a multi-bit timing margin indication code through a comparison result, and the timing margin indication code is used for adaptively adjusting the working frequency or working voltage of the chip. Through accurate monitoring and adaptive adjustment of the timing of the chip, all design margins can be utilized, the energy utilization efficiency is improved, and therefore, the ultimate low power consumption is realized.

A macro cell layout method and a related apparatus, relating to the technical field of electronic design automation. The method comprises: acquiring connection relationship information and alternative layouts of t macro cells; inputting the connection relationship information and position information into an indicator prediction model so as to output predicted values of evaluation indicators; and obtaining a target layout of the t macro cells on the basis of the predicted values of the evaluation indicators and the alternative layouts. In the present application, the evaluation indicators may be any indicators, such as worst negative slack, total negative slack, half-perimeter wirelength, and degree of congestion. The problem that existing macro cell layout methods mainly focus on optimizing intermediate proxy indicators which are easy to acquire at a current stage and ignore cross-stage indicators which truly reflect final chip quality is solved and the timing performance of a circuit is optimized, ensuring that the circuit has a higher design quality and higher manufacturability. In the present application, the objective of improving evaluation indicators of a circuit in an "end-to-end" manner is achieved, manual intervention is not needed, costs are lower, and efficiency is higher.

The present disclosure provides a circuit timing processing method and device, electronic equipment and storage medium, and relates to the technical field of integrated circuits. The method comprises: obtaining a timing violation path in a chip circuit and a timing margin of the timing violation path; the timing margin of the timing violation path does not satisfy a timing constraint condition; determining interface attribute information of an interface connection through which the timing violation path passes; based on the interface attribute information and the timing margin, determining a physical position of a delay unit to be inserted in the timing violation path; and generating a control instruction according to the physical position of the delay unit, the control instruction being used to instruct insertion of the delay unit at the physical position. The present scheme can improve the efficiency of circuit timing processing.

The present invention provides a memory testing method, system, device, and storage medium. The method includes: obtaining test input data based on the bit width of the memory to be tested; constructing test elements based on the test input data according to preset timing rules; and sequentially executing each test element on the memory to be tested; the preset timing rules satisfy the following conditions: after reading the previous address, writing the current address, the unit storage value corresponding to the previous address is not equal to the unit storage value corresponding to the current address, and the previous address and the current address are adjacent in both logical address sequence and physical address sequence. By adding test elements with insufficient timing margin, the present invention can prevent missed detection of the memory to be tested, thereby improving the test coverage of the memory testing method, increasing the qualified rate of produced memory, and reducing the user's losses caused by unqualified chips.

A timing margin sensor includes a delay circuit to generate a calibrated delay that corresponds to a known delay value of a logic circuit. Circuitry locks a first delay produced by the delay circuit to a clock period of a clock signal that is associated with the known delay value. A programmable selector adjusts the first delay to generate the calibrated delay, the calibrated delay including a timing margin component. Circuitry detects a change in supply voltage provided to the logic circuit based on a detected change in the calibrated delay. Clock adjustment circuitry selectively changes the clock period based on the detected change in the calibrated delay.

The application relates to a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology, which comprises an N-stage TDC module, a pulse generator and a digital decoding module; two adjacent TDC modules are connected through the pulse generator to form an N-stage pipeline architecture; the quantization of each TDC module generates a temperature code which is input to the digital decoding module; the digital decoding module obtains a digital code Dout after decoding and processing the temperature code and outputs the digital code Dout; the first N-1 TDC modules are the same in structure and each comprises two low-bit sub-TDC modules connected in cascade; the Nth TDC module comprises two high-bit sub-TDC modules connected in cascade. The application uses an N-stage pipeline architecture, each stage of which comprises two-stage sub-TDC modules, avoids the use of a time margin amplifier, the two-stage sub-TDC modules automatically calibrate the aperture error, higher linearity is achieved, and the noise performance remains unchanged.

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.

This application provides a dynamic timing adaptive adjustment method for NAND Flash controller chips, relating to the field of data processing. In this method, a calibration context is centrally located within the NAND Flash controller chip. Controlled transaction scheduling drives delay sampling measurements to obtain the true physical timing characteristics between the controller chip and the memory chips. Timing configurations matching the chip states are dynamically generated based on phase distribution statistics, environmental state information, and operational state information. During system operation, hardware-level feedback statistics are performed on error correction intensity, error count, and retry count. The direction of timing margin adjustment is determined online based on phase distribution changes. Uninterrupted switching of timing configurations is completed at transaction boundaries, thereby achieving multi-round adaptive calibration and improving the performance and reliability balance under different process technologies and different lifespan stages of the chips. Implementing the technical solution provided in this application facilitates the resolution of the problem of insufficient timing adaptability of NAND Flash controller chips under complex operating conditions.

This invention belongs to the technical field of time-to-digital converters (TD-SCDs), specifically disclosing a circuit and method for extracting the quantization margin of a time-to-digital converter. This invention adds an XOR gate and a transmission gate unit to the existing time-to-digital converter to extract the time margin, and outputs it through a dynamic OR gate. The circuit provided by this invention can extract the time margin that the time-to-digital converter cannot quantize, accurately measure the quantization error, and thus allow for further measurement of the time margin, improving the overall measurement accuracy of the time-to-digital converter. The circuit and method provided by this invention can not only extract the time margin that the time-to-digital converter cannot quantize, but also accurately determine the position of the trigger signal in the delay chain.

The invention provides a synchronous test software method and structure for a time-triggered bus. The method comprises the steps of system initialization, bus configuration, sending and receiving logic design and main loop construction based on a communication scheduling table, and accurate synchronization of a test process and a bus time slot is achieved. For testing software function complexity, two synchronization strategies are adopted: for a scene with a simple function, corresponding operation is executed by polling a current TDMA time slot number; for a scene with complex functions, a main cycle period is expanded into a cluster period, detection cycles of sending and receiving time slots are inserted into the cluster period, complex tasks are executed in idle time slots, and reliable capture of key time slots is ensured through logic decomposition and time margin reservation. According to the invention, non-intrusive and high-precision synchronous testing capability is realized, key performance indexes such as time delay, jitter and packet loss rate of the time-triggered bus can be effectively measured, and the method is suitable for multiple time-triggered bus protocols such as TTP / C, TTEEthernet and FlexRay.