53 results about "Timing margin" patented technology

The invention discloses a time sequence convergence method and device based on a clock tree, and relates to the technical field of circuit design. The method comprises the following steps: performing automatic layout on devices; determining a time sequence path needing to be optimized in the one-to-many structure time sequence path; performing establishment time sequence margin optimization, and determining a setting pattern of useful clock skew adjustment based on the optimized establishment time sequence margin; determining the number of buffers based on the setting pattern of useful clock skew adjustment and the optimized setup time sequence margin, and generating a clock tree; on the basis of the generated clock tree, determining whether the time sequence violation of the retention time of the time sequence path needing to be optimized meets a preset requirement or not, and if the preset requirement is not met, adjusting the setting pattern of the useful clock skew adjustment, and returning to the step of generating the clock tree; and completing automatic wiring based on the clock tree meeting the predetermined requirement. According to the invention, the problem of power consumption increase caused by restoration of Hold time sequence violation can be solved.

A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path_failure_signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.

The invention provides a circuit aging monitoring device and method based on a double-section delay chain and signal upset detection. The circuit aging monitoring device comprises a data upset detection module, a double-section buffer delay chain, a rising edge sampling logic module, a signal comparison module and a falling edge anti-burr judgment output logic module. The data flipping detection module monitors flipping of the input signal and generates an enabling control signal; the double-section buffer delay chain applies two-stage configurable delay to an input signal and outputs signals with different delay degrees; the rising edge sampling logic module is used for sampling and latching each path of signal; the signal comparison module compares the sampling signals and generates a time sequence margin intermediate signal; and the falling edge anti-burr judgment output logic module latches the intermediate signal at the falling edge of the clock and updates the output state only when the enabling is effective.

This invention provides a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. A sensor array is deployed along the critical signal path to simultaneously acquire high-frequency crosstalk spectrum and timing eye diagram parameters, generating a crosstalk intensity matrix (CIM) and a timing margin heatmap (TMM) to achieve multi-dimensional quantitative characterization of signal integrity. Based on the CIM, the main interference source is located, and the impedance of the affected line is dynamically adjusted and a reverse compensation current is injected to cancel high-frequency crosstalk at its source. The margin attenuation is predicted using a pre-trained model, and the clock phase of the affected line is fine-tuned to compensate for timing deviations. The optimized efficiency index per unit energy consumption after compensation is calculated, triggering a dynamic update or re-compensation mechanism for the strategy library. This invention achieves dynamic synergy between crosstalk suppression and timing optimization based on a closed-loop architecture composed of monitoring data, neural network prediction, dual-loop compensation, energy efficiency verification, and strategy learning.

The invention discloses a logic replication decision-making method and device, equipment and a storage medium. Comprising the following steps: extracting key parameters of each copy unit, and calculating the revenue density of each copy unit according to the key parameters; generating a copy unit list based on the revenue density, and selecting candidate combinations from the copy unit list; and calculating a cost value of each candidate combination to determine an optimal copy unit combination. The key parameters of the copy unit are extracted through the script tool, the key parameters comprise the multiplexing frequency, the time sequence margin lifting amount and the resource overhead, and errors and low efficiency caused by manual extraction are avoided. The replication value is quantified through a revenue density function, a list is generated, then the area cost and the time sequence loss are fused, the comprehensive optimization cost of the candidate combinations is quantified, the dimension difference of different dimension indexes is eliminated, and the advantages and disadvantages of the candidate combinations have the comparable basis. The dynamic balance of the area and the time sequence is realized, the problem that the copy area is out of control or the critical path coverage is incomplete is avoided, and the logic copy optimization effect is guaranteed.

This invention discloses a time-to-digital converter and its time margin extraction circuit, comprising multiple time margin extraction units; a first OR gate, with multiple input terminals receiving first output signals from the multiple time margin extraction units respectively, and an output terminal providing a second start signal; a second OR gate, with multiple input terminals receiving second output signals from the multiple time margin extraction units respectively, and an output terminal providing a second stop signal; each time margin extraction unit includes a first flip-flop, with its input terminal connected to a first input signal and a set terminal of a first pseudo-flip-flop, and its set terminal connected to the first stop signal and the input terminal of a second pseudo-flip-flop; a second flip-flop, providing a first output signal based on the output signal of the first flip-flop and the first input signal; and a third flip-flop, providing a second output signal based on the output signal of the first flip-flop and the second input signal, thereby improving the measurement accuracy of the time-to-digital converter and its continuous measurement capability.

Integrated circuit (IC) design based on timing slack according to an example includes accessing physical design data for an IC layout, wherein the physical design data comprises a netlist including active metal shapes of a metal shapes infrastructure forming signal path nets connecting different parts of the IC layout. Timing-based design rule checking of the physical design data is performed to identify slack stealing information for the signal path nets. Shape-based density design rule checking of the metal shapes infrastructure is performed, based on the slack stealing information, to perform fill insertion of metal fill shapes to satisfy density requirements in the IC layout.

Described herein is a User Equipment, UE, comprising: at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the UE at least to: determine a start time and an end time of a first time window comprising at least a second time window with uplink scheduling restrictions; and if, based on the determining, a time that remains before the start time of the first time window is equal to or smaller than a pre-configured time margin, perform triggering of a Delay Status Report, DSR.

The application relates to the technical field of integrated circuits, and provides a chip control circuit and method for adaptive frequency modulation and voltage modulation, which comprises a timing monitoring module, a critical path replication submodule and a daisy chain delay submodule connected to the timing monitoring module, the critical path replication submodule is used for simulating an actual critical data path in a chip, the daisy chain delay submodule is used for applying a configurable delay amount on the timing of an output data signal, so as to simulate the timing performance after different time points, a first flip-flop is used for transmitting the data signal, a sampling flip-flop module is used for sampling the data signal output by the timing monitoring module, a comparison logic module is used for generating a multi-bit timing margin indication code through a comparison result, and the timing margin indication code is used for adaptively adjusting the working frequency or working voltage of the chip. Through accurate monitoring and adaptive adjustment of the timing of the chip, all design margins can be utilized, the energy utilization efficiency is improved, and therefore, the ultimate low power consumption is realized.

A macro cell layout method and a related apparatus, relating to the technical field of electronic design automation. The method comprises: acquiring connection relationship information and alternative layouts of t macro cells; inputting the connection relationship information and position information into an indicator prediction model so as to output predicted values of evaluation indicators; and obtaining a target layout of the t macro cells on the basis of the predicted values of the evaluation indicators and the alternative layouts. In the present application, the evaluation indicators may be any indicators, such as worst negative slack, total negative slack, half-perimeter wirelength, and degree of congestion. The problem that existing macro cell layout methods mainly focus on optimizing intermediate proxy indicators which are easy to acquire at a current stage and ignore cross-stage indicators which truly reflect final chip quality is solved and the timing performance of a circuit is optimized, ensuring that the circuit has a higher design quality and higher manufacturability. In the present application, the objective of improving evaluation indicators of a circuit in an "end-to-end" manner is achieved, manual intervention is not needed, costs are lower, and efficiency is higher.

The present disclosure provides a circuit timing processing method and device, electronic equipment and storage medium, and relates to the technical field of integrated circuits. The method comprises: obtaining a timing violation path in a chip circuit and a timing margin of the timing violation path; the timing margin of the timing violation path does not satisfy a timing constraint condition; determining interface attribute information of an interface connection through which the timing violation path passes; based on the interface attribute information and the timing margin, determining a physical position of a delay unit to be inserted in the timing violation path; and generating a control instruction according to the physical position of the delay unit, the control instruction being used to instruct insertion of the delay unit at the physical position. The present scheme can improve the efficiency of circuit timing processing.

A timing margin sensor includes a delay circuit to generate a calibrated delay that corresponds to a known delay value of a logic circuit. Circuitry locks a first delay produced by the delay circuit to a clock period of a clock signal that is associated with the known delay value. A programmable selector adjusts the first delay to generate the calibrated delay, the calibrated delay including a timing margin component. Circuitry detects a change in supply voltage provided to the logic circuit based on a detected change in the calibrated delay. Clock adjustment circuitry selectively changes the clock period based on the detected change in the calibrated delay.

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.

This application provides a dynamic timing adaptive adjustment method for NAND Flash controller chips, relating to the field of data processing. In this method, a calibration context is centrally located within the NAND Flash controller chip. Controlled transaction scheduling drives delay sampling measurements to obtain the true physical timing characteristics between the controller chip and the memory chips. Timing configurations matching the chip states are dynamically generated based on phase distribution statistics, environmental state information, and operational state information. During system operation, hardware-level feedback statistics are performed on error correction intensity, error count, and retry count. The direction of timing margin adjustment is determined online based on phase distribution changes. Uninterrupted switching of timing configurations is completed at transaction boundaries, thereby achieving multi-round adaptive calibration and improving the performance and reliability balance under different process technologies and different lifespan stages of the chips. Implementing the technical solution provided in this application facilitates the resolution of the problem of insufficient timing adaptability of NAND Flash controller chips under complex operating conditions.

This invention belongs to the technical field of time-to-digital converters (TD-SCDs), specifically disclosing a circuit and method for extracting the quantization margin of a time-to-digital converter. This invention adds an XOR gate and a transmission gate unit to the existing time-to-digital converter to extract the time margin, and outputs it through a dynamic OR gate. The circuit provided by this invention can extract the time margin that the time-to-digital converter cannot quantize, accurately measure the quantization error, and thus allow for further measurement of the time margin, improving the overall measurement accuracy of the time-to-digital converter. The circuit and method provided by this invention can not only extract the time margin that the time-to-digital converter cannot quantize, but also accurately determine the position of the trigger signal in the delay chain.

The invention provides a synchronous test software method and structure for a time-triggered bus. The method comprises the steps of system initialization, bus configuration, sending and receiving logic design and main loop construction based on a communication scheduling table, and accurate synchronization of a test process and a bus time slot is achieved. For testing software function complexity, two synchronization strategies are adopted: for a scene with a simple function, corresponding operation is executed by polling a current TDMA time slot number; for a scene with complex functions, a main cycle period is expanded into a cluster period, detection cycles of sending and receiving time slots are inserted into the cluster period, complex tasks are executed in idle time slots, and reliable capture of key time slots is ensured through logic decomposition and time margin reservation. According to the invention, non-intrusive and high-precision synchronous testing capability is realized, key performance indexes such as time delay, jitter and packet loss rate of the time-triggered bus can be effectively measured, and the method is suitable for multiple time-triggered bus protocols such as TTP / C, TTEEthernet and FlexRay.

The application relates to the technical field of time measurement counting, and discloses a high-precision time-to-digital converter core, which comprises a delay phase-locked loop, a clock signal is input into the delay phase-locked loop to obtain a plurality of phase-split clock signals; an arbitrator, a to-be-measured signal and the phase-split clock signals are input into the arbitrator to perform first-stage time measurement and obtain first-stage quantization data; a time margin extraction circuit, the first-stage quantization data and the phase-split clock signals are input into the time margin extraction circuit, a time remaining part which cannot be measured in the first-stage time measurement is extracted, and a time start signal required by second-stage time measurement is obtained; a vernier chain, the time start signal and a time end signal are input into the vernier chain to perform second-stage time measurement, and second-stage quantization data obtained is quantization data output by the time-to-digital converter core. The high precision is achieved by breaking through the process limit, and the wide range characteristic is maintained; through later calibration, the linearity and the precision of the TDC can be further improved.

A clock tree timing optimization method and a computer readable storage medium, relate to the technical field of clock tree synthesis and timing optimization. The method comprises: obtaining a to-be-processed timing path, starting from the to-be-processed timing path, performing timing optimization on the to-be-processed timing path, the timing optimization comprising: determining a register with the smallest timing margin as a to-be-processed register; determining a target fan-in end timing margin according to a plurality of fan-in end timing margins of the to-be-processed register; and / or determining a target fan-out end timing margin according to a plurality of fan-out end timing margins of the to-be-processed register; calculating a clock offset according to the target fan-in end timing margin and / or the target fan-out end timing margin; adjusting each fan-in end timing margin of the to-be-processed register and / or each fan-out end timing margin of the to-be-processed register according to the clock offset; updating the to-be-processed timing path until a set ending condition is reached.

The application provides a critical path monitoring point screening method and system combining path activation rate and similarity, comprising: obtaining timing information of all paths of a target circuit based on static timing analysis, and screening paths with timing margin less than a preset timing margin threshold to form a critical path set; based on a preset benchmark test set, performing signal flip statistics on monitoring points of each path in the critical path set, calculating the activation rate of each path, and filtering out paths with zero activation rate to obtain an effective path set; grouping paths in the effective path set according to the starting points of the paths to obtain a plurality of path groups; for each path group, calculating the similarity between paths based on the logical topology structure sequence of the paths in the group, and clustering the paths according to the similarity, and screening at least one path from each cluster; and collecting paths obtained after screening of all path groups to form a final monitoring point set.

The invention provides a worst execution time path derivation method for an ARINC653 operating system. Only tasks to be tested are reserved in a partition to be tested; from the entrance of the to-be-tested task to top down, performing pile pitching on each branch possibly influencing the program trend in the to-be-tested task; running the to-be-tested task under the target machine, injecting a test case set into the to-be-tested task, and collecting time information of each branch in all pile points; subtracting the execution time of the pile point from the execution time of the to-be-tested task; and obtaining a theoretical worst path and an actual worst path of the to-be-tested project, fitting the bifurcation points of the two paths to obtain a fitting path, running the fitting path under the target machine again, and obtaining a final WCET path. The method solves the problems that a static analysis method is difficult to meet the time margin resource requirement of embedded software operation, a dynamic measurement method is difficult to prove that the obtained result is a real WCET value, and the algorithm threshold is too high.

The application discloses a dynamic voltage regulation and power balance control method and system in an integrated circuit, and particularly relates to the technical field of integrated circuit power management, which measures the timing margin, load change slope and voltage undershoot amplitude of a key path in real time, calculates a timing robustness quantitative value, calculates a leading compensation pulse and sends the same before load jumping, dynamically switches PID coefficients to suppress nonlinear oscillation, stretches a clock or freezes a pipeline when the timing robustness quantitative value is lower than a first threshold value, inserts idle instructions to cut off positive feedback when the product of a current change rate and a temperature gradient is higher than a second threshold value, decouples and isolates a calculation core from peripheral logic, and calibrates the first and second threshold values, so that the application suppresses voltage transients through the leading compensation pulse, reduces timing violation risks, blocks metastable state propagation and positive feedback cycles through clock stretching or pipeline freezing and forced idle instructions, and improves adaptive capacity through voltage domain decoupling and isolation and stable state feedback calibration of threshold values.

Aspects relate to monitoring, by an integrated circuit, a timing margin of a logic path and its degradation. In one example, an apparatus includes an integrated circuit having a logic path formed therein; and a monitoring circuit formed in the integrated circuit. The monitoring circuit is configured to monitor a condition of the logical path and generate a sequence of diagnostic codes to indicate the condition of the logical path over time. A monitoring controller is configured to receive diagnostic codes in the sequence of diagnostic codes, store the diagnostic codes in a log along with corresponding timestamps, and determine a condition of the integrated circuit based on the sequence of diagnostic codes.

The present application relates to a leakage power consumption optimization method and device of a chip. The method comprises: finding a timing logic device whose threshold voltage is lower than a predetermined threshold voltage in a circuit to form an initial device set; determining a first feature and a second feature of the timing logic device, the first feature comprising a timing margin of the timing logic device, and the second feature comprising a judgment result of whether there exists a replaceable target timing logic device corresponding to the timing logic device in a device library, the target timing logic device having a same function type as the timing logic device and a threshold voltage higher than that of the timing logic device; selecting a replaceable timing logic device from the initial device set according to the first feature, the second feature and a leakage power consumption optimization strategy parameter; and replacing the replaceable timing logic device in the target circuit with the target timing logic device. The method effectively reduces the leakage power consumption of the chip and improves the energy efficiency ratio of the chip under the premise of ensuring the timing performance of the circuit.

Optimizing timing margins across conditions is described. In one or more implementations, a computing system may include an interface circuitry configured to adjust a timing alignment of first and second signals between a central processing unit (CPU) of the system and a device coupled with the CPU and to measure and store one or more margins between the timing alignment and misalignments of the first and second signals. The interface circuitry may be configured to measure and store the timing margins at first and second conditions. The first and second conditions may be different voltages, temperatures, etc. The system may be configured to force the first and / or second condition. The system may be configured to calculate a coefficient from differences in between the margins and between the first and second conditions.

Embodiments of the present application provide a timing detection circuit, method and electronic device, and relate to the technical field of electronic devices. The circuit comprises an oscillator, a path simulator, a delay detector and a pre-warning device. The oscillator generates an oscillation signal based on the rising edge jump of a clock signal, the path simulator simulates the propagation process of the oscillation signal in the critical path of the chip, the delay detector determines the propagation time of the oscillation signal in the path simulator based on the clock signal, and the pre-warning device generates a timing pre-warning signal representing timing anomalies when the propagation time does not meet the preset conditions. By generating an oscillation signal based on the rising edge jump of the clock signal and simulating the propagation process of the oscillation signal in the critical path, the propagation time of the oscillation signal can be detected based on the clock signal, the propagation time of the oscillation signal can be quickly determined, and the propagation time of the signal in the critical path in the chip can be determined, and it is determined whether the timing margin of the chip is sufficient.

The invention discloses a sending channel circuit based on a 1 / 4 rate structure SERDES, and belongs to the technical field of integrated circuit design, and the circuit comprises a common phase-locked loop which is used for generating a four-phase sending clock, and the phase difference of the four-phase sending clock is 1 UI; at least one sending channel, each of which is connected with the common phase-locked loop and is used for receiving the four-phase sending clock; the sending channel comprises an input register used for receiving parallel input data; and the encoder is connected with the output end of the input register and is used for encoding the data. According to the invention, fast clock alignment of the SERDES sending channel can be realized through small circuit resource overhead, the precision is controlled to be about two UIs, and protocol application requirements such as PCIE, USB and the like are met; for a high-speed application scene, the time sequence margin of cross-clock data interaction is improved through frequency division, and the working reliability of the system is improved.

Methods and apparatus for obtaining timing adjustment values for clock points in a clock network are disclosed. In some embodiments, engineering change order (ECO) may be performed in a time- and resource-efficient manner by selecting candidate clock points from a plurality of clock points in the clock network, and performing enumerative and iterative tests on the selected candidate clock points to determine a combination of timing delay adjustment values that most reduces negative slack. The determined timing delay adjustment values may be implemented by an ECO system to effect changes to the clock network and reduce timing violations therein.

A technique capable of improving accuracy of an amount of delay of a sampling clock is provided. A semiconductor device includes: a communication device for wired communication; a delay adder circuit capable of adjusting an amount of delay of a clock to be received or transmitted by the communication device; and a control circuit controlling the amount of delay of the delay adder circuit. The communication device is configured to set a reception period or a transmission period of a normal frame and a reception period or a transmission period of a check frame in time division, and to confirm timing margins of setup and hold between data and a clock in the reception period or the transmission period of the check frame. The control circuit is configured to set the amount of delay in the normal frame, based on a confirmation result of the timing margins.

Aspects relate to monitoring, by an integrated circuit, a timing margin of a logic path and its degradation. In one example, an integrated circuit has a logic path formed in the integrated circuit. Monitoring circuitry is formed in the integrated circuit proximate to the logical path and is configured to monitor a condition of the logical path and to generate a sequence of diagnostic codes to indicate the condition of the logical path over time. A monitoring controller is configured to receive diagnostic codes in the sequence of diagnostic codes, determine a condition of the integrated circuit based on the sequence of diagnostic codes, and initiate a corrective action in response to the condition of the integrated circuit.

A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path failure signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.