9 results about "Clock domain crossing" patented technology

An interface control device includes a clock domain crossing (CDC) circuit configured to receive a first signal synchronized with a first clock, and output a second signal corresponding to the first signal synchronized with a second clock, a demultiplexer configured to divide the second signal into a plurality of signals to generate configuration information, a configuration register configured to store the configuration information, and an interface controller configured to operate according to the configuration information stored in the configuration register.

A synchronizer with flip-flops has a reduced number of flip-flops coupled in series, receiving as an input data of a first clock domain and supplying as an output data in the second clock domain. The second clock signal is at a variable frequency adjusted to a target frequency, by a division factor. The flip-flops are timed by a clock signal subsampling the second clock signal by a factor k1. The subsampled clock signal is generated by a frequency divider propagating a pulse of the signal every k1 clock pulses, while keeping the edges aligned.

The invention relates to a frequency modulation synchronizer for clock domain crossing. A synchronizer with flip-flops has a reduced number of flip-flops coupled in series that receive data of a first clock domain as an input and provide data in a second clock domain as an output. The second clock signal is at a variable frequency that is adjusted to a target frequency by a frequency division factor. The flip-flop is clocked by a clock signal subsampled by a factor k1 on the second clock signal. The sub-sampled clock signal is generated by a frequency divider that propagates one pulse of the signal per k1 clock pulses while maintaining edge alignment.

Techniques and apparatuses are described for supporting multiple functions of a network-on-chip using a buffer. In example aspects, a network-on-chip (110) uses a credit-based protocol and facilitates communication between different subsystems (108) associated with different clock domains (206), different voltage domains 208, different power domains 210, different data widths (212), or some combination thereof. The network-on-chip (110) includes a buffer (118), which provides storage for credit management (214), storage for an asynchronous clock-domain crossing (216), and storage for data upscaling (218). While other network-on-chips or other system-on-chips can have individual storage elements to support each function, the buffer (118) acts as a single storage element capable of supporting each of these functions. With the buffer (118), the network-on-chip (110) can have a smaller footprint, can consume less power, and can have less latency compared to other network-on-chips that utilize multiple storage elements.

A clock domain crossing interface is described. The clock domain crossing interface includes a transmit clock domain and a receive clock domain using a different clock from the transmit clock domain. The clock domain crossing interface also includes a first-in-first-out (FIFO) buffer coupled between the transmit clock domain and the receive clock domain. The FIFO buffer to store ordered transactions sent from the transmit clock domain to the receive clock domain. The clock domain crossing interface further includes a transmit clock domain event transfer block to notify the receive clock domain of a new transaction pushed onto the FIFO buffer in the transmit clock domain. The clock domain crossing interface also includes a receive clock domain event transfer block to notify the transmit clock domain of a new transaction pulled from the FIFO buffer in the receive clock domain.

The present invention provides a semiconductor device having two independent power domains: a first power domain and a second power domain. Different clock signals are applied to the respective circuits which are provided in the first and second power domains. The first and second power domains have a first storage unit and a second storage unit, respectively. When the semiconductor device enters a power-saving mode, the parameter of the first storage unit is maintained in the second storage unit, and then the first power domain is turned off. In the power-saving mode, the timing of each device in the second power domain is driven by the second clock signal, so as to solve the problem of clock domain crossing between different power domains. Therefore, the second power domain may use a second storage unit with a lower processing speed than the first storage unit.

An apparatus comprises buffer circuitry having a plurality of data entries each arranged to store a data block, where each data block has an associated data channel. The buffer circuitry is configured to receive data blocks from producer circuitry controlled by a first clock signal and to provide the data blocks to consumer circuitry controlled by a second clock signal. The apparatus also provides indicator storage having a plurality of indicator entries, wherein each data entry has an associated indicator entry and, for a given data entry storing a given data block, the associated indicator entry is configured to indicate the associated data channel for the given data block. Selection circuitry is provided to select a data entry from which to provide a data block to the consumer circuitry, by referencing the plurality of indicator entries.

The invention discloses an asynchronous dual-port memory and a real-time digital phase shifter system, the asynchronous dual-port memory is introduced into the real-time digital phase shifter system, and the asynchronous dual-port memory comprises a memory access time slot used for dynamically distributing a dual-port block RAM according to a data read-write task request, the controller is used for receiving a Gray code counter and issuing a stepping instruction of the Gray code counter and a cross-domain control instruction of the clock domain cross module; the Gray code counter is used for receiving a stepping instruction of the controller and outputting a Gray code address to the dual-port block RAM; the clock domain cross module is used for receiving a cross-domain control instruction and providing a synchronous access signal for the dual-port block RAM; and executing asynchronous read-write operation according to the Gray code address, the synchronous access signal and the allocated memory access time slot, and storing a dual-port block RAM of a phase and power data pair of the asynchronous read-write operation. The method has the characteristics of high data access efficiency, real-time performance and high precision.

A stacked Processing Near Memory (PNM) device, in order to achieve smooth clock domain crossing (CDC) between a stacked memory chip and a logic chip and to minimize a consumption of die area, can train a delay time of an asynchronous path for each bank of the memory chip and optimally control an output timing of received data for each bank in each corresponding FIFO in consideration of the delay time of each bank as a result of the training. The stacked PNM device may perform a CDC training method and a normal operation method.