2 results about "Clock domain crossing" patented technology

A clock domain crossing interface is described. The clock domain crossing interface includes a transmit clock domain and a receive clock domain using a different clock from the transmit clock domain. The clock domain crossing interface also includes a first-in-first-out (FIFO) buffer coupled between the transmit clock domain and the receive clock domain. The FIFO buffer to store ordered transactions sent from the transmit clock domain to the receive clock domain. The clock domain crossing interface further includes a transmit clock domain event transfer block to notify the receive clock domain of a new transaction pushed onto the FIFO buffer in the transmit clock domain. The clock domain crossing interface also includes a receive clock domain event transfer block to notify the transmit clock domain of a new transaction pulled from the FIFO buffer in the receive clock domain.

A stacked Processing Near Memory (PNM) device, in order to achieve smooth clock domain crossing (CDC) between a stacked memory chip and a logic chip and to minimize a consumption of die area, can train a delay time of an asynchronous path for each bank of the memory chip and optimally control an output timing of received data for each bank in each corresponding FIFO in consideration of the delay time of each bank as a result of the training. The stacked PNM device may perform a CDC training method and a normal operation method.