23 results about "Clock domain crossing" patented technology

The invention relates to the technical field of integrated circuits, and provides a clock domain crossing synchronization circuit and method based on a multiphase clock, and the circuit comprises a selector, an asynchronous clock synchronization module and a digital signal processor. Wherein serial data to be transmitted and a low-frequency clock are input into the selector, and the selector is used for outputting corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; the asynchronous clock synchronization module is used for outputting corresponding alignment data to the digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low-frequency clock; the asynchronous clock synchronization module is used for performing phase alignment on the RX parallel data and a clock of the digital signal processor; and the digital signal processor is used for carrying out data processing on the alignment data. According to the invention, stable transmission of low-delay cross-clock domain data can be realized.

The invention discloses a clock domain crossing circuit timing sequence closed-loop optimization method and system, and relates to the technical field of integrated circuit design, and the method comprises the steps: reading a circuit netlist and timing sequence constraints, recognizing a converged path, and carrying out the clustering analysis to form a plurality of path groups; establishing a time sequence analysis model, and dynamically calculating the maximum delay constraint of the data signal in the path group; matching and executing at least one time sequence optimization strategy for each path group; and carrying out closed-loop time sequence verification, retaining a legacy path set which does not meet the constraint, and repeatedly executing the time sequence optimization strategy until a convergence condition is reached or the maximum preset number of iterations is reached. According to the method disclosed by the invention, the cross-domain path needing to be optimized in the DMUX structure can be accurately positioned without manual intervention, so that the path identification efficiency is improved, constraint omission or grouping deviation caused by manual operation is avoided, design defects are reduced from the source, and the design reliability of a chip is improved.

An interface control device includes a clock domain crossing (CDC) circuit configured to receive a first signal synchronized with a first clock, and output a second signal corresponding to the first signal synchronized with a second clock, a demultiplexer configured to divide the second signal into a plurality of signals to generate configuration information, a configuration register configured to store the configuration information, and an interface controller configured to operate according to the configuration information stored in the configuration register.

A synchronizer with flip-flops has a reduced number of flip-flops coupled in series, receiving as an input data of a first clock domain and supplying as an output data in the second clock domain. The second clock signal is at a variable frequency adjusted to a target frequency, by a division factor. The flip-flops are timed by a clock signal subsampling the second clock signal by a factor k1. The subsampled clock signal is generated by a frequency divider propagating a pulse of the signal every k1 clock pulses, while keeping the edges aligned.

The present disclosure provides a method for transmitting a signal between a drive chip and a flash memory, and a drive chip. By means of an IOBUF, an APR directly transmits to a flash memory a control signal for reading / writing the flash memory. Upon receiving a read / write request, the flash memory feeds back the read / write request to the IOBUF. A feedback signal is registered for one clock cycle by means of a register inside the IOBUF to obtain a delayed signal, thereby reducing timing urgency of directly providing the feedback signal from the flash memory to the inside of the APR. The delayed signal is transmitted to an asynchronous FIFO memory of the APR for clock domain crossing processing to obtain an internal signal required by the APR. Clock domain crossing transmission of the signal output by the register of the IOBUF is performed by means of the asynchronous FIFO memory, avoiding a timing impact caused by an interactive routing delay between an APR circuit and an IOBUF circuit.

Systems and methods for communicating data via a multilane data link from a first clock domain a second clock domain, where the data streams of a multilane link are clocked into FIFO deskew buffers using clock signals that are recovered from the data streams themselves. Each data stream is clocked into the deskew buffer with the clock signal recovered from that data stream. The data is clocked out of the deskew buffers using the clock signal of a target clock domain so that the data streams clocked out of the deskew buffers are synchronized with each other and with the clock signal of the target clock domain (the target clock signal) to eliminate the need for a separate clock domain crossing buffer.

The invention relates to a frequency modulation synchronizer for clock domain crossing. A synchronizer with flip-flops has a reduced number of flip-flops coupled in series that receive data of a first clock domain as an input and provide data in a second clock domain as an output. The second clock signal is at a variable frequency that is adjusted to a target frequency by a frequency division factor. The flip-flop is clocked by a clock signal subsampled by a factor k1 on the second clock signal. The sub-sampled clock signal is generated by a frequency divider that propagates one pulse of the signal per k1 clock pulses while maintaining edge alignment.

The invention discloses a cross-clock domain data transmission method and a circuit system. The method comprises the following steps: firstly, obtaining data to be transmitted; then, based on the to-be-transmitted data, a PLL output phase adjustment function in the FPGA is utilized, the phase of a RESET emission clock is adjusted through fine grit, fine grit adjustment of the RESET pulse phase and the phase of a data sending clock of the analog-to-digital converter is achieved, and the target clock phase of data sending of the analog-to-digital converter is determined; wherein the target clock phase enables the data to be transmitted to be correctly sampled by a system clock domain of the FPGA. And low delay, stable and reliable transmission of clock domain crossing data is realized, and scene requirements of data transmission and the like with extremely high delay and reliability requirements are met.

The invention relates to a method, a computer implemented method and a storage medium configured to perform a method for optimizing clock domain crossing data transfer between a source domain and a destination domain, comprising: a. determining the data transfer capacity of the source domain (ds) and the data transfer capacity of the destination domain (dd); b. If ds > dd, transmitting an availability signal from the destination domain to the source domain via an intermediate metastability buffer; c. If ds < dd, transmitting a validity signal from the source domain to the destination domain via the intermediate metastability buffer.

Techniques and apparatuses are described for supporting multiple functions of a network-on-chip using a buffer. In example aspects, a network-on-chip (110) uses a credit-based protocol and facilitates communication between different subsystems (108) associated with different clock domains (206), different voltage domains 208, different power domains 210, different data widths (212), or some combination thereof. The network-on-chip (110) includes a buffer (118), which provides storage for credit management (214), storage for an asynchronous clock-domain crossing (216), and storage for data upscaling (218). While other network-on-chips or other system-on-chips can have individual storage elements to support each function, the buffer (118) acts as a single storage element capable of supporting each of these functions. With the buffer (118), the network-on-chip (110) can have a smaller footprint, can consume less power, and can have less latency compared to other network-on-chips that utilize multiple storage elements.

A clock domain crossing interface is described. The clock domain crossing interface includes a transmit clock domain and a receive clock domain using a different clock from the transmit clock domain. The clock domain crossing interface also includes a first-in-first-out (FIFO) buffer coupled between the transmit clock domain and the receive clock domain. The FIFO buffer to store ordered transactions sent from the transmit clock domain to the receive clock domain. The clock domain crossing interface further includes a transmit clock domain event transfer block to notify the receive clock domain of a new transaction pushed onto the FIFO buffer in the transmit clock domain. The clock domain crossing interface also includes a receive clock domain event transfer block to notify the transmit clock domain of a new transaction pulled from the FIFO buffer in the receive clock domain.

The invention discloses a chip system and a frequency conversion method based on a DDR coprocessor, and the method comprises the steps: defining an operation trigger point and a period duration of a main processor and a calculation coprocessor through a global clock generated by the DDR coprocessor, and guaranteeing that the read-write operation is strictly aligned with a clock edge; a built-in frequency conversion module of the DDR coprocessor responds to the request of the main processor, and the clock frequency is adjusted in real time by prefetching the proportion, so that the system automatically reconstructs a time sequence grid when the energy efficiency mode is switched; meanwhile, the self-starting module triggers an initialization process after a global clock is ready, and reliable guidance in a frequency conversion scene is guaranteed. According to the chip system, the clock domain crossing risk is eliminated from the source, and the system is endowed with millisecond-level dynamic frequency modulation capability.

The present invention provides a semiconductor device having two independent power domains: a first power domain and a second power domain. Different clock signals are applied to the respective circuits which are provided in the first and second power domains. The first and second power domains have a first storage unit and a second storage unit, respectively. When the semiconductor device enters a power-saving mode, the parameter of the first storage unit is maintained in the second storage unit, and then the first power domain is turned off. In the power-saving mode, the timing of each device in the second power domain is driven by the second clock signal, so as to solve the problem of clock domain crossing between different power domains. Therefore, the second power domain may use a second storage unit with a lower processing speed than the first storage unit.

The invention relates to a multi-channel hybrid coding transmission system, method, module and terminal based on an FPGA. The system comprises a multi-interface receiving module, a receiving interface data preprocessing module, a multi-interface sending module, a sending interface data preprocessing module, a security coding unit, a fault-tolerant unit and a system control unit which are arranged in the FPGA. After data is sent out from an upper computer and received by an interface in the FPGA, receiving clock domain crossing processing and encoding pre-processing are carried out on the data, data security encoding processing is carried out after completion, the processed data are sent to encoding post-processing, sending clock domain crossing processing is carried out after completion, and finally the data are sent back to the upper computer from an interface module. Compared with the prior art, the system, the method, the module and the terminal have the advantages of flexibility enhancement, expansibility breakthrough, instantaneity improvement, security optimization and fault tolerance rate improvement, and can well solve the technical defects in the prior art.

The accelerator may include one or more data processing units that perform deep learning operations in a neural network. The data processing unit includes a memory and a computing engine. A memory may include a bank and a clock domain crossover (CDC) buffer. Each bank may have its own CDC buffer (s). The memory banks may be grouped into memory bank groups. The memory may also include a group selection module and bank selection modules, each of which is associated with a different bank group. The group selection module may select a bank group for a data transfer request from a compute engine. A bank selection module of a selected bank group may select a bank from the selected bank group and store a data transfer request in a CDC buffer of the selected bank. A data transfer request may be sent from the CDC buffer to a selected bank.

An apparatus comprises buffer circuitry having a plurality of data entries each arranged to store a data block, where each data block has an associated data channel. The buffer circuitry is configured to receive data blocks from producer circuitry controlled by a first clock signal and to provide the data blocks to consumer circuitry controlled by a second clock signal. The apparatus also provides indicator storage having a plurality of indicator entries, wherein each data entry has an associated indicator entry and, for a given data entry storing a given data block, the associated indicator entry is configured to indicate the associated data channel for the given data block. Selection circuitry is provided to select a data entry from which to provide a data block to the consumer circuitry, by referencing the plurality of indicator entries.

The invention provides a clock domain crossing counter device and a clock domain crossing method thereof, and the device comprises a low n-bit clock domain crossing processing module which processes low n-bit clock domain crossing processing of a counter; the high m-bit clock domain crossing control module is used for generating high m-bit clock domain crossing control logic according to values before and after low n-bit clock domain crossing of the counter; the high m-bit clock domain crossing processing module is used for finishing high m-bit clock domain crossing of the counter based on control logic driving of the high m-bit clock domain crossing control module; and high m-bit data sent by the counter accumulator is input into the first high m-bit register of the module. According to the scheme, a handshake type cross-clock domain is adopted, high logic complexity of a large-bit-width counter is avoided, time sequence performance is improved, register resource consumption is reduced, and the area is optimized.

Clock domain crossing synchronization circuits and methods include generating a destination domain current buffer signal in a destination clock domain. The destination domain current buffer signal indicates a first or second data buffer in a source clock domain as a current buffer for use during a current data transfer cycle. The destination domain current buffer signal is synchronized and a source domain current buffer signal indicating the current buffer generated. A source data transfer request signal is generated based on the source domain current buffer signal and the source data transfer request signal synchronized to generate a destination domain data transfer request signal. Transfer of data between a memory in the destination clock domain is delayed to a subsequent data transfer cycle when the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

An accelerator may include one or more data processing units that perform deep learning operations in neural networks. A data processing unit includes a memory and a compute engine. The memory includes memory banks and clock domain crossing (CDC) buffers. Each memory bank has its own CDC buffer(s). The memory banks may be grouped into bank groups. The memory may also include a group selection module and includes bank selection modules, each of which is associated with a different bank group. The group selection module selects a bank group for a data transfer request from the compute engine. The bank selection module of the selected bank group may select a memory bank from the selected bank group and store the data transfer request in a CDC buffer of the selected memory bank. The data transfer request is transmitted to the selected memory bank from the CDC buffer.

The invention discloses an asynchronous dual-port memory and a real-time digital phase shifter system, the asynchronous dual-port memory is introduced into the real-time digital phase shifter system, and the asynchronous dual-port memory comprises a memory access time slot used for dynamically distributing a dual-port block RAM according to a data read-write task request, the controller is used for receiving a Gray code counter and issuing a stepping instruction of the Gray code counter and a cross-domain control instruction of the clock domain cross module; the Gray code counter is used for receiving a stepping instruction of the controller and outputting a Gray code address to the dual-port block RAM; the clock domain cross module is used for receiving a cross-domain control instruction and providing a synchronous access signal for the dual-port block RAM; and executing asynchronous read-write operation according to the Gray code address, the synchronous access signal and the allocated memory access time slot, and storing a dual-port block RAM of a phase and power data pair of the asynchronous read-write operation. The method has the characteristics of high data access efficiency, real-time performance and high precision.

A stacked Processing Near Memory (PNM) device, in order to achieve smooth clock domain crossing (CDC) between a stacked memory chip and a logic chip and to minimize a consumption of die area, can train a delay time of an asynchronous path for each bank of the memory chip and optimally control an output timing of received data for each bank in each corresponding FIFO in consideration of the delay time of each bank as a result of the training. The stacked PNM device may perform a CDC training method and a normal operation method.

A radio-frequency amplifier can have a radio-frequency input configured to receive a radio-frequency signal and a control input for receiving a control signal. The radio-frequency signal can be generated using a first group of digital-to-analog converters (DACs), whereas the control signal can be generated using a second set of DACs. Data intended for the first group of DACs can be fed through a first set of retiming circuits and a first crossbar circuit. Data intended for the second group of DACs can be fed through a second set of retiming circuits and a second crossbar circuit. A low skew clocking interface and constant latency control and clock domain cross circuits can be employed to ensure that data streams arriving at the first group of DACs are time aligned with data streams arriving at the second group of DACs.

A computing system can perform static verification operations on a circuit design with a first set of design constraints characterizing portions of an electronic device described by the circuit design and identify one or more violations associated with clock domain crossings in the circuit design. The computing system can analyze the circuit design and the first set of the design constraints to determine at least one of the violations associated with the clock domain crossings in the circuit design corresponds to the first set of the design constraints, and generate one or more additional design constraints to integrate into the first set of the design constraints based on the analysis of the circuit design and the first set of the design constraints. The computing system can re-perform the static verification operations on the circuit design based on a second set of the design constraints that includes the additional design constraints.