45 results about "Clock domain crossing" patented technology

The invention relates to the technical field of integrated circuits, and provides a clock domain crossing synchronization circuit and method based on a multiphase clock, and the circuit comprises a selector, an asynchronous clock synchronization module and a digital signal processor. Wherein serial data to be transmitted and a low-frequency clock are input into the selector, and the selector is used for outputting corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; the asynchronous clock synchronization module is used for outputting corresponding alignment data to the digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low-frequency clock; the asynchronous clock synchronization module is used for performing phase alignment on the RX parallel data and a clock of the digital signal processor; and the digital signal processor is used for carrying out data processing on the alignment data. According to the invention, stable transmission of low-delay cross-clock domain data can be realized.

The embodiment of the invention provides a clock domain crossing path checking method and device and a related device.The method comprises the steps that a clock domain crossing path set designed by a chip is obtained, and each clock domain crossing path in the clock domain crossing path set comprises a source clock domain and a target clock domain which are different in clock domain; the source clock domain and the target clock domain of each cross-clock-domain path are subjected to clock domain constraint, equivalent synchronous time sequence paths are obtained, and the source clock domain and the target clock domain of each equivalent synchronous time sequence path are from the same clock domain under the clock domain constraint; performing time sequence analysis on the equivalent synchronous time sequence path to obtain path delay information; and checking the corresponding cross-clock-domain path based on the path delay information of the equivalent synchronous time sequence path to obtain a check result of the cross-clock-domain path. According to the technical scheme provided by the embodiment of the invention, the path comprehensiveness and completeness when the time sequence analysis is carried out on the clock domain crossing path can be improved, and the time sequence analysis accuracy of the clock domain crossing path is improved.

The invention discloses a clock domain crossing circuit timing sequence closed-loop optimization method and system, and relates to the technical field of integrated circuit design, and the method comprises the steps: reading a circuit netlist and timing sequence constraints, recognizing a converged path, and carrying out the clustering analysis to form a plurality of path groups; establishing a time sequence analysis model, and dynamically calculating the maximum delay constraint of the data signal in the path group; matching and executing at least one time sequence optimization strategy for each path group; and carrying out closed-loop time sequence verification, retaining a legacy path set which does not meet the constraint, and repeatedly executing the time sequence optimization strategy until a convergence condition is reached or the maximum preset number of iterations is reached. According to the method disclosed by the invention, the cross-domain path needing to be optimized in the DMUX structure can be accurately positioned without manual intervention, so that the path identification efficiency is improved, constraint omission or grouping deviation caused by manual operation is avoided, design defects are reduced from the source, and the design reliability of a chip is improved.

A clock domain crossing (CDC) circuit receives a first data. The CDC circuit includes a first buffer and a second buffer. The first buffer includes a single-clock static random-access memory. The second buffer includes a plurality of data flip-flops. Logic coupled to the first buffer and the second buffer can determine that first buffer is not full at a first time. Responsive to the determination that the second buffer is not full at the first time, the processing logic can bypass the first buffer to write the first data to the second buffer according to the first clock domain. The processing logic can provide the first data as output from the second buffer according to the second clock domain.

A clock domain crossing interface is described. The clock domain crossing interface includes a transmit clock domain and a receive clock domain using a different clock from the transmit clock domain. The clock domain crossing interface also includes a first-in-first-out (FIFO) buffer coupled between the transmit clock domain and the receive clock domain. The FIFO buffer to store ordered transactions sent from the transmit clock domain to the receive clock domain. The clock domain crossing interface further includes a transmit clock domain event transfer block to notify the receive clock domain of a new transaction pushed onto the FIFO buffer in the transmit clock domain. The clock domain crossing interface also includes a receive clock domain event transfer block to notify the transmit clock domain of a new transaction pulled from the FIFO buffer in the receive clock domain.

This document describes systems and techniques directed at verifying, in a test environment, that an undefined digital logic signal is unlikely to cause functional impact on a system-on-chip. In various aspects, clock domain crossing (CDC) and reset domain crossing (RDC) results in an undefined digital value. Various paths through a circuit design that may generate an undefined value (e.g., not a value of zero or a value of one) during testing are identified. A signal injection circuit may be inserted into paths identified as possibly providing an undefined value. The signal injection circuit may be configured to inject an undefined signal into identified paths during testing. The injection of undefined signals within a circuit may simulate signal instability at identified paths. The testing of instability at the identified paths provides thorough analysis, which allows failures to be identified early in the design process.

Clock domain crossing synchronization circuits and methods include generating a destination domain current buffer signal in a destination clock domain. The destination domain current buffer signal indicates a first or second data buffer in a source clock domain as a current buffer for use during a current data transfer cycle. The destination domain current buffer signal is synchronized and a source domain current buffer signal indicating the current buffer generated. A source data transfer request signal is generated based on the source domain current buffer signal and the source data transfer request signal synchronized to generate a destination domain data transfer request signal. Transfer of data between a memory in the destination clock domain is delayed to a subsequent data transfer cycle when the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

The invention discloses a dynamic multi-clock domain soc chip signal observation device and method.The dynamic multi-clock domain soc chip signal observation device comprises a plurality of first selection modules, a plurality of second selection modules, a plurality of clock domain crossing signal splicing modules and a third selection module, the cross-clock-domain signal splicing module carries out cross-time-domain and splicing operation on the signals to be detected, and finally the third selection module carries out the last round of screening and sends the signals to a pad port for observation. Static signals, quasi-static signals and high-speed dynamic signals are processed in a unified mode, an additional high-speed IO port is not needed for achieving a debug function, and real-time observation can be conducted on clocks, control signals and data signals.

An interface control device includes a clock domain crossing (CDC) circuit configured to receive a first signal synchronized with a first clock, and output a second signal corresponding to the first signal synchronized with a second clock, a demultiplexer configured to divide the second signal into a plurality of signals to generate configuration information, a configuration register configured to store the configuration information, and an interface controller configured to operate according to the configuration information stored in the configuration register.

The invention relates to a clock domain crossing synchronization circuit and method for ensuring a correct data signal order. Clock domain crossing synchronization circuits and methods include generating a destination domain current buffer signal in a destination clock domain. The destination region current buffer signal indicates either the first data buffer or the second data buffer in the source clock domain as a current buffer used during a current data transfer period. The destination domain current buffer signal is synchronized and a source domain current buffer signal indicative of the current buffer is generated. A source data transfer request signal is generated based on the synchronized source domain current buffer signal and the source data transfer request signal to generate a destination domain data transfer request signal. When the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal, transfer of data between memories in the destination clock domain is delayed to a subsequent data transfer cycle.

The present invention relates to a system and method for queuing in custom instruction extension of a hardened processor (203) such as a RISC-V processor implemented on a System-on-Chip (SoC) fabric; which enables high performance for said RISC-V processor (203) when interacting with any custom accelerator (205) via custom instruction extension (207) due to the reduced latency in waiting for a response from said custom accelerator (205). The system and method of the present invention also facilities clock domain crossing between the high frequency hardened processor (203) and the lower frequency custom accelerator (205), thus simplifying the design requirements for the custom accelerator (205) to close the timing gap. Besides that, the system and method of the present invention also supports blocking and non-blocking implementations of the queueing capability without needing for updates to the register transfer level (RTL) design.

A synchronizer with flip-flops has a reduced number of flip-flops coupled in series, receiving as an input data of a first clock domain and supplying as an output data in the second clock domain. The second clock signal is at a variable frequency adjusted to a target frequency, by a division factor. The flip-flops are timed by a clock signal subsampling the second clock signal by a factor k1. The subsampled clock signal is generated by a frequency divider propagating a pulse of the signal every k1 clock pulses, while keeping the edges aligned.

An accelerator may include one or more data processing units that perform deep learning operations in neural networks. A data processing unit includes a memory and a compute engine. The memory may include memory banks and clock domain crossing (CDC) buffers. Each memory bank may have its own CDC buffer(s). The memory banks may be grouped into bank groups. The memory may also include a group selection module and bank selection modules, each of which is associated with a different bank group. The group selection module may select a bank group for a data transfer request from the compute engine. The bank selection module of the selected bank group may select a memory bank from the selected bank group and store the data transfer request in a CDC buffer of the selected memory bank. The data transfer request may be transmitted to the selected memory bank from the CDC buffer.

The present disclosure provides a method for transmitting a signal between a drive chip and a flash memory, and a drive chip. By means of an IOBUF, an APR directly transmits to a flash memory a control signal for reading / writing the flash memory. Upon receiving a read / write request, the flash memory feeds back the read / write request to the IOBUF. A feedback signal is registered for one clock cycle by means of a register inside the IOBUF to obtain a delayed signal, thereby reducing timing urgency of directly providing the feedback signal from the flash memory to the inside of the APR. The delayed signal is transmitted to an asynchronous FIFO memory of the APR for clock domain crossing processing to obtain an internal signal required by the APR. Clock domain crossing transmission of the signal output by the register of the IOBUF is performed by means of the asynchronous FIFO memory, avoiding a timing impact caused by an interactive routing delay between an APR circuit and an IOBUF circuit.

Clock domain crossing synchronization circuits and methods include generating a destination domain current buffer signal in a destination clock domain. The destination domain current buffer signal indicates a first or second data buffer in a source clock domain as a current buffer for use during a current data transfer cycle. The destination domain current buffer signal is synchronized and a source domain current buffer signal indicating the current buffer generated. A source data transfer request signal is generated based on the source domain current buffer signal and the source data transfer request signal synchronized to generate a destination domain data transfer request signal. Transfer of data between a memory in the destination clock domain is delayed to a subsequent data transfer cycle when the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

Systems and methods for communicating data via a multilane data link from a first clock domain a second clock domain, where the data streams of a multilane link are clocked into FIFO deskew buffers using clock signals that are recovered from the data streams themselves. Each data stream is clocked into the deskew buffer with the clock signal recovered from that data stream. The data is clocked out of the deskew buffers using the clock signal of a target clock domain so that the data streams clocked out of the deskew buffers are synchronized with each other and with the clock signal of the target clock domain (the target clock signal) to eliminate the need for a separate clock domain crossing buffer.

The invention relates to a frequency modulation synchronizer for clock domain crossing. A synchronizer with flip-flops has a reduced number of flip-flops coupled in series that receive data of a first clock domain as an input and provide data in a second clock domain as an output. The second clock signal is at a variable frequency that is adjusted to a target frequency by a frequency division factor. The flip-flop is clocked by a clock signal subsampled by a factor k1 on the second clock signal. The sub-sampled clock signal is generated by a frequency divider that propagates one pulse of the signal per k1 clock pulses while maintaining edge alignment.

The invention discloses a method for extracting a qualifier expression in a clock domain. The method comprises the following steps of: 1, extracting a data path when the clock domain of an integrated circuit is crossed; step 2, a qualier expression is extracted; step 3, for each data path, generating a table assertion, and ensuring that the output signal of the source register is kept stable when the qualifier expression is valid; and 4, binding all assertions to the circuit design, carrying out simulation verification, and if the assertion fails, returning to the step 2 to newly extract the qualier expression until the assertion is successful, and extracting a correct qualier expression. According to the method, the qualifier expression can be automatically extracted, the stability of the data is ensured, and the metastable state is avoided.

The utility model relates to a clock domain crossing synchronization circuit and an electronic system. Clock domain crossing synchronization circuits and methods include generating a destination domain current buffer signal in a destination clock domain. The destination region current buffer signal indicates either the first data buffer or the second data buffer in the source clock domain as a current buffer used during a current data transfer period. The destination domain current buffer signal is synchronized and a source domain current buffer signal indicative of the current buffer is generated. A source data transfer request signal is generated based on the synchronized source domain current buffer signal and the source data transfer request signal to generate a destination domain data transfer request signal. When the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal, transfer of data between memories in the destination clock domain is delayed to a subsequent data transfer cycle.

The invention discloses a cross-clock domain data transmission method and a circuit system. The method comprises the following steps: firstly, obtaining data to be transmitted; then, based on the to-be-transmitted data, a PLL output phase adjustment function in the FPGA is utilized, the phase of a RESET emission clock is adjusted through fine grit, fine grit adjustment of the RESET pulse phase and the phase of a data sending clock of the analog-to-digital converter is achieved, and the target clock phase of data sending of the analog-to-digital converter is determined; wherein the target clock phase enables the data to be transmitted to be correctly sampled by a system clock domain of the FPGA. And low delay, stable and reliable transmission of clock domain crossing data is realized, and scene requirements of data transmission and the like with extremely high delay and reliability requirements are met.

The invention relates to a method, a computer implemented method and a storage medium configured to perform a method for optimizing clock domain crossing data transfer between a source domain and a destination domain, comprising: a. determining the data transfer capacity of the source domain (ds) and the data transfer capacity of the destination domain (dd); b. If ds > dd, transmitting an availability signal from the destination domain to the source domain via an intermediate metastability buffer; c. If ds < dd, transmitting a validity signal from the source domain to the destination domain via the intermediate metastability buffer.

Techniques and apparatuses are described for supporting multiple functions of a network-on-chip using a buffer. In example aspects, a network-on-chip (110) uses a credit-based protocol and facilitates communication between different subsystems (108) associated with different clock domains (206), different voltage domains 208, different power domains 210, different data widths (212), or some combination thereof. The network-on-chip (110) includes a buffer (118), which provides storage for credit management (214), storage for an asynchronous clock-domain crossing (216), and storage for data upscaling (218). While other network-on-chips or other system-on-chips can have individual storage elements to support each function, the buffer (118) acts as a single storage element capable of supporting each of these functions. With the buffer (118), the network-on-chip (110) can have a smaller footprint, can consume less power, and can have less latency compared to other network-on-chips that utilize multiple storage elements.

Systems and methods for communicating data via a multilane data link from a first clock domain to a second clock domain, where the data streams of a multilane link are clocked into FIFO deskew buffers using clock signals that are recovered from the data streams themselves. Each data stream is clocked into the deskew buffer with the clock signal recovered from that data stream. The data is clocked out of the deskew buffers using the clock signal of a target clock domain so that the data streams clocked out of the deskew buffers are synchronized with each other and with the clock signal of the target clock domain (the target clock signal) to eliminate the need for a separate clock domain crossing buffer.

The utility model relates to the technical field of signal processing, in particular to a clock module for a data link communication processing device, which comprises a clock selection circuit, a first clock circuit and a second clock circuit. The clock selection circuit is electrically connected with the FPGA circuit, the first clock circuit and the second clock circuit respectively; the first clock circuit is connected with the data receiving circuit, the second clock circuit is connected with the data transmitting circuit, the clock selection circuit is connected with a plurality of clock sources, including the first clock circuit and the second clock circuit, so that the clock module can select proper clock signals from different clock sources; and the data is distributed to the data receiving and transmitting circuit according to needs, so that the flexibility and adaptability of the system are improved, the clock domain crossing problem is avoided, and the performance of the data link communication processing module is enhanced.

A clock domain crossing interface is described. The clock domain crossing interface includes a transmit clock domain and a receive clock domain using a different clock from the transmit clock domain. The clock domain crossing interface also includes a first-in-first-out (FIFO) buffer coupled between the transmit clock domain and the receive clock domain. The FIFO buffer to store ordered transactions sent from the transmit clock domain to the receive clock domain. The clock domain crossing interface further includes a transmit clock domain event transfer block to notify the receive clock domain of a new transaction pushed onto the FIFO buffer in the transmit clock domain. The clock domain crossing interface also includes a receive clock domain event transfer block to notify the transmit clock domain of a new transaction pulled from the FIFO buffer in the receive clock domain.

The invention discloses a chip system and a frequency conversion method based on a DDR coprocessor, and the method comprises the steps: defining an operation trigger point and a period duration of a main processor and a calculation coprocessor through a global clock generated by the DDR coprocessor, and guaranteeing that the read-write operation is strictly aligned with a clock edge; a built-in frequency conversion module of the DDR coprocessor responds to the request of the main processor, and the clock frequency is adjusted in real time by prefetching the proportion, so that the system automatically reconstructs a time sequence grid when the energy efficiency mode is switched; meanwhile, the self-starting module triggers an initialization process after a global clock is ready, and reliable guidance in a frequency conversion scene is guaranteed. According to the chip system, the clock domain crossing risk is eliminated from the source, and the system is endowed with millisecond-level dynamic frequency modulation capability.

The present invention provides a semiconductor device having two independent power domains: a first power domain and a second power domain. Different clock signals are applied to the respective circuits which are provided in the first and second power domains. The first and second power domains have a first storage unit and a second storage unit, respectively. When the semiconductor device enters a power-saving mode, the parameter of the first storage unit is maintained in the second storage unit, and then the first power domain is turned off. In the power-saving mode, the timing of each device in the second power domain is driven by the second clock signal, so as to solve the problem of clock domain crossing between different power domains. Therefore, the second power domain may use a second storage unit with a lower processing speed than the first storage unit.

The invention relates to a multi-channel hybrid coding transmission system, method, module and terminal based on an FPGA. The system comprises a multi-interface receiving module, a receiving interface data preprocessing module, a multi-interface sending module, a sending interface data preprocessing module, a security coding unit, a fault-tolerant unit and a system control unit which are arranged in the FPGA. After data is sent out from an upper computer and received by an interface in the FPGA, receiving clock domain crossing processing and encoding pre-processing are carried out on the data, data security encoding processing is carried out after completion, the processed data are sent to encoding post-processing, sending clock domain crossing processing is carried out after completion, and finally the data are sent back to the upper computer from an interface module. Compared with the prior art, the system, the method, the module and the terminal have the advantages of flexibility enhancement, expansibility breakthrough, instantaneity improvement, security optimization and fault tolerance rate improvement, and can well solve the technical defects in the prior art.

The accelerator may include one or more data processing units that perform deep learning operations in a neural network. The data processing unit includes a memory and a computing engine. A memory may include a bank and a clock domain crossover (CDC) buffer. Each bank may have its own CDC buffer (s). The memory banks may be grouped into memory bank groups. The memory may also include a group selection module and bank selection modules, each of which is associated with a different bank group. The group selection module may select a bank group for a data transfer request from a compute engine. A bank selection module of a selected bank group may select a bank from the selected bank group and store a data transfer request in a CDC buffer of the selected bank. A data transfer request may be sent from the CDC buffer to a selected bank.

The invention provides a clock domain crossing signal synchronization device and method and a consumable chip. The clock domain crossing signal synchronization device comprises a trigger, a signal acquisition terminal of the trigger receives a target clock signal, and a clock terminal of the trigger receives a reference clock signal; the clock domain crossing signal synchronization device further comprises a first edge detection circuit, the first edge detection circuit receives a target clock signal and detects a first edge signal of the target clock signal, and the first edge detection circuit outputs a signal to the first AND gate; the clock domain crossing signal synchronization device further comprises a first time delay circuit, a second time delay circuit and a phase inverter, the first time delay circuit receives a reference clock signal and then outputs the reference clock signal to the phase inverter, the phase inverter outputs a signal to the first AND gate, and the first AND gate outputs a signal to a first input terminal of the first latch; the second time delay circuit receives the signal output by the first time delay circuit and outputs the signal to the second input terminal of the first latch after time delay, and the output terminal of the first latch outputs the signal to the reset terminal of the trigger. The invention further provides a working method of the device and the consumable chip with the device. According to the invention, the metastable state of the synchronous clock signal can be avoided, and the synchronization efficiency of the clock signal across the clock domain can be improved.