The invention provides an FPGA (
Field Programmable Gate Array) accelerator card with a hard synchronization function, which comprises an
FPGA chip used for
processing a computing task issued by a universal processor
system, the
FPGA chip is provided with a storage module and a power supply module, and external interfaces comprise a PCIE (
Peripheral Component Interface Express) interface, a
QSFP (Quad Small Form-factor Pluggable) optical interface, an SMA (
Shape Memory Alloy) interface and an RS422 interface. And the PCIE interface and the
QSFP optical interface are respectively interconnected with the high-speed port of the FPGA module at a high speed. And the storage module, the SMA interface and the RS422 interface are all connected to a general I / O pin of the FPGA. According to the invention, the
synchronization signal from the external device can be received, and the PCIE message interrupt is sent to the universal processor
system end through the PCIE interface, so that the synchronization time base establishment between the universal processor
system and the acceleration card external device is realized. And the message interruption of the PCIE is used as a strong real-
time synchronization mode, so that the accurate control on the external equipment can be realized. Meanwhile, the PCIE module and the
QSFP optical interface can achieve high-speed
data transmission, and the acceleration card supporting strong real-
time processing is formed by combining high-density
parallel computing of the FPGA.