394 results about "Pci interface" patented technology

A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. First and second PCI local buses are connected to the system bus through a PCI host bridge. The first and second PCI local buses have sets of in-line electronic switches, dividing the PCI local buses into PCI local bus segments supporting a plurality of PCI peripheral component slots for connecting PCI devices. The sets of in-line electronic switches are open and closed in accordance with bus control logic within the PCI host bridge allowing up to fourteen or more PCI peripheral component slots for connecting up to fourteen PCI devices to have access through a single PCI host bridge to the system bus. An internal PCI-to-PCI bridge is provided to allow a PCI device to share data with another PCI device as peer-to-peer devices across the first and second PCI local bus segments.

The data rate at which DMA transactions are processed by a General Purpose Computer System can be significantly improved by directing housekeeping type transactions directly to the CPU bus and by directing data type transactions directly to Shared Memory. By assigning memory address ranges to particular I/O devices and by programming PCI Interface Logic on a System Controller to detect these ranges and to direct DMA requests directly to either the CPU bus or to the Memory Controller depending upon the address range detected, the speed with which DMA transactions can be processed is enhanced.

A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. First and second PCI local buses are connected to the system bus through a PCI host bridge. The first and second PCI local buses have sets of in-line electronic switches, dividing the PCI local buses into PCI local bus segments supporting a plurality of PCI peripheral component slots. The sets of in-line electronic switches are open and closed in accordance with bus control logic within the PCI host bridge allowing up to fourteen PCI peripheral component slots to have access through a single PCI host bridge to the system bus.

The invention discloses a 1553B bus monitor. A local bus module of the 1553B bus monitor connected with a PCI bus comprises a PCI master equipment unit and a PCI slave equipment unit, wherein the PCI master equipment unit and the PCI slave equipment unit provide a 32-bit PCI interface together; the PCI slave equipment unit supports passive access; and the PCI master equipment unit realizes direct memory transmission and actively transmits data to memory space pre-allocated by a central processing unit (CPU). This invention also discloses a 1553B bus system with the 1553B bus monitor. The 32-bit 1553B bus monitor adopting PCI interface design can be conveniently hung to the PCI bus outside a microprocessor, has processing bandwidth of 32 bits, integrates DMA modules, can automatically initiate data transmission after CPU configuration, supports a BURST transmission mode, and greatly improves the efficiency of data transmission.

The invention discloses a gigabit Ethernet field bus communication device based on an FPGA (Field Programmable Gate Array). The device comprises an ARM (Asynchronous Response Mode)/DSP (Digital Signal Processor) expansion interface, an FPGA module, a PHY (Physical Layer) chip and a field bus communication interface and is characterized in that an electrical signal or an optical signal on a field bus is converted into a differential signal through a field bus interface; data is downloaded into the FPGA module through the gigabit PHY chip; and the FPGA module is used for receiving and analyzing the downloaded data and then transmitting the analyzed data to an ARM or a DSP connected with the ARM/DSP expansion interface through the ARM/DSP expansion interface for processing; the data processed by the ARM/DSP is packaged into a data frame by the FPGA module and is then converted into the differential signal through the gigabit PHY chip; and the differential signal is converted into the electrical signal or the optical signal through the field bus communication interface to be transmitted onto a the field bus. The gigabit Ethernet field bus communication device has the beneficial effects that the data transmission rate of 1000 Mbps can be realized, the communication with external equipment with the PCI (Peripheral Component Interconnect) interface can be realized, and different controllers can be externally connected according to the actual needs, the flexibility is high, and the gigabit Ethernet field bus communication device can be flexibly applied to real-time monitoring and communication of an industrial control field.

The invention discloses a device and a method of simulation and testing of a finished car controller of a hybrid power car. Due to the fact that a PCI interface and a micro processor are used for communication, the device of simulation and testing of the finished car controller of the hybrid power car has the advantages of being good in reliability, high in transmission rate of data, and good in extendibility. Due to the fact that a mathematical model of a power unit is used for simulating a working state of an actual power unit, cost of a system is greatly reduced. The device of simulation and testing of the finished car controller of the hybrid power car comprises a micro processor unit, a PCI bus processing unit, a display unit and an interface board card. The display unit and the PCI bus processing unit are respectively connected with the micro processor unit. The interface board card is connected with the PCI bus processing unit through a PCI bus. The interface board card is connected with the finished car controller to be detected. Therefore, configuration can be conveniently carried out on the structure of a finished car, relevant power unit parameters, an operation spectrum/a road spectrum, and port attributes of an interface board, and the system is good in generality. When the device and the method of simulation and testing of the finished car controller of the hybrid power car are used for testing a hybrid power finished car controller, a test period is shortened, test cost is reduced, and test results are good in stability and high in accuracy.

The invention relates to a distribution welding point quality detection system and a relative method, belonging to welding technical field. The system comprises a detection host computer, a controller local network bus and a distribution node lower computer, wherein the detection host computer comprises a PC and a controller local network bus communication adaptive card which are connected via a PCI interface, the controller local network bus communication adaptive card is connected with each distribution node lower computer via a controller local network bus. The inventive method comprises that each lower computer online real-time extracts the impression of welding point to be sent to the controller local network bus, the PC sends the welding point match change information caused by the change of servo welding gun position to a lower computer of relative ID number, real-time refreshes the standard base of the distribution node lower computer that judges the welding point, and returns the off-grade welding point counter. The inventive system and method have high reliability, strong bus correct function, better real-time property, remote transmission distance and better expansibility.

The invention discloses a PCI integrated circuit board device used for ARINC429, mainly comprising an FPGA module, an ARINC429 interface chip, two ARINC429 protocol processing chips, two ARINC429 signal output linear drive chips and a power switching circuit. The FPGA chip is used for realizing PCI interface protocol and completing information interaction and control of a host computer and the board; the FPGA chip executes instruction of the host computer, initializes the ARINC429 interface chip and realizes control and caching of sending and receiving data to realize independent four receiving and two sending function and data sending rate adjustable function. The invention is flexible in configuration, the sending rate is adjustable and is wide in adjustable range, circuit construction is simple, processing cost of the circuit board is low, and different requirements of ARINC429 communication can be completed only by modifying FPGA software without changing hardware, thus the invention has strong commonality and flexibility.

The invention relates to the technical field of space-time consistency of all simulation real objects in a network, and discloses a high-precision network time unifying device and method. The device employed by the method comprises a time server and a client. The time server is connected with the client through the network, and the time server is formed by the connection of a PCI interface and a PCI time unifying demodulation card. A radio frequency input end of the PCI time unifying demodulation card is connected with a GPS/BD dual-mode antenna through a signal line. A data input end of the PCI time unifying demodulation card is connected with an IRIG-B time code signal source through a signal line. The high-precision network time setting and network frequency modulation enables the time bias of each network client to be less than or equal to 1ms. The device can provide in-network overall consistent natural time or simulation time for a plurality of application progresses or users, and can achieve the accelerating or slowing of the in-network overall simulation time. The device is low in cost, and is small in network bandwidth occupation and computer resource occupation.

An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system includes a first PCI interface, a second PCI interface, a PCI bridge serving as a bridge between the first PCI interface and the second PCI interface, and a control circuit for controlling an interrupt signal. The PCI bridge recognizes a message signal interrupt issued from the first PCI interface to the second PCI interface and transfers the message signal interrupt to the control circuit, and the control circuit is provided with an interrupt conversion unit for converting the message signal interrupt into an interrupt signal and outputting it via a signal line.

The invention discloses a PCI interface protocol based array expandable data collection system realized by adopting an FPGA (field programmable gate array). The system comprises a plurality of identical analog signal collection boards. Each of the boards comprises a controller module, a multipath ADC module, a power supply module and a PCI bridging chip, wherein the controller module is composed of an FPGA chip and an SRAM chip, and used for controlling the sampling process, generating between-board bus signals and controlling caching and transmission of data; the multipath ADC module is composed of 64 paths of single-path ADC modules with the same structure, and used for converting analog signals into digital signals and transmitting the data to the controller module; the power supply module is composed of two identical power supply sub-modules, and used for providing stable and low-noise power for the chips; and the PCI bridging chip is used for realizing communication between the analog signal collection boards and an upper computer through a PCI bus. The PCI interface protocol based array expandable data collection system realizes sampling control of a multipath ADC and control of data flows by using the FPGA, and greatly increases the flexibility and the reliability of the design.

The invention provides a signal-processing board, which comprises a plurality of FPGA processing nodes, an FPGA main control module, a PCI interface module, a clock module and a power supply module, wherein the plurality of FPGA processing nodes are interconnected by an interconnection bus in a totally communicated topological structure and the interconnection bus is used for transmitting a high-speed data signal; the FPGA main control module is interconnected with the plurality of FPGA processing nodes through a shared bus which is used for transmitting a control signal; the PCI interface module is connected with the FPGA main control module through a local bus; the clock module is connected with the FPGA main control module, controlled by the main control module and used for supplying aworking clock to the signal-processing board; and the power supply module is used for supplying a voltage required by the signal-processing board. The topological structure of the plurality of FPGA processing nodes of the signal-processing board is flexible and the reconfiguration of the interconnection structure can be implemented according to specific application.

The invention relates to a UWB radar signal simulator based on FPGA, comprising a PC104 interface module, an RAM module, an FPGA module and a high-speed DAC module; the PC104 interface module completes data transmission with a host with PC104 mode by a PCI protocol; the RAM module adopts six ZBT-SRAMs with the bit width of 32 as data cache; the FPGA module adopts Virtex-4 series of product XC4VLX40 offered by Xilinx company and comprises a PCI interface control module, a RAM control module, a high-speed DAC control module and a radar waveform control module; the high-speed DAC control module selects AD9736 of ADI company; the interconnection of all the modules is realized by control modules in the FPGA module, the PC104 interface control module completes butting joint of the FPGA module and the PC104 interface module; data generated by controlling a host computer is transmitted to the inner part of the FPGA module from the PC 104 interface module; the RAM control module completes butting joint of the FPGA module and the RAM module so as to realize the transmission of data between the FPGA and the ZBT-SRAM; and the high-speed DAC control module completes butting joint of the FPGA module and the high-speed DAC module and controls the high-speed DAC module to generate various radar waveforms.

The IP kernel simulating verification platform based on PCI bus includes crystal vibrator, DC voltage regulator, FPGA, programming interface, SDRAM and PCI interface. The verification process includes describing IP kernel system in Verilog HDL language, interconnecting the top layer simulating modules with PCI bus, interconnecting hardware modules with internal bus the same as that in SoC inside the chip, embedding verified IP kernel into the verification platform, and controlling the platform to test IP kernel in PC. The present invention has verification platform with simple structure and convenient use, and verification process capable of simulating effectively SoC environment of IP, utilizing FPGA and PC in the hardware verification of IP, real-time creating test data for IP kernel to test and real-time accessing the register and memory inside IP kernel to obtain the verification finishing data.

A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge. Each of the primary bridge and secondary bridge include parallel/serial transceivers for converting parallel data generated on the first PCI bus and second PCI bus, respectively, to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first PCI bus and second PCI bus, respectively. The primary bridge and the secondary bridge collectively implement a PCI-PCI bridge register set.

The invention discloses a video information encryption and video terminal security certification system, certification method, and application. The system includes a security video monitoring terminal module and a security video access gateway module, the security video monitoring terminal module is provided with a security chip embedded into an IP camera or an NVR to realize the commercial cipher SM1 algorithm so as to realize the data encryption transmission and identity authentication between the security video monitoring terminal module and the security video access gateway module, the security video access gateway module includes an access gateway module, a video digital certificate module, an access certification module and a commercial cipher hardware encryption card based on the PCI interface, and the security video access gateway module establishes a video monitoring terminal hardware characteristic information database to guarantee that only the registered legal video monitoring terminal can access the security video access gateway module. The certification system is fewer in equipment, safe and efficient, convenient to implement, and low in cost, can guarantee the security of video information and the transmission efficiency of video information, and has the wide application prospect.

An internal and external system of computer shared by multiuser consists of a multiuser operation system, host board, central processor, internal memory and external storage. It is featured as forming said host board by multiple USB interface, USB controller, multiple PCI interface, PCI controller and a shared control unit including an input unit control device, a display output control unit, a resource distribution memory unit and multiuser bottom layer analog core. The method of utilizing said system is also disclosed.