305 results about "System bus" patented technology

Embodiments of the present disclosure provide a data transmission method, a data link layer, a chip interconnection interface, and an electronic device. The data transmission method is applied to the data link layer of the chip interconnection interface, the data link layer communicates with the system bus and the physical layer, the system bus operates in a first clock domain, and the physical layer operates in a second clock domain or in a second clock domain and a third clock domain. The method includes: the data link layer performs packet processing on the first data received from the system bus to obtain second data, and provides the second data to the physical layer; or, the data link layer performs unpacking processing on the third data received from the physical layer to obtain fourth data, and provides the fourth data to the system bus, wherein the data link layer partially operates in the third clock domain, and the first clock domain is different from the second clock domain and the third clock domain, the first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal.

The invention relates to the technical field of integrated circuit design, computer system structures and embedded systems, in particular to a high-real-time interrupt management system and method based on an RISC-V. The system comprises an improved platform-level interrupt controller and an optimized processor internal interrupt processing unit. The system and the method are in tight coupling cooperative work through a special interruption field interface and a system bus, and the system further comprises a core local interrupter, an SRAM, an APB bus matrix and other components. The improved platform-level interrupt controller is responsible for sampling, gating, arbitration, flow control and direct memory access transmission of external interrupt, and a plurality of functional modules are arranged in the improved platform-level interrupt controller; an interrupt processing unit in the processor is responsible for hardware handshake, vector jump, nested control and tail biting mechanism implementation. Through hardware field management, multi-level priority arbitration, hardware nesting and tail biting mechanisms, delay and overhead caused by software intervention in a traditional architecture are eliminated, nanosecond response is achieved, the system throughput rate is increased, the software development threshold is lowered, and the method is suitable for strong real-time scenes.

The invention belongs to the technical field of agricultural picking robot control, and provides an apple picking robot control method based on multi-sensor fusion, which comprises the following steps: deploying an RGB-D camera, a laser radar and a touch sensor, cooperatively collecting data and issuing the data to a system bus, and carrying out timestamp alignment, denoising processing and fusion; the method comprises the following steps: registering collected data to a unified robot coordinate system; establishing a voxel grid to set a voxel state; mapping to form a three-dimensional occupied grid model; obtaining a visibility index according to an RGB-D segmented region; performing weighted fusion in combination with the 3D point cloud set to obtain a fruit position; the method comprises the following steps: generating a motion feasible region by utilizing a three-dimensional occupied grid model, generating candidate poses by fitting a spherical angle increment, traversing the poses to carry out collision judgment, solving a joint track, calculating a quality index and a corresponding fusion weight through real-time sensing data, and carrying out weight adjustment and parameter correction according to a corresponding problem.

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an FPGA software and hardware cooperation testing platform based on a BFM. The test platform is formed by connecting a BFM with a Testbench, an AXI bus, an off-chip DDR and a DUT. The test process comprises the steps that the Testbench issues parameters through a transaction function interface, the BFM reads an excitation vector from the off-chip DDR / on-chip BRAM through an Avalon main interface, adaptive transmission of a system bus clock domain and a DUT clock domain is completed through double asynchronous FIFO (SNDfifo / RECfifo), and signal level interaction with the DUT is achieved through a pin protocol interface; the state machine dynamically switches long and short simulation modes according to the vector length, and drives the output vector to be written back and stored; the error monitoring unit monitors data flow faults in the whole process and outputs seven types of error reporting codes. The simulation equivalent frequency reaches a 10 megahertz level, and the method is suitable for efficient verification of the digital IC.

The invention provides bus hardware security monitoring equipment and a monitoring method based on an embedded system, master control equipment and slave equipment on a bus are connected with an intermediate control module, a bus monitoring module comprises a lightweight hash algorithm module and a DM module, all the master control equipment and slave equipment on the bus are connected with the input end of each channel, and the input end of each channel is connected with the corresponding channel. The outputs of all the channels are summarized to the interrupt management unit, the interrupt management unit serves as the output end of the bus monitoring module and is connected with the DMA, each channel comprises a monitoring selection unit, an access selection unit and a counting comparison unit, and an address range is set for each channel. Corresponding interrupt information is generated by monitoring the integrity abnormal behavior of a specific bus access sequence occurring in a system bus in the SoC security program running process. In a low-power-consumption application scene, the security of the embedded SoC can be improved, and key information is protected from being stolen and damaged.

The invention relates to the technical field of artificial intelligence and computer hardware, and discloses an artificial intelligence calculation optimization system and method based on deep learning, and the system comprises a main calculation server node, a heterogeneous calculation acceleration module, a high-speed interconnection and storage module, and a uniform resource management and scheduling module. The main computing server node is connected with the heterogeneous computing acceleration module and the high-speed interconnection and storage module through PCIe buses, and the uniform resource management and scheduling module is integrated in the main computing server node and communicates with each hardware component through a system bus. Through integration of a main computing server node, a heterogeneous computing acceleration module, a high-speed interconnection and storage module and a uniform resource management and scheduling module, efficient execution of a deep learning computing task and optimal utilization of resources are realized; the efficient and stable execution of the deep learning calculation task is realized, and powerful support is provided for the development of the artificial intelligence technology.

The invention provides a multi-protocol configurable interface circuit. The multi-protocol configurable interface circuit comprises a plurality of channel modules, a plurality of counter modules, an input / output module and a configuration register, the channel module comprises a state machine, a shift register and a cache module. The configuration register obtains configuration information through the system bus, and the configuration information comprises which protocol is selected. The counter module generates a shift signal required by a shift register in the channel module according to the configuration information; the input and output module selects the corresponding pins according to the configuration information and determines the function of each pin; and the channel module determines the mode of each channel and the required state of the state machine according to the configuration information to complete data transmission of the selected protocol. According to the invention, a hardware design which focuses on realizing clock and data transmission by matching a state machine state transition and a shift register with a cache module is adopted, so that software intervention and CPU occupation are reduced, and the overall efficiency is improved; hardware resources are reduced, and hardware flexibility is improved.

A transmitting module. The transmitting module has a first transmission stage for generating transmission currents for a first signal to be transmitted onto a bus of a serial bus system, a second transmission stage for generating transmission currents for a second signal to be transmitted onto the bus as a signal that is differential to the first signal, a third transmission stage for generating transmission currents for the first signal, and a fourth transmission stage for generating transmission currents for the second signal. The first to fourth transmission stages are connected in a full bridge. The first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series. Each of the first to fourth transmission stages has at least two current stages, connected in parallel with one another. Each of the at least two current stages has a switchable resistor.

The invention provides a simulation integration method and system for an FPGA communication module. The simulation integration method comprises the following steps that S1, an IP source code of the FPGA communication module is converted into an FPGA simulation module code of a C + + language; s2, based on the FPGA simulation module code, performing interface adaptation on a system bus access part for accessing an FPGA communication module in the all-digital simulation system; s3, introducing another module which is completely the same as the FPGA communication module as a symmetric module, and performing transceiving interface cross connection on the symmetric module and the FPGA communication module; and S4, performing interface adaptation on the communication data receiving side of the symmetric module according to a bus access mode in the full-digital simulation system. The FPGA module simulation is based on the source code of the FPGA, so that the accuracy of the FPGA simulation behavior is improved.

A system on chip (SoC) for testing a component in a system during runtime includes a plurality of functional components; a system bus for allowing the plurality of functional components to communicate with each other; one or more wrappers, each connected to one of the plurality of functional components; and an in-system component tester (ICT). The ICT monitors, via the wrappers, states of the functional components; selects, as a component under test (CUT), at least one functional component in an idle state; tests, via the wrappers, the selected at least one functional component; interrupts the testing step with respect to the selected at least one functional component, based on a detection of a collision with an access from the system bus to the selected at least one functional component; and allows a connection of the at least one functional component to the system bus, based on the interrupting step.

The utility model discloses a nuclear power station master control room architecture based on a DCS. The nuclear power station master control room architecture comprises a security-level DCS, a non-security-level DCS and a backup panel. The backup panel is provided with a first security level control display device, the non-security level DCS comprises a work station, and the work station is provided with a second security level control display device, a non-security level control display device and a conventional monitoring instrument; the safety-level DCS comprises an equipment interface cabinet, a safety bus, a data transmission cabinet, a reactor protection cabinet and a safety-level system bus which are in communication connection in sequence; the non-security-level DCS further comprises a field control cabinet and a server. Compared with an onshore nuclear power station master control room in the related technology, the nuclear power station master control room architecture based on the DCS reduces a whole set of diversified driving system equipment, and integrates diversified driving functions into a work station for realization. A man-machine interface of the master control room is simplified, the human factor risk is reduced, meanwhile, the requirement for the building space is lowered, and reference is provided for the design of the master control room arranged in a compact mode.

In a processing system, a conversion circuit coupled to a system bus generates a flow control unit (FLIT) and provides the FLIT to a link interface circuit for transmission over an external link. The external link may be a peripheral component interface (PCI) express (PCIe) link coupled to an external device comprising a cache or memory. The conversion circuit generates the FLIT, including write information based on the write instruction, metadata associated with at least one cache line, and cache line chunks, including bytes of a cache line. The cache line chunks may be chunks of one of the at least one cache line. Including the metadata in the FLIT avoids separately transmitting the at least one cache line and the metadata over the external link, which improves performance compared to generating separate transmissions. In some examples, the FLIT corresponds to a compute express link (CXL) protocol FLIT.

The invention discloses a vehicle information display method, a system-on-chip, electronic equipment, a storage medium and a program product, and is applied to the system-on-chip, the system-on-chip comprises a CPU, a GPU and a memory unit which are mutually connected through a system bus; the method comprises the steps that a CPU transmits vehicle information obtained from the outside to a memory unit through a system bus, so that a GPU reads the vehicle information, performs 3D rendering processing and outputs and displays the vehicle information; when the GPU breaks down, the CPU generates two-dimensional display information at least according to the vehicle information and outputs and displays the two-dimensional display information. According to the embodiment of the invention, when the GPU breaks down, the CPU takes over the display processing of the vehicle information, and carries out the two-dimensional display processing and output display of the vehicle information in a simplified drawing mode, so that the output display function of the vehicle information is completed, and the user experience is improved. And negative effects caused by excessive occupation of CPU resources when 3D rendering processing is carried out on the vehicle information are also avoided.

A simple configuration aims to reduce MCU vulnerabilities. [Solution] The control device 10 includes an MCU 20. The MCU 20 has a CPU 22, a system bus 26, a storage device 28, and an address translation device 24 that translates addresses between the CPU address space of the CPU 22 and the system bus address space of the system bus 26 in accordance with translation rules set in a special function register 24A. The MCU 20 starts up in an unrestricted mode in which all addresses in the CPU address space are available, and after startup, when a predetermined condition is met, it switches to a restricted mode in which only a portion of the addresses in the CPU address space are available. The special function register 24A allows the translation rules to be set and read when in the unrestricted mode, and does not allow the translation rules to be set or read when in the restricted mode.

The utility model relates to an actuator power supply control circuit and a robot. The actuator power supply control circuit comprises a control circuit used for supplying power to a boost circuit; the first end of the booster circuit is connected with the control circuit, the second end of the booster circuit is connected with the slow start circuit, and the booster circuit is used for receiving the output voltage of the control circuit and boosting the output voltage to obtain boosted voltage; and the slow start circuit is used for receiving the boosted voltage and controlling the slow start time of the actuator power supply. By adopting the actuator power supply control circuit, the problem of transient drop of the system bus voltage caused when a plurality of actuator power supplies are started at the same time can be avoided, and the reliability of the system is further guaranteed. And meanwhile, stable operation of the actuator can be realized on the basis of not additionally increasing the system power supply capacity, and the energy efficiency loss is reduced.

This application discloses a valve island diagnostic method, control system, bus valve island, and storage medium, relating to the field of electrical control. The method includes: acquiring the real-time power signal of the valve seat; when the real-time power signal meets preset power diagnostic conditions, acquiring the valve disc insertion monitoring signal to obtain the number of valve discs inserted on the valve seat, thereby determining the theoretical current value of the valve seat; when the real-time current value in the real-time power signal is less than or equal to the theoretical current value of the valve seat, acquiring the number of operations of each valve disc and the number of operations of the actuator connected to the valve disc; and diagnosing the mechanical life of the valve island based on the number of operations of the valve discs and the actuator, thereby obtaining the valve island diagnostic result. This application solves the problem that bus valve islands lack fault diagnosis functions, and provides multiple diagnostic functions for the valve island, enabling timely understanding of the valve island's condition and timely implementation of corrective measures.

The invention discloses a GJB289A bus ICD missing-oriented test method. The GJB289A bus ICD missing test method comprises the following steps: acquiring messages on a GJB289A bus in a normal working mode of a tested system through a first GJB289A terminal module, and forming a recording file; extracting a non-broadcast message in the recorded file, converting the extracted message into a BC instruction, and sending the BC instruction to a GJB289A bus of the tested system; obtaining the address of the remote terminal from the instruction word converted from the current instruction according to the response condition of the remote terminal to the sent instruction; obtaining a simple network message of the remote terminal; extracting an instruction from the obtained simple network message of the specified remote terminal, and judging whether the GJB289A bus communication of the tested system is normal or not; and when the GJB289A bus communication of the tested system is normal, testing the state of the specified remote terminal according to the comparison condition of the current response and the response of the pre-recorded simple network message. According to the invention, the problem that the function of the tested product cannot be tested under the condition that the ICD of the GJB289A bus is lacked is well solved.

The electronic paper device and its refreshing method provided by the present application include a first housing, an electronic paper display screen, a first conductive contact, a first system bus, and a power management circuit. The electronic paper display screen is disposed on the first housing. The first conductive contact is disposed on the first housing. The first conductive contact is used for contact connection with an electronic paper refreshing device. The first system bus and the power management circuit are disposed inside the first housing. The first system bus is connected to the first conductive contact, the electronic paper display screen, and the power management circuit. The power management circuit is connected to the electronic paper display screen. The electronic paper refreshing device provides power and display information to the first system bus through the first conductive contact. The electronic paper device is connected to the first system bus and the power management circuit through the first conductive contact, which can simplify the structure of the electronic paper device.

An electronic device is provided. The electronic device includes: a plurality of master devices; and a shared subsystem including: a system bus connected to the plurality of master devices; a shared slave device; and a shared slave access controller connected to the system bus, and configured to determine a master identification number corresponding to an access request received from a first master device of the plurality of master devices, determine whether or not to permit the first master device to access the shared slave device during an access window of the shared slave device based on the master identification number, and control access authority of the first master device during the access window.

The invention belongs to the technical field of powder metallurgy processes, and particularly relates to a flexible powder metallurgy press production process optimization control system, which comprises a central processing unit which establishes a command and execution cooperative relationship with modules through a system bus and is responsible for distributing tasks, transmitting parameters and receiving feedback for various modules, the overall orderly and efficient operation of the system is realized; the data sensing module comprises a powder feeding unit, a pressing unit, a pressure maintaining unit, a demolding unit and a whole-process online detection unit, multiple types of sensors are arranged, whole-process real-time data sensing is achieved, collected data are preprocessed in real time through edge computing nodes, and data time sequence consistency is ensured; according to the execution driving module, a plurality of piezoelectric ceramic actuators are evenly arranged at the connecting end of the punch and the press main shaft in the circumferential direction, the actuators are controlled to stretch out and draw back through a high-voltage driving power source, and reverse compensation force is generated.

The invention discloses a network space data security compliance management system based on an artificial intelligence technology, and the system comprises a real-time compliance response module which is used for analyzing a supervision file and outputting structured clause information; the deep data cognition module is used for processing the service data and generating a scene label; the dynamic strategy management module is connected with the real-time compliance response module and the depth data cognition module, and is used for receiving the clause information and the scene label, compiling the clause information and the scene label into an executable strategy code, and carrying out strategy conflict resolution based on a conflict arbitration algorithm; the risk assessment model is connected with the dynamic strategy management module and the depth data cognition module; a unified management module; all the modules are in interactive connection with a block chain network through a system bus to form a closed-loop governance system from data analysis, strategy generation, risk assessment to audit execution. According to the method, the data security and the compliance check automation level are comprehensively improved, and meanwhile, the compliance cost is remarkably reduced, and the overall improvement of the whole-process management efficiency is realized.

A neural network computing system includes a processor including heterogeneous computing devices, a memory, a memory controller that controls the memory, and a system bus that communicates between the processor and the memory controller. The processor generates a frequency level combination table representing frequency level combinations of hardware devices that include the heterogeneous computing devices, the memory controller, and the system bus, each of the frequency level combinations maximizing a decreasing amount of execution time relative to an increasing amount of energy consumption when a performance level of the neural network model is increased by one level, determines, a target performance level, selects a frequency level combination among the frequency level combinations according to the target performance level, and controls, based on a selected frequency level combination, the hardware devices while the neural network model is executed.

The invention discloses a general test system for electrical system equipment of a carrier rocket, and the system constructs a comprehensive test platform with high compatibility through a system-level scheduling control strategy, a modular combined algorithm collaborative design and an ultra-wide threshold hardware interface signal conditioning technology. Comprising a system logic processing platform, a system parallel computing platform, a system power supply module, a system analog quantity acquisition module, a system bus interface module and a system digital quantity receiving module. The test system can meet the test requirements of different models and different types of carrier rocket electrical system equipment, and can realize the general test of various mainstream carrier rocket electrical equipment.

The invention suggests a vehicle occupant restraint system (10), comprising central sensor electronics (14) which can generate a locking signal; at least one belt retractor (12) which includes an electromechanical locking system (20); drive electronics (22) which is assigned to and can activate the locking system (20) of the belt retractor (12) in reaction to a locking signal; a bus system (16) to which the sensor electronics (14) and the drive electronics (22) are connected; and a line (18) separate from the bus system (16) which connects the drive electronics (22) to the sensor electronics (14). Further, a method of controlling at least one belt retractor (12) of a vehicle occupant restraint system (10) is suggested in which the following steps are provided:a vehicle acceleration is detected by sensor electronics (14);if the vehicle acceleration exceeds a predetermined threshold, a locking signal is transmitted via a bus system (16) and via a line (18) separate from the bus system (16) to drive electronics (22, 26) which is assigned to an electromechanical locking system of the belt retractor (12),the electromechanical locking system (1) then locks the belt reel.

The invention discloses a control method of a fuel cell power system integrated with online impedance spectroscopy measurement, which belongs to the technical field of fuel cell systems, and comprises the following steps: constructing a mathematical model of the fuel cell power system; designing a closed-loop control strategy and an electrochemical impedance spectroscopy measurement strategy of the fuel cell power system; designing an improved active anti-disturbance controller based on multi-resonance control; a multi-stack system electrochemical impedance spectrum disturbance self-cancellation strategy is introduced, and the design process of the fuel cell power system bus voltage control method based on multi-resonance control is achieved. By adopting the control method of the fuel cell power system integrated with impedance spectrum online measurement, the mutual exclusion limitation of online monitoring and voltage stability is broken through, full-band impedance spectrum continuous acquisition is realized under the condition of continuous normal operation of the system, the bus voltage quality is remarkably improved, and the system reliability is improved. And a key technical support is provided for real-time health diagnosis and active life management of the fuel cell power system.

The invention provides a control method, a control unit, electronic equipment and a storage medium, and the method comprises the steps: obtaining the component state information of each first component sent by an operation system and a target corresponding relation, and enabling the target corresponding relation to represent the corresponding relation between the logic identifier of each first component and the physical position of the component; the target corresponding relation is determined based on the one-to-one corresponding relation between the system bus interface and the component controller; determining an abnormal first component based on the component state information; and determining the target position of the abnormal first component according to the target corresponding relation, and performing state management on each abnormal first component based on the target position and the component state information of the abnormal first component.

The invention relates to an integrated circuit (1000) for providing a control system (10) for providing control and / or regulating signals. The integrated circuit (1000) comprises a system bus (14) with a system controller (16) configured to execute a system function (18) of the control system (10). The control system is characterized in that the control system (10) further has a measurement bus (20) with at least one measurement controller (22) configured to execute a measurement function for acquiring and / or processing measurement data and / or an output function for adjusting and / or outputting control and / or regulating signals. Furthermore, the control system (10) has a bus interface (24) configured to provide a communication connection (26) between the system bus (14) and the measurement bus (20).

1. The name of the design product: square tail exhaust muffler. 2. The use of the design product: the design product is used for fuel cell system buses, logistics vehicles, light trucks, heavy trucks, etc., which can be used for exhaust system noise reduction and water drainage. 3. The design points of the design product: in shape. 4. The picture or photo that best shows the design points: perspective view.

The embodiment of the present application discloses a bus energy storage system. The bus energy storage system is a two-layer architecture, and the bus energy storage system comprises a display control module and at least one slave control module. The display control module is located in one layer of the two-layer architecture, and the at least one slave control module is located in another layer of the two-layer architecture. The slave control module comprises a bus, a master control unit and at least one slave control unit. The display control module is electrically connected with the master control unit and the at least one slave control unit through the bus. The bus is used for signal transmission between the display control module and the master control unit and signal transmission between the display control module and the slave control unit. The bus energy storage system provided by the embodiment of the present application can improve the communication bandwidth of the bus energy storage system, solve the bandwidth bottleneck of the low-speed bus in large-scale data acquisition, and effectively improve the signal acquisition efficiency, the signal transmission rate and the working efficiency of the bus energy storage system.

A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in a plurality of groups, and circuits coupled to the memory devices. The circuits including circuitry configurable to receive from the memory controller a system clock and input control and address (C / A) signals, and to generate a module clock signal and module C / A signals in response to the system clock and input C / A signals. The circuits further include circuitry configurable to generate a plurality of local clock signals corresponding, respectively, to the plurality of groups of memory devices, and to output the plurality of local clock signals to respective groups of the memory devices. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices.