245 results about "System bus" patented technology

The invention relates to the technical field of integrated circuit design, computer system structures and embedded systems, in particular to a high-real-time interrupt management system and method based on an RISC-V. The system comprises an improved platform-level interrupt controller and an optimized processor internal interrupt processing unit. The system and the method are in tight coupling cooperative work through a special interruption field interface and a system bus, and the system further comprises a core local interrupter, an SRAM, an APB bus matrix and other components. The improved platform-level interrupt controller is responsible for sampling, gating, arbitration, flow control and direct memory access transmission of external interrupt, and a plurality of functional modules are arranged in the improved platform-level interrupt controller; an interrupt processing unit in the processor is responsible for hardware handshake, vector jump, nested control and tail biting mechanism implementation. Through hardware field management, multi-level priority arbitration, hardware nesting and tail biting mechanisms, delay and overhead caused by software intervention in a traditional architecture are eliminated, nanosecond response is achieved, the system throughput rate is increased, the software development threshold is lowered, and the method is suitable for strong real-time scenes.

The invention belongs to the technical field of agricultural picking robot control, and provides an apple picking robot control method based on multi-sensor fusion, which comprises the following steps: deploying an RGB-D camera, a laser radar and a touch sensor, cooperatively collecting data and issuing the data to a system bus, and carrying out timestamp alignment, denoising processing and fusion; the method comprises the following steps: registering collected data to a unified robot coordinate system; establishing a voxel grid to set a voxel state; mapping to form a three-dimensional occupied grid model; obtaining a visibility index according to an RGB-D segmented region; performing weighted fusion in combination with the 3D point cloud set to obtain a fruit position; the method comprises the following steps: generating a motion feasible region by utilizing a three-dimensional occupied grid model, generating candidate poses by fitting a spherical angle increment, traversing the poses to carry out collision judgment, solving a joint track, calculating a quality index and a corresponding fusion weight through real-time sensing data, and carrying out weight adjustment and parameter correction according to a corresponding problem.

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an FPGA software and hardware cooperation testing platform based on a BFM. The test platform is formed by connecting a BFM with a Testbench, an AXI bus, an off-chip DDR and a DUT. The test process comprises the steps that the Testbench issues parameters through a transaction function interface, the BFM reads an excitation vector from the off-chip DDR / on-chip BRAM through an Avalon main interface, adaptive transmission of a system bus clock domain and a DUT clock domain is completed through double asynchronous FIFO (SNDfifo / RECfifo), and signal level interaction with the DUT is achieved through a pin protocol interface; the state machine dynamically switches long and short simulation modes according to the vector length, and drives the output vector to be written back and stored; the error monitoring unit monitors data flow faults in the whole process and outputs seven types of error reporting codes. The simulation equivalent frequency reaches a 10 megahertz level, and the method is suitable for efficient verification of the digital IC.

The invention relates to the technical field of artificial intelligence and computer hardware, and discloses an artificial intelligence calculation optimization system and method based on deep learning, and the system comprises a main calculation server node, a heterogeneous calculation acceleration module, a high-speed interconnection and storage module, and a uniform resource management and scheduling module. The main computing server node is connected with the heterogeneous computing acceleration module and the high-speed interconnection and storage module through PCIe buses, and the uniform resource management and scheduling module is integrated in the main computing server node and communicates with each hardware component through a system bus. Through integration of a main computing server node, a heterogeneous computing acceleration module, a high-speed interconnection and storage module and a uniform resource management and scheduling module, efficient execution of a deep learning computing task and optimal utilization of resources are realized; the efficient and stable execution of the deep learning calculation task is realized, and powerful support is provided for the development of the artificial intelligence technology.

The invention provides a multi-protocol configurable interface circuit. The multi-protocol configurable interface circuit comprises a plurality of channel modules, a plurality of counter modules, an input / output module and a configuration register, the channel module comprises a state machine, a shift register and a cache module. The configuration register obtains configuration information through the system bus, and the configuration information comprises which protocol is selected. The counter module generates a shift signal required by a shift register in the channel module according to the configuration information; the input and output module selects the corresponding pins according to the configuration information and determines the function of each pin; and the channel module determines the mode of each channel and the required state of the state machine according to the configuration information to complete data transmission of the selected protocol. According to the invention, a hardware design which focuses on realizing clock and data transmission by matching a state machine state transition and a shift register with a cache module is adopted, so that software intervention and CPU occupation are reduced, and the overall efficiency is improved; hardware resources are reduced, and hardware flexibility is improved.

The invention provides a simulation integration method and system for an FPGA communication module. The simulation integration method comprises the following steps that S1, an IP source code of the FPGA communication module is converted into an FPGA simulation module code of a C + + language; s2, based on the FPGA simulation module code, performing interface adaptation on a system bus access part for accessing an FPGA communication module in the all-digital simulation system; s3, introducing another module which is completely the same as the FPGA communication module as a symmetric module, and performing transceiving interface cross connection on the symmetric module and the FPGA communication module; and S4, performing interface adaptation on the communication data receiving side of the symmetric module according to a bus access mode in the full-digital simulation system. The FPGA module simulation is based on the source code of the FPGA, so that the accuracy of the FPGA simulation behavior is improved.

The invention discloses a vehicle information display method, a system-on-chip, electronic equipment, a storage medium and a program product, and is applied to the system-on-chip, the system-on-chip comprises a CPU, a GPU and a memory unit which are mutually connected through a system bus; the method comprises the steps that a CPU transmits vehicle information obtained from the outside to a memory unit through a system bus, so that a GPU reads the vehicle information, performs 3D rendering processing and outputs and displays the vehicle information; when the GPU breaks down, the CPU generates two-dimensional display information at least according to the vehicle information and outputs and displays the two-dimensional display information. According to the embodiment of the invention, when the GPU breaks down, the CPU takes over the display processing of the vehicle information, and carries out the two-dimensional display processing and output display of the vehicle information in a simplified drawing mode, so that the output display function of the vehicle information is completed, and the user experience is improved. And negative effects caused by excessive occupation of CPU resources when 3D rendering processing is carried out on the vehicle information are also avoided.

A simple configuration aims to reduce MCU vulnerabilities. [Solution] The control device 10 includes an MCU 20. The MCU 20 has a CPU 22, a system bus 26, a storage device 28, and an address translation device 24 that translates addresses between the CPU address space of the CPU 22 and the system bus address space of the system bus 26 in accordance with translation rules set in a special function register 24A. The MCU 20 starts up in an unrestricted mode in which all addresses in the CPU address space are available, and after startup, when a predetermined condition is met, it switches to a restricted mode in which only a portion of the addresses in the CPU address space are available. The special function register 24A allows the translation rules to be set and read when in the unrestricted mode, and does not allow the translation rules to be set or read when in the restricted mode.

This application discloses a valve island diagnostic method, control system, bus valve island, and storage medium, relating to the field of electrical control. The method includes: acquiring the real-time power signal of the valve seat; when the real-time power signal meets preset power diagnostic conditions, acquiring the valve disc insertion monitoring signal to obtain the number of valve discs inserted on the valve seat, thereby determining the theoretical current value of the valve seat; when the real-time current value in the real-time power signal is less than or equal to the theoretical current value of the valve seat, acquiring the number of operations of each valve disc and the number of operations of the actuator connected to the valve disc; and diagnosing the mechanical life of the valve island based on the number of operations of the valve discs and the actuator, thereby obtaining the valve island diagnostic result. This application solves the problem that bus valve islands lack fault diagnosis functions, and provides multiple diagnostic functions for the valve island, enabling timely understanding of the valve island's condition and timely implementation of corrective measures.

An electronic device is provided. The electronic device includes: a plurality of master devices; and a shared subsystem including: a system bus connected to the plurality of master devices; a shared slave device; and a shared slave access controller connected to the system bus, and configured to determine a master identification number corresponding to an access request received from a first master device of the plurality of master devices, determine whether or not to permit the first master device to access the shared slave device during an access window of the shared slave device based on the master identification number, and control access authority of the first master device during the access window.

The invention belongs to the technical field of powder metallurgy processes, and particularly relates to a flexible powder metallurgy press production process optimization control system, which comprises a central processing unit which establishes a command and execution cooperative relationship with modules through a system bus and is responsible for distributing tasks, transmitting parameters and receiving feedback for various modules, the overall orderly and efficient operation of the system is realized; the data sensing module comprises a powder feeding unit, a pressing unit, a pressure maintaining unit, a demolding unit and a whole-process online detection unit, multiple types of sensors are arranged, whole-process real-time data sensing is achieved, collected data are preprocessed in real time through edge computing nodes, and data time sequence consistency is ensured; according to the execution driving module, a plurality of piezoelectric ceramic actuators are evenly arranged at the connecting end of the punch and the press main shaft in the circumferential direction, the actuators are controlled to stretch out and draw back through a high-voltage driving power source, and reverse compensation force is generated.

The invention discloses a network space data security compliance management system based on an artificial intelligence technology, and the system comprises a real-time compliance response module which is used for analyzing a supervision file and outputting structured clause information; the deep data cognition module is used for processing the service data and generating a scene label; the dynamic strategy management module is connected with the real-time compliance response module and the depth data cognition module, and is used for receiving the clause information and the scene label, compiling the clause information and the scene label into an executable strategy code, and carrying out strategy conflict resolution based on a conflict arbitration algorithm; the risk assessment model is connected with the dynamic strategy management module and the depth data cognition module; a unified management module; all the modules are in interactive connection with a block chain network through a system bus to form a closed-loop governance system from data analysis, strategy generation, risk assessment to audit execution. According to the method, the data security and the compliance check automation level are comprehensively improved, and meanwhile, the compliance cost is remarkably reduced, and the overall improvement of the whole-process management efficiency is realized.

The invention discloses a general test system for electrical system equipment of a carrier rocket, and the system constructs a comprehensive test platform with high compatibility through a system-level scheduling control strategy, a modular combined algorithm collaborative design and an ultra-wide threshold hardware interface signal conditioning technology. Comprising a system logic processing platform, a system parallel computing platform, a system power supply module, a system analog quantity acquisition module, a system bus interface module and a system digital quantity receiving module. The test system can meet the test requirements of different models and different types of carrier rocket electrical system equipment, and can realize the general test of various mainstream carrier rocket electrical equipment.

The invention suggests a vehicle occupant restraint system (10), comprising central sensor electronics (14) which can generate a locking signal; at least one belt retractor (12) which includes an electromechanical locking system (20); drive electronics (22) which is assigned to and can activate the locking system (20) of the belt retractor (12) in reaction to a locking signal; a bus system (16) to which the sensor electronics (14) and the drive electronics (22) are connected; and a line (18) separate from the bus system (16) which connects the drive electronics (22) to the sensor electronics (14). Further, a method of controlling at least one belt retractor (12) of a vehicle occupant restraint system (10) is suggested in which the following steps are provided:a vehicle acceleration is detected by sensor electronics (14);if the vehicle acceleration exceeds a predetermined threshold, a locking signal is transmitted via a bus system (16) and via a line (18) separate from the bus system (16) to drive electronics (22, 26) which is assigned to an electromechanical locking system of the belt retractor (12),the electromechanical locking system (1) then locks the belt reel.

The invention discloses a control method of a fuel cell power system integrated with online impedance spectroscopy measurement, which belongs to the technical field of fuel cell systems, and comprises the following steps: constructing a mathematical model of the fuel cell power system; designing a closed-loop control strategy and an electrochemical impedance spectroscopy measurement strategy of the fuel cell power system; designing an improved active anti-disturbance controller based on multi-resonance control; a multi-stack system electrochemical impedance spectrum disturbance self-cancellation strategy is introduced, and the design process of the fuel cell power system bus voltage control method based on multi-resonance control is achieved. By adopting the control method of the fuel cell power system integrated with impedance spectrum online measurement, the mutual exclusion limitation of online monitoring and voltage stability is broken through, full-band impedance spectrum continuous acquisition is realized under the condition of continuous normal operation of the system, the bus voltage quality is remarkably improved, and the system reliability is improved. And a key technical support is provided for real-time health diagnosis and active life management of the fuel cell power system.

The invention relates to an integrated circuit (1000) for providing a control system (10) for providing control and / or regulating signals. The integrated circuit (1000) comprises a system bus (14) with a system controller (16) configured to execute a system function (18) of the control system (10). The control system is characterized in that the control system (10) further has a measurement bus (20) with at least one measurement controller (22) configured to execute a measurement function for acquiring and / or processing measurement data and / or an output function for adjusting and / or outputting control and / or regulating signals. Furthermore, the control system (10) has a bus interface (24) configured to provide a communication connection (26) between the system bus (14) and the measurement bus (20).

1. The name of the design product: square tail exhaust muffler. 2. The use of the design product: the design product is used for fuel cell system buses, logistics vehicles, light trucks, heavy trucks, etc., which can be used for exhaust system noise reduction and water drainage. 3. The design points of the design product: in shape. 4. The picture or photo that best shows the design points: perspective view.

The embodiment of the present application discloses a bus energy storage system. The bus energy storage system is a two-layer architecture, and the bus energy storage system comprises a display control module and at least one slave control module. The display control module is located in one layer of the two-layer architecture, and the at least one slave control module is located in another layer of the two-layer architecture. The slave control module comprises a bus, a master control unit and at least one slave control unit. The display control module is electrically connected with the master control unit and the at least one slave control unit through the bus. The bus is used for signal transmission between the display control module and the master control unit and signal transmission between the display control module and the slave control unit. The bus energy storage system provided by the embodiment of the present application can improve the communication bandwidth of the bus energy storage system, solve the bandwidth bottleneck of the low-speed bus in large-scale data acquisition, and effectively improve the signal acquisition efficiency, the signal transmission rate and the working efficiency of the bus energy storage system.

A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in a plurality of groups, and circuits coupled to the memory devices. The circuits including circuitry configurable to receive from the memory controller a system clock and input control and address (C / A) signals, and to generate a module clock signal and module C / A signals in response to the system clock and input C / A signals. The circuits further include circuitry configurable to generate a plurality of local clock signals corresponding, respectively, to the plurality of groups of memory devices, and to output the plurality of local clock signals to respective groups of the memory devices. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices.

A bus control unit includes: a compression execution unit, configured to compress sparse data by using a compression algorithm, to obtain compression data and compression attribute information; and a compression control unit, configured to generate, according to an instruction format of a communication bus, a data signal carrying the compression attribute information and the compression data, and send the data signal through the communication bus, where the compression attribute information is used for decompressing the compression data to obtain the sparse data.

The invention relates to the technical field of power system bus load prediction, and discloses a power system bus load prediction system, method, device and medium, and the system collects multi-source data through a data sensing module, carries out the feature extraction and fusion, generates a multi-dimensional feature vector, and provides a rich and comprehensive data basis for the subsequent prediction. A rule engine unit, a model engine unit and a result fusion unit in the intelligent prediction engine module work cooperatively, and standardized feature data can be efficiently processed and accurately predicted. The rule matching mechanism of the rule engine unit improves the system operation efficiency, the diversified prediction mode of the model engine unit considers multiple influence factors, and the result fusion unit further optimizes the prediction result. The multi-module cooperation mode overcomes the problems that a traditional prediction method is single in data utilization, poor in model adaptability, insufficient in multi-source heterogeneous data fusion processing capacity and the like.

For example, a controller may be configured to process system bus information received via a system bus of a vehicle to identify active acoustic control (AAC) configuration information representing one or more parameters that affect real-time configuration of an AAC in at least one sound control region in the vehicle. For example, the controller may be configured to selectively enable or disable an AAC state switching function provided to a user by a user interface (UI), for example, based on the AAC configuration information. For example, the AAC state switching function may be configured to allow the user to switch between at least a first AAC state and a second AAC state of the AAC in the at least one sound control region.

The invention discloses a self-checking device and method for an RISC-V storage architecture, and the device enables a state monitoring module to be independent of the RISC-V storage architecture, integrates a high-precision performance monitoring unit, achieves the interaction with an external upper computer through a serial communication protocol, achieves the self-checking of the RISC-V storage architecture, and achieves the self-checking of the RISC-V storage architecture. State acquisition and performance monitoring of the RISC-V multi-level storage system in a plurality of key stages such as instruction access, data read-write and cache response are realized, and a high-reliability and low-intrusive self-checking process is completed on the premise of not depending on a system bus and internal resources. According to the scheme, the fault mode and the performance bottleneck can be accurately identified in the system operation process, and the testability, the debuggeability and the overall stability of the storage architecture are effectively improved.

A control device 10 includes an MCU 20 including a CPU 22, a system bus 26, storage 28, and an address translator 24 translating an address in the CPU address space of the CPU 22 to and from an address in the system bus address space of the system bus 26 according to the translation rule set in the special function register 24A. The MCU 20 starts up in the limitation-release mode in which all addresses in the CPU address space are available, and switches to the limitation mode in which only some of the addresses in the CPU address space are available when a predetermined condition is satisfied after the start-up. For the special function register 24A, the translation rule is settable and readable in the limitation release mode, and the translation rule is neither settable nor readable in the limitation mode.

The invention discloses a control system bus communication load self-adaption method and device, and the method comprises the steps: comparing the real-time data of a current period with the data of a previous period, judging whether a real-time data frame is a change frame or a period frame, enabling the change frame to transmit the real-time data in a minimum communication manner, and enabling the period frame to transmit the real-time data in a minimum communication manner according to the number of change frames and the number of period frames in a statistical period; and calculating an effective load rate, and dynamically adjusting a communication period of the non-critical data based on comparison between the effective load rate and a preset target load rate, thereby realizing on-demand distribution and adaptive balance of the bus bandwidth. According to the method, periodic dynamic self-adaptive adjustment is realized by quantifying the effective load rate of a single module, and the bus communication effective utilization rate and the data real-time performance are improved on the premise of not upgrading hardware.

A data access processing circuit, control method, and electronic device are disclosed. The circuit, used for data access between multiple functional modules and a system bus, includes: an arbitration circuit connected to the multiple functional modules, configured to receive access request signals and urgency signals sent by the multiple functional modules, determine a target functional module from the multiple functional modules based on the urgency signal, send a confirmation signal to the target functional module, and generate internal operation instructions based on the access request signals; and a conversion circuit connected to the arbitration circuit, the multiple functional modules, and the system bus, configured to receive the internal operation instructions, convert the internal operation instructions into bus operation instructions conforming to the system bus protocol and send them to the system bus, and transmit data corresponding to the bus operation instructions between the system bus and the target functional module. This application has the technical effect of improving data access processing efficiency.

The invention discloses a multifunctional electrosurgical workstation and a control method thereof, and is characterized in that the workstation comprises at least two surgical operating instruments; a CAN bus, a CAN bus communication module and a system MCU; a control switch; the at least two surgical procedure instruments, the CAN bus communication module and the control switch are respectively connected to the CAN bus; and the CAN bus is connected with the system MCU through the CAN bus communication module. The CAN bus technology is applied to the multifunctional electrosurgical workstation, a plurality of surgical procedure instruments in the system are controlled through the CAN bus, system buses are greatly reduced, and the reliability of the system is improved.

The invention discloses a test method and system based on an XCP Ethernet, and belongs to the technical field of hardware-in-the-loop testing, the system comprises a test module, an upper computer module and a tested module, the test module and the tested module are in bidirectional electrical connection, the test module and the upper computer module are in bidirectional electrical connection, and the upper computer module is in bidirectional electrical connection with the tested module. The test module comprises a core board, a driving circuit, a processor chip and a programmable chip, the core board is bidirectionally and electrically connected with the driving circuit, the processor chip and the programmable chip are arranged on the core board, and the processor chip and the programmable chip can be bidirectionally connected through an internal system bus. The tested module comprises a controlled power supply module and a vehicle controller module. The XCP protocol stack is integrated in the test module, so that any upper computer software supporting the XCP protocol in the market can be communicated with the test device, on one hand, the development cost of the upper computer software is saved, the development period of the upper computer software is shortened, and on the other hand, the universality of the test device is improved.

The application discloses a kind of SPI slave controller and chip, belong to integrated circuit technical field.The SPI slave controller includes SPI interface, core control module, register module, AHB system bus decoding module and receiving buffer, sending buffer and receiving shift register, sending shift register.The register module is stored with control flag and state flag.The core control module works according to the control flag, and the chip selection signal of SPI interface is detected in real time.When chip selection signal is valid, core control module calculates and records the effective data length currently sent or received in real time;When chip selection signal is invalid, set data transmission completion flag, and finally effective data length is latched to register module.The application realizes that SPI transmission is not needed software preconfiguration or intervention, hardware self-adapting detects end transmission and automatically records effective data length, guarantees the atomicity and accuracy of data transmission.

The embodiment of the application provides a system-level chip for communication between an AUTBUS and an SPI slave module, a system bus, and the system bus is connected with an AUTBUS module and a serial peripheral interface (SPI) slave module; wherein, the AUTBUS module is provided with an AUTBUS cache and an AUTBUS arbitration module, and the SPI slave module is provided with an SPI write cache and an SPI read cache; when the AUTBUS arbitration module controls the transmission direction to be a first transmission direction, the AUTBUS module reads cache data from the AUTBUS cache and sends the cache data to the SPI slave module through a direct memory access (DMA) mode, and the SPI slave module receives the cache data from the system bus and writes the cache data into the SPI write cache; when the AUTBUS arbitration module controls the transmission direction to be a second transmission direction, the AUTBUS module sends a first read request to the SPI slave module, the first read request comprising: target data length, the SPI slave module reads cache data of the target data length from the SPI read cache and sends the cache data to the AUTBUS; thereby, the communication between the AUTBUS module and the SPI slave module can be realized, and the efficiency of the communication between the AUTBUS module and the SPI slave module is improved.