500 results about "System bus" patented technology

The invention discloses an I2C bus system for configuration of a plurality of circuit structures, the I2C bus system comprises a plurality of circuit structures connected to an I2C bus, and the circuit structures are used for configuring I2C address device information according to detection pins set by the circuit structures; the I2C address device information comprises device addresses, and the device addresses configured by any two circuit structures are different; wherein the mapping relations about the I2C address equipment information used by the plurality of circuit structures are the same. By providing corresponding detection pins in the circuit structures connected to the I2C bus and detecting signals at the pins in real time, I2C master-slave roles and device addresses of all the circuit structures are automatically configured, and personnel in related technical fields do not need to burn matched firmware for all the circuit structures according to set welding positions when leaving a factory. Even if the welding position is wrong, the correct device address configuration of each circuit structure in the I2C bus is not influenced, and the production process of the chip supporting I2C communication is simplified.

A transmitting / receiving device for a bus system and a method for reducing an oscillation tendency in the transition between different bit states. The transmitting / receiving device has a transmitting stage for transmitting a transmission signal to a first bus wire of a bus of the bus system and for transmitting the transmission signal as an inverse signal to a second bus wire of the bus, and an asymmetry reduction module for reducing an asymmetry of bus signals arising in the bus wires. The asymmetry reduction module includes a polarity reversing diode, whose cathode is connected to the cathode of a reverse polarity diode of the transmitting stage. The asymmetry reduction module switches a potential of the cathode of the polarity reversing diode to a potential that is greater than or equal to a level of a recessive bus state.

A system can include a host computer system and a host system bus coupled to the host computer system. One or more storage devices can be coupled to the host system bus and configured to store data. Additionally, a computational storage device (CSD) can be coupled to the host system bus and configured to receive a data write request comprising data from the host computer system. The CSD can further include a memory and an application processor. The application processor of the CSD can be configured to write the data of the data write request to the one or more storage devices in response to receiving the data write request.

The invention belongs to the field of chip design, and provides a packet bus interconnection architecture of an SoC system, which comprises a system bus matrix SYSBUSMatrix, at least one processor bus matrix CBM, at least one high-speed peripheral bus matrix HPBM, at least one memory bus matrix RBM and one low-speed peripheral bus matrix SPBM, the CBM, the HPBM, the RBM and the SPBM are all connected with the SYSBUSMatrix through a bus bridge; the embedded processor is mounted on the CBM, and meanwhile, the CBM is connected with the RMB; a high-speed peripheral is mounted on the HPBM, and meanwhile, the HPBM is connected with the RMB; a random access memory (RAM) is mounted on the RBM, and meanwhile, the RBM is connected with the CBM and the HPBM; the SPBM is connected with a plurality of paths of AHB buses through an AXI-AHB bridge, the SPBM is connected with a plurality of paths of APB buses through an AXI-APB bridge, meanwhile, the SPBM is connected with SYSBUSMatrix, and a plurality of paths of low-speed peripherals are mounted on the AHB buses or the APB buses. According to the method, bus transmission among modules such as a processor, a high-speed peripheral and a storage can be balanced, bus competition among high-speed interfaces is effectively reduced, data transmission efficiency is improved, chip rear-end implementation is simplified, and therefore the performance of the whole SOC is optimized.

The invention provides an active intervention type arc-extinguishing and resonance-eliminating device and method, and relates to the technical field of power system safety control, the device comprises an intelligent grounding module, the intelligent grounding module comprises a three-phase line led out from a system bus, and the three-phase line is grounded through a secondary side of a voltage transformer; a three-phase contactor and an impedance grounding transformer are sequentially connected in series between the system bus and the grounding end; when overvoltage and line resonance are caused by a non-single-phase earth fault of the power distribution network system, the PTC resonance elimination module is used for actively carrying out resonance suppression; the monitoring module is used for monitoring the working state of the device and generating state information; the processing module is used for processing the state information; and the alarm module performs a corresponding alarm action. According to the active intervention type arc and resonance elimination device and the matched fault treatment method thereof, innovative application of the intelligent grounding module and the PTC resonance elimination module is combined, and a comprehensive solution with high flexibility and self-adaptive capacity is formed.

Embodiments of the present disclosure provide a data transmission method, a data link layer, a chip interconnection interface, and an electronic device. The data transmission method is applied to the data link layer of the chip interconnection interface, the data link layer communicates with the system bus and the physical layer, the system bus operates in a first clock domain, and the physical layer operates in a second clock domain or in a second clock domain and a third clock domain. The method includes: the data link layer performs packet processing on the first data received from the system bus to obtain second data, and provides the second data to the physical layer; or, the data link layer performs unpacking processing on the third data received from the physical layer to obtain fourth data, and provides the fourth data to the system bus, wherein the data link layer partially operates in the third clock domain, and the first clock domain is different from the second clock domain and the third clock domain, the first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal.

The invention relates to the technical field of integrated circuit design, computer system structures and embedded systems, in particular to a high-real-time interrupt management system and method based on an RISC-V. The system comprises an improved platform-level interrupt controller and an optimized processor internal interrupt processing unit. The system and the method are in tight coupling cooperative work through a special interruption field interface and a system bus, and the system further comprises a core local interrupter, an SRAM, an APB bus matrix and other components. The improved platform-level interrupt controller is responsible for sampling, gating, arbitration, flow control and direct memory access transmission of external interrupt, and a plurality of functional modules are arranged in the improved platform-level interrupt controller; an interrupt processing unit in the processor is responsible for hardware handshake, vector jump, nested control and tail biting mechanism implementation. Through hardware field management, multi-level priority arbitration, hardware nesting and tail biting mechanisms, delay and overhead caused by software intervention in a traditional architecture are eliminated, nanosecond response is achieved, the system throughput rate is increased, the software development threshold is lowered, and the method is suitable for strong real-time scenes.

The invention belongs to the technical field of agricultural picking robot control, and provides an apple picking robot control method based on multi-sensor fusion, which comprises the following steps: deploying an RGB-D camera, a laser radar and a touch sensor, cooperatively collecting data and issuing the data to a system bus, and carrying out timestamp alignment, denoising processing and fusion; the method comprises the following steps: registering collected data to a unified robot coordinate system; establishing a voxel grid to set a voxel state; mapping to form a three-dimensional occupied grid model; obtaining a visibility index according to an RGB-D segmented region; performing weighted fusion in combination with the 3D point cloud set to obtain a fruit position; the method comprises the following steps: generating a motion feasible region by utilizing a three-dimensional occupied grid model, generating candidate poses by fitting a spherical angle increment, traversing the poses to carry out collision judgment, solving a joint track, calculating a quality index and a corresponding fusion weight through real-time sensing data, and carrying out weight adjustment and parameter correction according to a corresponding problem.

The invention relates to a method for intelligently judging the type of a single-phase earth fault in a power supply and distribution system, which is suitable for connecting arc extinguishing equipment to a system bus and is parallel to each feeder line connected to the system bus. Wherein the working stage of the arc extinguishing equipment is divided into an arc extinguishing equipment awakening stage, a fault phase selection arc extinguishing stage and a fault type line selection stage. When a single-phase earth fault occurs in the range of a system line where the arc extinction equipment is located, the arc extinction equipment is quickly awakened and enters a fault phase selection arc extinction stage, and the single-phase earth fault occurring in the system line can be quickly processed through three links of phase selection, verification and arc extinction. And the method has the capabilities of fault tolerance, error correction and severe transient process suppression in the processing process. A three-phase split-phase switch driven by eddy current is selected as a phase selection switch in the arc extinction equipment, and the two-phase switch cannot be switched on or switched off at the same time due to disorder switching-on and switching-off programs when the arc extinction equipment performs phase selection action due to the wiring mode of each phase switch coil panel in the three-phase split-phase switch.

The invention discloses a communication data security protection method and system based on an HSM module. Relates to the field of data security transmission, and aims to realize a high-security, high-performance and high-reliability data protection scheme, the method comprises the following steps: S1, an application processor is connected with an HSM module through a system bus, and the HSM module comprises a configuration register, a state register and a data register; s2, loading an SDK (Software Development Kit) by the application processor, wherein the SDK provides an application program interface for interacting with the HSM module; s3, receiving data to be encrypted, and transmitting the data to the HSM module through the API; s4, in the HSM module, initializing a state register, configuring an encryption mode, encrypting the data, and storing the encrypted data in a data register; and S5, the encrypted data is returned through the API. The method is suitable for secure data transmission in the fields of Internet of Things, cloud computing and the like, and an innovative solution is provided for sensitive information protection.

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an FPGA software and hardware cooperation testing platform based on a BFM. The test platform is formed by connecting a BFM with a Testbench, an AXI bus, an off-chip DDR and a DUT. The test process comprises the steps that the Testbench issues parameters through a transaction function interface, the BFM reads an excitation vector from the off-chip DDR / on-chip BRAM through an Avalon main interface, adaptive transmission of a system bus clock domain and a DUT clock domain is completed through double asynchronous FIFO (SNDfifo / RECfifo), and signal level interaction with the DUT is achieved through a pin protocol interface; the state machine dynamically switches long and short simulation modes according to the vector length, and drives the output vector to be written back and stored; the error monitoring unit monitors data flow faults in the whole process and outputs seven types of error reporting codes. The simulation equivalent frequency reaches a 10 megahertz level, and the method is suitable for efficient verification of the digital IC.

The invention discloses a vehicle-mounted controller and a communication virtualization system and method, and relates to the field of automobile control, and the system is based on an x86 architecture computer as a host machine; a virtual controller bottom layer model in the system simulates an actual vehicle-mounted controller on an x86 architecture computer by utilizing a virtualization technology, a layered decoupling virtualization controller is developed on the basis of the virtualization technology, and host machine hardware, a controller kernel, a simulation system and an application verification part are developed in a layered manner; on the basis of the virtual controller bottom layer model, the virtual communication bus model is compared with an actual vehicle-mounted controller bus port, simulates a bus signal by utilizing a PCI (Peripheral Component Interconnect) and a system bus, and is carried on the Ethernet through a conversion protocol; the signal closed-loop transmission model is built by using a Simulink tool, and bidirectional conversion between a controller bus signal and an external data signal is carried out. According to the method, the universal vehicle-mounted virtual controller model can be established, and the function verification efficiency of the vehicle related to the controller is improved.

The invention provides bus hardware security monitoring equipment and a monitoring method based on an embedded system, master control equipment and slave equipment on a bus are connected with an intermediate control module, a bus monitoring module comprises a lightweight hash algorithm module and a DM module, all the master control equipment and slave equipment on the bus are connected with the input end of each channel, and the input end of each channel is connected with the corresponding channel. The outputs of all the channels are summarized to the interrupt management unit, the interrupt management unit serves as the output end of the bus monitoring module and is connected with the DMA, each channel comprises a monitoring selection unit, an access selection unit and a counting comparison unit, and an address range is set for each channel. Corresponding interrupt information is generated by monitoring the integrity abnormal behavior of a specific bus access sequence occurring in a system bus in the SoC security program running process. In a low-power-consumption application scene, the security of the embedded SoC can be improved, and key information is protected from being stolen and damaged.

The embodiment of the invention discloses a read-only code patch repairing method and device and a storage medium, and relates to the field of embedding. According to the method, the read-write request on the system bus is monitored, so that all-bus patch coverage of any code / data is realized. According to the patch repairing device, the patch pool containing various kinds of information is preset, and when a read-write request of a specific address is detected, corresponding patch data items can be quickly inquired and matched. And if the matching is successful and the patch is valid, replacing the target data according to the patch type or triggering a CPU exception instruction to enter an interrupt processing flow to obtain the patch. The method is universal and flexible, supports undifferentiated full-function patches, can cope with various code / data errors, and greatly reduces the risk of chip scrapping or re-burning caused by ROM code abnormity. By means of bus replacement, abnormal triggering and the like, effective repair of read-only codes is achieved, remarkable economic effects are achieved, production efficiency is improved, and product cost is reduced.

The invention discloses an accelerator supporting an attention mechanism, which is used for realizing matrix multiplication operation, scaling operation or nonlinear activation processing related to the attention mechanism, and is characterized in that a weight cache state machine module is used for controlling weight data to flow from a system bus to a weight cache unit; the thread cache state machine module is used for controlling thread data to flow from the system bus to the thread cache unit; the attention tensor processing unit state machine module is used for controlling loading and flowing of thread data and weight data from the two-dimensional systolic array in different directions, the thread data is controlled to be transmitted to the next processing unit in each period, and the weight data is spread to the processing units in the corresponding directions in a broadcast mode; the calculation result of the two-dimensional systolic array is transmitted to different branches according to whether nonlinear activation processing needs to be executed or not. According to the method, data filling is carried out on the matrix so that the matrix can be matched with the systolic array data stream, and then the attention mechanism with the variable sequence length is accelerated through hardware.

The invention discloses a reset circuit, a reset method and a multi-core heterogeneous system. The reset circuit is applied to the multi-core heterogeneous system comprising at least two hardware domains. Each mutually isolated hardware domain is composed of a plurality of processor cores with different architectures in the multi-core heterogeneous system and hardware resources connected with each processor core; each hardware domain and the operating system corresponding to each hardware domain form each domain system; each domain system accesses system resources through a system bus; the reset circuit comprises a monitoring module which is used for monitoring each monitored object and obtaining a monitoring signal for each monitored object; the first processing module is used for acquiring a target reset mode from at least two reset modes according to the monitoring signal; processing the monitoring signal based on the target reset mode to obtain a first reset signal; and the reset control module is used for controlling the output of a first reset signal, and the output first reset signal is used for resetting the monitored object matched with the target reset mode.

The invention relates to the technical field of artificial intelligence and computer hardware, and discloses an artificial intelligence calculation optimization system and method based on deep learning, and the system comprises a main calculation server node, a heterogeneous calculation acceleration module, a high-speed interconnection and storage module, and a uniform resource management and scheduling module. The main computing server node is connected with the heterogeneous computing acceleration module and the high-speed interconnection and storage module through PCIe buses, and the uniform resource management and scheduling module is integrated in the main computing server node and communicates with each hardware component through a system bus. Through integration of a main computing server node, a heterogeneous computing acceleration module, a high-speed interconnection and storage module and a uniform resource management and scheduling module, efficient execution of a deep learning computing task and optimal utilization of resources are realized; the efficient and stable execution of the deep learning calculation task is realized, and powerful support is provided for the development of the artificial intelligence technology.

The invention belongs to the field of analog-to-digital conversion controller design, and discloses an analog-to-digital conversion control device and a control method.The analog-to-digital conversion control device receives scheduling of a CPU through a system bus and generates a control signal to control an analog-to-digital converter. Comprising an interface conversion unit, a decoding unit, a sampling clock generator, a channel calibration unit, a reference processing unit, a zero-cross detection unit and a threshold detection unit, in hardware, the channel calibration unit is directly utilized to compensate channel differences, and the reference processing unit is utilized to process reference errors. Meanwhile, zero-cross detection and threshold detection can be carried out by using hardware, and extra software overhead is not needed, so that resource consumption is reduced, and the efficiency of the system is improved. A user can conveniently select a processing mode according to an application scene, an operation way in the prior art is supported, and a processing mode without additional software overhead is also supported.

Provided in the embodiments of the present disclosure are a protocol controller, a protocol control method, a chiplet, a system on a chip, and an electronic device. The protocol controller comprises: a first bus interface, which is connected to a system bus, wherein the first bus interface implements an inter-chip interconnect protocol, and a first partial sub-protocol of a peripheral protocol; and a second bus interface, which is connected to the system bus, wherein the second bus interface implements a second partial sub-protocol of the peripheral protocol, and the first partial sub-protocol and the second partial sub-protocol are configured to be implemented by different bus interfaces; and a chiplet uses one of the inter-chip interconnect protocol and the peripheral protocol at the same time.

The invention provides a starting method, related equipment and a readable storage medium, and is applied to the technical field of computers, the method is applied to a system-on-chip configured with a main processor and a bus monitoring module, the bus monitoring module provides an initialization operation sequence, and the operation sequence of the main processor is initialized based on the pre-stored initialization operation sequence. The bus monitoring module initializes the main processor and awakens the main processor after a first starting address of the main processor is configured, the first starting address is obtained after the main processor is awakened, and target starting firmware needing to be executed after the main processor is initialized is executed according to the first starting address. And the bus monitoring module initializes the main processor by using the pre-stored initialization operation sequence and skips a BL1 stage and a BL33 stage, so that the interaction times of BL1 firmware and BL33 firmware in the initialization process of the processor are reduced, the exposure risk is reduced, and the running safety of the processor is improved.

Disclosed in the present invention are a post-quantum cryptographic algorithm processor and a system-on-chip comprising same. The post-quantum cryptographic processor comprises an instruction fetch unit, a decode unit, an execute unit and a write-back unit; the execute unit comprises a parallel computing unit module, and the parallel computing unit module uses a part recomposition technology and an operator fusion technology and thus can use a same part to realize core operation of different computing types and bit widths of a post-quantum cryptographic algorithm; the system-on-chip for running the post-quantum cryptographic processor comprises: a system bus, the post-quantum cryptographic processor connected to the system bus, a storage unit connected to the post-quantum cryptographic processor, an external device interface connected to the system bus and a cache active prefetching / pre-storing data functional module which is connected to the post-quantum cryptographic processor and is combined with a DMA; and the post-quantum cryptographic processor communicates with an external device by means of the external device interface, and performs data and instruction read / write on the storage unit. The present invention reduces the power consumption and resource overhead of systems, and improves the running speed of a post-quantum cryptographic algorithm.

The invention provides a multi-protocol configurable interface circuit. The multi-protocol configurable interface circuit comprises a plurality of channel modules, a plurality of counter modules, an input / output module and a configuration register, the channel module comprises a state machine, a shift register and a cache module. The configuration register obtains configuration information through the system bus, and the configuration information comprises which protocol is selected. The counter module generates a shift signal required by a shift register in the channel module according to the configuration information; the input and output module selects the corresponding pins according to the configuration information and determines the function of each pin; and the channel module determines the mode of each channel and the required state of the state machine according to the configuration information to complete data transmission of the selected protocol. According to the invention, a hardware design which focuses on realizing clock and data transmission by matching a state machine state transition and a shift register with a cache module is adopted, so that software intervention and CPU occupation are reduced, and the overall efficiency is improved; hardware resources are reduced, and hardware flexibility is improved.

Methods, systems, and devices for message signaled interrupt (MSI-X) tunneling on a host device exposed by a bridge connection are described. A device may receive data and a first interrupt signal from a remote destination over a network protocol. The device may receive the data and / or the first interrupt signal over the bridge connection, via a tunneled communication from the remote destination. The device may generate a second interrupt signal based on the first interrupt signal and a local interrupt configuration provided by a system bus driver of the device. The device may inject the data and the second interrupt signal over the system bus. Injecting the data and injecting the second interrupt signal may include ensuring the data is made available to the system bus driver, prior to the interrupt handler receiving the second interrupt signal.

A transmitting module. The transmitting module has a first transmission stage for generating transmission currents for a first signal to be transmitted onto a bus of a serial bus system, a second transmission stage for generating transmission currents for a second signal to be transmitted onto the bus as a signal that is differential to the first signal, a third transmission stage for generating transmission currents for the first signal, and a fourth transmission stage for generating transmission currents for the second signal. The first to fourth transmission stages are connected in a full bridge. The first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series. Each of the first to fourth transmission stages has at least two current stages, connected in parallel with one another. Each of the at least two current stages has a switchable resistor.

The embodiment of the invention provides a system-on-chip for communication between an AUTBUS and an SPI slave module. The system-on-chip comprises a system bus, wherein an AUTBUS module and the SPI slave module are hung on the system bus; wherein an AUTBUS cache and an AUTBUS arbitration module are arranged in the AUTBUS module, and an SPI write cache and an SPI read cache are arranged in the SPI slave module; when the AUTBUS arbitration module controls the transmission direction to be a first transmission direction, the AUTBUS module reads cache data from an AUTBUS cache and sends the cache data to an SPI slave module in a direct memory access (DMA) mode, and the SPI slave module receives the cache data from a system bus and writes the cache data into an SPI write cache; when the AUTBUS arbitration module controls the transmission direction to be a second transmission direction, the AUTBUS module sends a first read request to an SPI slave module, the first read request comprises a target data length, and the SPI slave module reads cached data of the target data length from an SPI read cache and sends the cached data to the AUTBUS; therefore, the communication between the AUTBUS module and the SPI slave module can be realized, and the communication efficiency between the AUTBUS module and the SPI slave module is improved.

The present disclosure provides a multi-core synchronization system and a system component. The system comprises a neural network processor and a system component. The neural network processor comprises a task scheduling processor and a plurality of cores. The system component is connected to the task scheduling processor and the plurality of cores respectively by means of a system bus. The system component is used for performing communication among the plurality of cores under the control of the task scheduling processor, so that the plurality of cores synchronously execute allocated model tasks.

The embodiment of the invention discloses a bus balance hybrid topology circuit of a UPS system. The bus balance hybrid topology circuit comprises an A-phase branch, a B-phase branch, a C-phase branch, a battery positive discharge unit, a battery negative discharge unit and a bus balance unit, the A-phase branch comprises a first dual-BOOST PFC (Power Factor Correction) circuit; the C-phase branch circuit comprises a second dual-BOOST PFC circuit; the B-phase branch comprises a first change-over switch and a Vienna PFC circuit; the Vienna PFC circuit comprises a bus balance unit, and the Vienna PFC circuit is connected with the first change-over switch; the battery positive discharge unit and the battery negative discharge unit are respectively connected with the battery; and each circuit is connected with a direct-current power supply. By implementing the circuit provided by the embodiment of the invention, the midpoint cable of the battery can be removed, the voltage balance of the battery can be realized by adding the bus balancing circuit, the cable erection cost is reduced, and the increase of the design complexity and the cost of a PCB (Printed Circuit Board) can be reduced.

The invention provides a simulation integration method and system for an FPGA communication module. The simulation integration method comprises the following steps that S1, an IP source code of the FPGA communication module is converted into an FPGA simulation module code of a C + + language; s2, based on the FPGA simulation module code, performing interface adaptation on a system bus access part for accessing an FPGA communication module in the all-digital simulation system; s3, introducing another module which is completely the same as the FPGA communication module as a symmetric module, and performing transceiving interface cross connection on the symmetric module and the FPGA communication module; and S4, performing interface adaptation on the communication data receiving side of the symmetric module according to a bus access mode in the full-digital simulation system. The FPGA module simulation is based on the source code of the FPGA, so that the accuracy of the FPGA simulation behavior is improved.

The invention provides a multi-core synchronization system and system component in a neural network processor, and belongs to the technical field of computers. The system comprises a neural network processor and a system component, the neural network processor comprises a task scheduling processor and a plurality of cores; the system component is respectively connected with the task scheduling processor and each core through a system bus; and the system component is used for communicating among the cores under the control of the task scheduling processor so as to enable the cores to synchronously execute the distributed model tasks. The system is used for efficient inter-core communication and synchronization.

A system on chip (SoC) for testing a component in a system during runtime includes a plurality of functional components; a system bus for allowing the plurality of functional components to communicate with each other; one or more wrappers, each connected to one of the plurality of functional components; and an in-system component tester (ICT). The ICT monitors, via the wrappers, states of the functional components; selects, as a component under test (CUT), at least one functional component in an idle state; tests, via the wrappers, the selected at least one functional component; interrupts the testing step with respect to the selected at least one functional component, based on a detection of a collision with an access from the system bus to the selected at least one functional component; and allows a connection of the at least one functional component to the system bus, based on the interrupting step.