353 results about "System bus" patented technology

A transmitting / receiving device for a bus system and a method for reducing an oscillation tendency in the transition between different bit states. The transmitting / receiving device has a transmitting stage for transmitting a transmission signal to a first bus wire of a bus of the bus system and for transmitting the transmission signal as an inverse signal to a second bus wire of the bus, and an asymmetry reduction module for reducing an asymmetry of bus signals arising in the bus wires. The asymmetry reduction module includes a polarity reversing diode, whose cathode is connected to the cathode of a reverse polarity diode of the transmitting stage. The asymmetry reduction module switches a potential of the cathode of the polarity reversing diode to a potential that is greater than or equal to a level of a recessive bus state.

The invention provides an active intervention type arc-extinguishing and resonance-eliminating device and method, and relates to the technical field of power system safety control, the device comprises an intelligent grounding module, the intelligent grounding module comprises a three-phase line led out from a system bus, and the three-phase line is grounded through a secondary side of a voltage transformer; a three-phase contactor and an impedance grounding transformer are sequentially connected in series between the system bus and the grounding end; when overvoltage and line resonance are caused by a non-single-phase earth fault of the power distribution network system, the PTC resonance elimination module is used for actively carrying out resonance suppression; the monitoring module is used for monitoring the working state of the device and generating state information; the processing module is used for processing the state information; and the alarm module performs a corresponding alarm action. According to the active intervention type arc and resonance elimination device and the matched fault treatment method thereof, innovative application of the intelligent grounding module and the PTC resonance elimination module is combined, and a comprehensive solution with high flexibility and self-adaptive capacity is formed.

Embodiments of the present disclosure provide a data transmission method, a data link layer, a chip interconnection interface, and an electronic device. The data transmission method is applied to the data link layer of the chip interconnection interface, the data link layer communicates with the system bus and the physical layer, the system bus operates in a first clock domain, and the physical layer operates in a second clock domain or in a second clock domain and a third clock domain. The method includes: the data link layer performs packet processing on the first data received from the system bus to obtain second data, and provides the second data to the physical layer; or, the data link layer performs unpacking processing on the third data received from the physical layer to obtain fourth data, and provides the fourth data to the system bus, wherein the data link layer partially operates in the third clock domain, and the first clock domain is different from the second clock domain and the third clock domain, the first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal.

The invention relates to the technical field of integrated circuit design, computer system structures and embedded systems, in particular to a high-real-time interrupt management system and method based on an RISC-V. The system comprises an improved platform-level interrupt controller and an optimized processor internal interrupt processing unit. The system and the method are in tight coupling cooperative work through a special interruption field interface and a system bus, and the system further comprises a core local interrupter, an SRAM, an APB bus matrix and other components. The improved platform-level interrupt controller is responsible for sampling, gating, arbitration, flow control and direct memory access transmission of external interrupt, and a plurality of functional modules are arranged in the improved platform-level interrupt controller; an interrupt processing unit in the processor is responsible for hardware handshake, vector jump, nested control and tail biting mechanism implementation. Through hardware field management, multi-level priority arbitration, hardware nesting and tail biting mechanisms, delay and overhead caused by software intervention in a traditional architecture are eliminated, nanosecond response is achieved, the system throughput rate is increased, the software development threshold is lowered, and the method is suitable for strong real-time scenes.

The invention belongs to the technical field of agricultural picking robot control, and provides an apple picking robot control method based on multi-sensor fusion, which comprises the following steps: deploying an RGB-D camera, a laser radar and a touch sensor, cooperatively collecting data and issuing the data to a system bus, and carrying out timestamp alignment, denoising processing and fusion; the method comprises the following steps: registering collected data to a unified robot coordinate system; establishing a voxel grid to set a voxel state; mapping to form a three-dimensional occupied grid model; obtaining a visibility index according to an RGB-D segmented region; performing weighted fusion in combination with the 3D point cloud set to obtain a fruit position; the method comprises the following steps: generating a motion feasible region by utilizing a three-dimensional occupied grid model, generating candidate poses by fitting a spherical angle increment, traversing the poses to carry out collision judgment, solving a joint track, calculating a quality index and a corresponding fusion weight through real-time sensing data, and carrying out weight adjustment and parameter correction according to a corresponding problem.

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an FPGA software and hardware cooperation testing platform based on a BFM. The test platform is formed by connecting a BFM with a Testbench, an AXI bus, an off-chip DDR and a DUT. The test process comprises the steps that the Testbench issues parameters through a transaction function interface, the BFM reads an excitation vector from the off-chip DDR / on-chip BRAM through an Avalon main interface, adaptive transmission of a system bus clock domain and a DUT clock domain is completed through double asynchronous FIFO (SNDfifo / RECfifo), and signal level interaction with the DUT is achieved through a pin protocol interface; the state machine dynamically switches long and short simulation modes according to the vector length, and drives the output vector to be written back and stored; the error monitoring unit monitors data flow faults in the whole process and outputs seven types of error reporting codes. The simulation equivalent frequency reaches a 10 megahertz level, and the method is suitable for efficient verification of the digital IC.

The invention provides bus hardware security monitoring equipment and a monitoring method based on an embedded system, master control equipment and slave equipment on a bus are connected with an intermediate control module, a bus monitoring module comprises a lightweight hash algorithm module and a DM module, all the master control equipment and slave equipment on the bus are connected with the input end of each channel, and the input end of each channel is connected with the corresponding channel. The outputs of all the channels are summarized to the interrupt management unit, the interrupt management unit serves as the output end of the bus monitoring module and is connected with the DMA, each channel comprises a monitoring selection unit, an access selection unit and a counting comparison unit, and an address range is set for each channel. Corresponding interrupt information is generated by monitoring the integrity abnormal behavior of a specific bus access sequence occurring in a system bus in the SoC security program running process. In a low-power-consumption application scene, the security of the embedded SoC can be improved, and key information is protected from being stolen and damaged.

The embodiment of the invention discloses a read-only code patch repairing method and device and a storage medium, and relates to the field of embedding. According to the method, the read-write request on the system bus is monitored, so that all-bus patch coverage of any code / data is realized. According to the patch repairing device, the patch pool containing various kinds of information is preset, and when a read-write request of a specific address is detected, corresponding patch data items can be quickly inquired and matched. And if the matching is successful and the patch is valid, replacing the target data according to the patch type or triggering a CPU exception instruction to enter an interrupt processing flow to obtain the patch. The method is universal and flexible, supports undifferentiated full-function patches, can cope with various code / data errors, and greatly reduces the risk of chip scrapping or re-burning caused by ROM code abnormity. By means of bus replacement, abnormal triggering and the like, effective repair of read-only codes is achieved, remarkable economic effects are achieved, production efficiency is improved, and product cost is reduced.

The invention discloses an accelerator supporting an attention mechanism, which is used for realizing matrix multiplication operation, scaling operation or nonlinear activation processing related to the attention mechanism, and is characterized in that a weight cache state machine module is used for controlling weight data to flow from a system bus to a weight cache unit; the thread cache state machine module is used for controlling thread data to flow from the system bus to the thread cache unit; the attention tensor processing unit state machine module is used for controlling loading and flowing of thread data and weight data from the two-dimensional systolic array in different directions, the thread data is controlled to be transmitted to the next processing unit in each period, and the weight data is spread to the processing units in the corresponding directions in a broadcast mode; the calculation result of the two-dimensional systolic array is transmitted to different branches according to whether nonlinear activation processing needs to be executed or not. According to the method, data filling is carried out on the matrix so that the matrix can be matched with the systolic array data stream, and then the attention mechanism with the variable sequence length is accelerated through hardware.

The invention relates to the technical field of artificial intelligence and computer hardware, and discloses an artificial intelligence calculation optimization system and method based on deep learning, and the system comprises a main calculation server node, a heterogeneous calculation acceleration module, a high-speed interconnection and storage module, and a uniform resource management and scheduling module. The main computing server node is connected with the heterogeneous computing acceleration module and the high-speed interconnection and storage module through PCIe buses, and the uniform resource management and scheduling module is integrated in the main computing server node and communicates with each hardware component through a system bus. Through integration of a main computing server node, a heterogeneous computing acceleration module, a high-speed interconnection and storage module and a uniform resource management and scheduling module, efficient execution of a deep learning computing task and optimal utilization of resources are realized; the efficient and stable execution of the deep learning calculation task is realized, and powerful support is provided for the development of the artificial intelligence technology.

Provided in the embodiments of the present disclosure are a protocol controller, a protocol control method, a chiplet, a system on a chip, and an electronic device. The protocol controller comprises: a first bus interface, which is connected to a system bus, wherein the first bus interface implements an inter-chip interconnect protocol, and a first partial sub-protocol of a peripheral protocol; and a second bus interface, which is connected to the system bus, wherein the second bus interface implements a second partial sub-protocol of the peripheral protocol, and the first partial sub-protocol and the second partial sub-protocol are configured to be implemented by different bus interfaces; and a chiplet uses one of the inter-chip interconnect protocol and the peripheral protocol at the same time.

The invention provides a starting method, related equipment and a readable storage medium, and is applied to the technical field of computers, the method is applied to a system-on-chip configured with a main processor and a bus monitoring module, the bus monitoring module provides an initialization operation sequence, and the operation sequence of the main processor is initialized based on the pre-stored initialization operation sequence. The bus monitoring module initializes the main processor and awakens the main processor after a first starting address of the main processor is configured, the first starting address is obtained after the main processor is awakened, and target starting firmware needing to be executed after the main processor is initialized is executed according to the first starting address. And the bus monitoring module initializes the main processor by using the pre-stored initialization operation sequence and skips a BL1 stage and a BL33 stage, so that the interaction times of BL1 firmware and BL33 firmware in the initialization process of the processor are reduced, the exposure risk is reduced, and the running safety of the processor is improved.

Disclosed in the present invention are a post-quantum cryptographic algorithm processor and a system-on-chip comprising same. The post-quantum cryptographic processor comprises an instruction fetch unit, a decode unit, an execute unit and a write-back unit; the execute unit comprises a parallel computing unit module, and the parallel computing unit module uses a part recomposition technology and an operator fusion technology and thus can use a same part to realize core operation of different computing types and bit widths of a post-quantum cryptographic algorithm; the system-on-chip for running the post-quantum cryptographic processor comprises: a system bus, the post-quantum cryptographic processor connected to the system bus, a storage unit connected to the post-quantum cryptographic processor, an external device interface connected to the system bus and a cache active prefetching / pre-storing data functional module which is connected to the post-quantum cryptographic processor and is combined with a DMA; and the post-quantum cryptographic processor communicates with an external device by means of the external device interface, and performs data and instruction read / write on the storage unit. The present invention reduces the power consumption and resource overhead of systems, and improves the running speed of a post-quantum cryptographic algorithm.

The invention provides a multi-protocol configurable interface circuit. The multi-protocol configurable interface circuit comprises a plurality of channel modules, a plurality of counter modules, an input / output module and a configuration register, the channel module comprises a state machine, a shift register and a cache module. The configuration register obtains configuration information through the system bus, and the configuration information comprises which protocol is selected. The counter module generates a shift signal required by a shift register in the channel module according to the configuration information; the input and output module selects the corresponding pins according to the configuration information and determines the function of each pin; and the channel module determines the mode of each channel and the required state of the state machine according to the configuration information to complete data transmission of the selected protocol. According to the invention, a hardware design which focuses on realizing clock and data transmission by matching a state machine state transition and a shift register with a cache module is adopted, so that software intervention and CPU occupation are reduced, and the overall efficiency is improved; hardware resources are reduced, and hardware flexibility is improved.

A transmitting module. The transmitting module has a first transmission stage for generating transmission currents for a first signal to be transmitted onto a bus of a serial bus system, a second transmission stage for generating transmission currents for a second signal to be transmitted onto the bus as a signal that is differential to the first signal, a third transmission stage for generating transmission currents for the first signal, and a fourth transmission stage for generating transmission currents for the second signal. The first to fourth transmission stages are connected in a full bridge. The first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series. Each of the first to fourth transmission stages has at least two current stages, connected in parallel with one another. Each of the at least two current stages has a switchable resistor.

The embodiment of the invention provides a system-on-chip for communication between an AUTBUS and an SPI slave module. The system-on-chip comprises a system bus, wherein an AUTBUS module and the SPI slave module are hung on the system bus; wherein an AUTBUS cache and an AUTBUS arbitration module are arranged in the AUTBUS module, and an SPI write cache and an SPI read cache are arranged in the SPI slave module; when the AUTBUS arbitration module controls the transmission direction to be a first transmission direction, the AUTBUS module reads cache data from an AUTBUS cache and sends the cache data to an SPI slave module in a direct memory access (DMA) mode, and the SPI slave module receives the cache data from a system bus and writes the cache data into an SPI write cache; when the AUTBUS arbitration module controls the transmission direction to be a second transmission direction, the AUTBUS module sends a first read request to an SPI slave module, the first read request comprises a target data length, and the SPI slave module reads cached data of the target data length from an SPI read cache and sends the cached data to the AUTBUS; therefore, the communication between the AUTBUS module and the SPI slave module can be realized, and the communication efficiency between the AUTBUS module and the SPI slave module is improved.

The embodiment of the invention discloses a bus balance hybrid topology circuit of a UPS system. The bus balance hybrid topology circuit comprises an A-phase branch, a B-phase branch, a C-phase branch, a battery positive discharge unit, a battery negative discharge unit and a bus balance unit, the A-phase branch comprises a first dual-BOOST PFC (Power Factor Correction) circuit; the C-phase branch circuit comprises a second dual-BOOST PFC circuit; the B-phase branch comprises a first change-over switch and a Vienna PFC circuit; the Vienna PFC circuit comprises a bus balance unit, and the Vienna PFC circuit is connected with the first change-over switch; the battery positive discharge unit and the battery negative discharge unit are respectively connected with the battery; and each circuit is connected with a direct-current power supply. By implementing the circuit provided by the embodiment of the invention, the midpoint cable of the battery can be removed, the voltage balance of the battery can be realized by adding the bus balancing circuit, the cable erection cost is reduced, and the increase of the design complexity and the cost of a PCB (Printed Circuit Board) can be reduced.

The invention provides a simulation integration method and system for an FPGA communication module. The simulation integration method comprises the following steps that S1, an IP source code of the FPGA communication module is converted into an FPGA simulation module code of a C + + language; s2, based on the FPGA simulation module code, performing interface adaptation on a system bus access part for accessing an FPGA communication module in the all-digital simulation system; s3, introducing another module which is completely the same as the FPGA communication module as a symmetric module, and performing transceiving interface cross connection on the symmetric module and the FPGA communication module; and S4, performing interface adaptation on the communication data receiving side of the symmetric module according to a bus access mode in the full-digital simulation system. The FPGA module simulation is based on the source code of the FPGA, so that the accuracy of the FPGA simulation behavior is improved.

A system on chip (SoC) for testing a component in a system during runtime includes a plurality of functional components; a system bus for allowing the plurality of functional components to communicate with each other; one or more wrappers, each connected to one of the plurality of functional components; and an in-system component tester (ICT). The ICT monitors, via the wrappers, states of the functional components; selects, as a component under test (CUT), at least one functional component in an idle state; tests, via the wrappers, the selected at least one functional component; interrupts the testing step with respect to the selected at least one functional component, based on a detection of a collision with an access from the system bus to the selected at least one functional component; and allows a connection of the at least one functional component to the system bus, based on the interrupting step.

The utility model discloses a nuclear power station master control room architecture based on a DCS. The nuclear power station master control room architecture comprises a security-level DCS, a non-security-level DCS and a backup panel. The backup panel is provided with a first security level control display device, the non-security level DCS comprises a work station, and the work station is provided with a second security level control display device, a non-security level control display device and a conventional monitoring instrument; the safety-level DCS comprises an equipment interface cabinet, a safety bus, a data transmission cabinet, a reactor protection cabinet and a safety-level system bus which are in communication connection in sequence; the non-security-level DCS further comprises a field control cabinet and a server. Compared with an onshore nuclear power station master control room in the related technology, the nuclear power station master control room architecture based on the DCS reduces a whole set of diversified driving system equipment, and integrates diversified driving functions into a work station for realization. A man-machine interface of the master control room is simplified, the human factor risk is reduced, meanwhile, the requirement for the building space is lowered, and reference is provided for the design of the master control room arranged in a compact mode.

In a processing system, a conversion circuit coupled to a system bus generates a flow control unit (FLIT) and provides the FLIT to a link interface circuit for transmission over an external link. The external link may be a peripheral component interface (PCI) express (PCIe) link coupled to an external device comprising a cache or memory. The conversion circuit generates the FLIT, including write information based on the write instruction, metadata associated with at least one cache line, and cache line chunks, including bytes of a cache line. The cache line chunks may be chunks of one of the at least one cache line. Including the metadata in the FLIT avoids separately transmitting the at least one cache line and the metadata over the external link, which improves performance compared to generating separate transmissions. In some examples, the FLIT corresponds to a compute express link (CXL) protocol FLIT.

The invention discloses a vehicle information display method, a system-on-chip, electronic equipment, a storage medium and a program product, and is applied to the system-on-chip, the system-on-chip comprises a CPU, a GPU and a memory unit which are mutually connected through a system bus; the method comprises the steps that a CPU transmits vehicle information obtained from the outside to a memory unit through a system bus, so that a GPU reads the vehicle information, performs 3D rendering processing and outputs and displays the vehicle information; when the GPU breaks down, the CPU generates two-dimensional display information at least according to the vehicle information and outputs and displays the two-dimensional display information. According to the embodiment of the invention, when the GPU breaks down, the CPU takes over the display processing of the vehicle information, and carries out the two-dimensional display processing and output display of the vehicle information in a simplified drawing mode, so that the output display function of the vehicle information is completed, and the user experience is improved. And negative effects caused by excessive occupation of CPU resources when 3D rendering processing is carried out on the vehicle information are also avoided.

A simple configuration aims to reduce MCU vulnerabilities. [Solution] The control device 10 includes an MCU 20. The MCU 20 has a CPU 22, a system bus 26, a storage device 28, and an address translation device 24 that translates addresses between the CPU address space of the CPU 22 and the system bus address space of the system bus 26 in accordance with translation rules set in a special function register 24A. The MCU 20 starts up in an unrestricted mode in which all addresses in the CPU address space are available, and after startup, when a predetermined condition is met, it switches to a restricted mode in which only a portion of the addresses in the CPU address space are available. The special function register 24A allows the translation rules to be set and read when in the unrestricted mode, and does not allow the translation rules to be set or read when in the restricted mode.

The utility model relates to an actuator power supply control circuit and a robot. The actuator power supply control circuit comprises a control circuit used for supplying power to a boost circuit; the first end of the booster circuit is connected with the control circuit, the second end of the booster circuit is connected with the slow start circuit, and the booster circuit is used for receiving the output voltage of the control circuit and boosting the output voltage to obtain boosted voltage; and the slow start circuit is used for receiving the boosted voltage and controlling the slow start time of the actuator power supply. By adopting the actuator power supply control circuit, the problem of transient drop of the system bus voltage caused when a plurality of actuator power supplies are started at the same time can be avoided, and the reliability of the system is further guaranteed. And meanwhile, stable operation of the actuator can be realized on the basis of not additionally increasing the system power supply capacity, and the energy efficiency loss is reduced.

The present application relates to a radar system and a radar signal processing method. The radar system includes: one or more transmitting channel devices for processing a radar signal to be transmitted according to a first control parameter to generate a transmitted signal; one or more receiving channel devices for receiving an echo signal of the transmitted signal and processing the received echo signal according to a second control parameter to obtain a received signal; and a control processor for performing read and write control on the first control parameter and the second control parameter connected to a system bus, wherein the first control parameter and the second control parameter are preset in a storage medium of the radar system and / or set by the control processor. The present application relates to a radar system capable of defining parameters, which can be compatible with various systems, such as FMCW radar, PMCW radar, pulse radar and other systems, and can achieve the effect of flexibly selecting a suitable technical system as needed.

This application discloses a valve island diagnostic method, control system, bus valve island, and storage medium, relating to the field of electrical control. The method includes: acquiring the real-time power signal of the valve seat; when the real-time power signal meets preset power diagnostic conditions, acquiring the valve disc insertion monitoring signal to obtain the number of valve discs inserted on the valve seat, thereby determining the theoretical current value of the valve seat; when the real-time current value in the real-time power signal is less than or equal to the theoretical current value of the valve seat, acquiring the number of operations of each valve disc and the number of operations of the actuator connected to the valve disc; and diagnosing the mechanical life of the valve island based on the number of operations of the valve discs and the actuator, thereby obtaining the valve island diagnostic result. This application solves the problem that bus valve islands lack fault diagnosis functions, and provides multiple diagnostic functions for the valve island, enabling timely understanding of the valve island's condition and timely implementation of corrective measures.

The invention discloses a GJB289A bus ICD missing-oriented test method. The GJB289A bus ICD missing test method comprises the following steps: acquiring messages on a GJB289A bus in a normal working mode of a tested system through a first GJB289A terminal module, and forming a recording file; extracting a non-broadcast message in the recorded file, converting the extracted message into a BC instruction, and sending the BC instruction to a GJB289A bus of the tested system; obtaining the address of the remote terminal from the instruction word converted from the current instruction according to the response condition of the remote terminal to the sent instruction; obtaining a simple network message of the remote terminal; extracting an instruction from the obtained simple network message of the specified remote terminal, and judging whether the GJB289A bus communication of the tested system is normal or not; and when the GJB289A bus communication of the tested system is normal, testing the state of the specified remote terminal according to the comparison condition of the current response and the response of the pre-recorded simple network message. According to the invention, the problem that the function of the tested product cannot be tested under the condition that the ICD of the GJB289A bus is lacked is well solved.

The invention discloses a bus load prediction method and device, a storage medium and an electronic device, and relates to the technical field of power system bus load prediction. The method comprises the following steps: acquiring a target reference curve of a bus load in a first preset time period; fitting the target reference curve to obtain at least one type of fitting curve; determining an initial prediction result based on the at least one type of fitted curve; and performing error adjustment on the initial prediction result based on the weight optimization curve to obtain a target prediction result. According to the invention, the technical problem that the load prediction result cannot be obtained in time due to the fact that a large amount of data needs to be collected and when the bus ultra-short-term load prediction is carried out, the requirement on hardware performance is high and the situation that the data is not collected in time easily occurs in the prior art is solved.

The electronic paper device and its refreshing method provided by the present application include a first housing, an electronic paper display screen, a first conductive contact, a first system bus, and a power management circuit. The electronic paper display screen is disposed on the first housing. The first conductive contact is disposed on the first housing. The first conductive contact is used for contact connection with an electronic paper refreshing device. The first system bus and the power management circuit are disposed inside the first housing. The first system bus is connected to the first conductive contact, the electronic paper display screen, and the power management circuit. The power management circuit is connected to the electronic paper display screen. The electronic paper refreshing device provides power and display information to the first system bus through the first conductive contact. The electronic paper device is connected to the first system bus and the power management circuit through the first conductive contact, which can simplify the structure of the electronic paper device.

An electronic device is provided. The electronic device includes: a plurality of master devices; and a shared subsystem including: a system bus connected to the plurality of master devices; a shared slave device; and a shared slave access controller connected to the system bus, and configured to determine a master identification number corresponding to an access request received from a first master device of the plurality of master devices, determine whether or not to permit the first master device to access the shared slave device during an access window of the shared slave device based on the master identification number, and control access authority of the first master device during the access window.