41 results about "System bus" patented technology

This application discloses a valve island diagnostic method, control system, bus valve island, and storage medium, relating to the field of electrical control. The method includes: acquiring the real-time power signal of the valve seat; when the real-time power signal meets preset power diagnostic conditions, acquiring the valve disc insertion monitoring signal to obtain the number of valve discs inserted on the valve seat, thereby determining the theoretical current value of the valve seat; when the real-time current value in the real-time power signal is less than or equal to the theoretical current value of the valve seat, acquiring the number of operations of each valve disc and the number of operations of the actuator connected to the valve disc; and diagnosing the mechanical life of the valve island based on the number of operations of the valve discs and the actuator, thereby obtaining the valve island diagnostic result. This application solves the problem that bus valve islands lack fault diagnosis functions, and provides multiple diagnostic functions for the valve island, enabling timely understanding of the valve island's condition and timely implementation of corrective measures.

A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in a plurality of groups, and circuits coupled to the memory devices. The circuits including circuitry configurable to receive from the memory controller a system clock and input control and address (C / A) signals, and to generate a module clock signal and module C / A signals in response to the system clock and input C / A signals. The circuits further include circuitry configurable to generate a plurality of local clock signals corresponding, respectively, to the plurality of groups of memory devices, and to output the plurality of local clock signals to respective groups of the memory devices. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices.

A data access processing circuit, control method, and electronic device are disclosed. The circuit, used for data access between multiple functional modules and a system bus, includes: an arbitration circuit connected to the multiple functional modules, configured to receive access request signals and urgency signals sent by the multiple functional modules, determine a target functional module from the multiple functional modules based on the urgency signal, send a confirmation signal to the target functional module, and generate internal operation instructions based on the access request signals; and a conversion circuit connected to the arbitration circuit, the multiple functional modules, and the system bus, configured to receive the internal operation instructions, convert the internal operation instructions into bus operation instructions conforming to the system bus protocol and send them to the system bus, and transmit data corresponding to the bus operation instructions between the system bus and the target functional module. This application has the technical effect of improving data access processing efficiency.

This application relates to the field of simulation and testing technology, and in particular to a remote CAN simulation system and method. The system includes: a first terminal and a second terminal connected via Ethernet; the second terminal accesses the system to be simulated via a CAN bus or CANFD bus. The first terminal receives remote command parameters input from an external source, packages the remote command parameters based on a preset protocol to obtain a message body to be sent, and sends the message body to the second terminal. The second terminal receives the message body to be sent, parses it into a local call instruction, and calls the SocketCAN function according to the local call instruction to complete data interaction with the bus of the system to be simulated. This system provides a highly versatile remote CAN simulation architecture, which helps reduce system usage costs and facilitates deployment.

An automation system includes a control device, a system bus, a first field device, and a second field device. The control device includes a system bus interface for communication with the field devices by the system bus, and each field device includes a data interface for communication by the system bus. Each field device includes a monitoring input for receiving a monitoring signal and a monitoring output for outputting a monitoring signal. The monitoring input of the first field device is coupled to the monitoring output of the second field device by the system bus, and the monitoring input of the second field device is coupled to the monitoring output of the first field device by the system bus.

The present application belongs to the technical field of aircraft design, and particularly relates to an avionics Ethernet-based bus architecture for an avionics system of a trainer aircraft. The bus architecture comprises a core processor and devices / subsystems, wherein the devices / subsystems comprise a video processor, a display end, a data loading recorder and an electromechanical management computing system; the video processor, the display end, the data loading recorder and the electromechanical management computing system are all connected to the core processor; the core processor comprises a first core processor and a second core processor, the first core processor and the second core processor are hot standbys for each other, and the first core processor and the second core processor are both interconnected to the devices / subsystems by means of a bus; and when an error occurs in either core processor, the core processor in a normal state can continue operating, without affecting normal task processes of the devices / subsystems, and without propagating the error throughout the entire combat flight software, thereby ensuring the normal operation of the avionics system.

The application provides a bus performance simulation analysis method and device and electronic equipment, and relates to the technical field of computer system bus. The method comprises the following steps: acquiring a bus performance simulation waveform file; determining a signal extraction file based on a preset signal configuration file; performing statistical analysis on the signal extraction file based on a preset access analysis script to obtain an access information statistical file; labeling data meeting a preset condition in the access information statistical file based on a preset labeling generation script, and generating a waveform labeling script; and extracting multiple data in the bus performance simulation waveform file according to the flexibly configured signal configuration file, which greatly expands the analyzable data. The access request is analyzed and labeled piece by piece, and statistical analysis is performed on all data to improve the flexibility of the analysis method. Since the bus performance simulation waveform file is fixed data, simulation does not need to be performed again when new analysis statistical information is added, time is saved, and efficiency is improved.

This invention discloses a redundant architecture method for a UAV flight control system, relating to the field of UAV control technology. It includes redundant design for four layers: flight sensor system, redundant flight control computer system, bus communication system, and actuator system. The bus communication system employs a three-bus redundant architecture consisting of a 1553B dual-bus, FlexRay bus, and CAN bus. The redundant flight control computer system features automatic switching between three modes: triple-mode redundancy, dual-mode redundancy, and single-mode redundancy, and possesses online fault channel repair and reconnection capabilities. The actuator system includes aerodynamic control surface segment redundancy, servo electrical dual-path redundancy, and dual-path access redundancy via the CAN bus main path and RS422 backup path. This invention, using the aforementioned redundant architecture method for a UAV flight control system, achieves long-endurance, highly reliable flight control with no awareness of single faults, return capability in the event of dual faults, and no degradation due to bus faults.

The application discloses an intelligent dual-BIOS self-recovery method and system, which comprises the following steps: performing hash calculation on the main and standby BIOS chips based on a hardware root of trust, establishing an initial trusted state identifier, and generating trusted state judgment information and a running state vector graph through dynamic measurement; comparing the vector graph with dual-BIOS configuration data, constructing a structured difference graph, combining mode matching and state reasoning to output difference potential intention judgment information; making a repair decision based on the trusted state and the difference intention, and building an isolated repair execution environment if repair is needed; in the environment, extracting pure data blocks from a trusted source according to the difference graph, merging the pure data blocks with faulty data in a cache area to generate a correction image; repairing the faulty chip in a system bus idle window by using the image, re-performing trusted identification after the repair, generating a full-disk erasing request and prompting switching to a healthy BIOS if the chip is still untrusted, so that the final chip-level recovery is completed.

The embodiment of the application discloses a Lua-based reinforcement method and device, a terminal and a storage medium, and the method comprises the following steps: starting a master component, registering a dbus interface, and starting a security item management component; receiving reinforcement parameters, inputting the reinforcement parameters into the security item management component through the dbus interface; reading the reinforcement baseline template by using the security item management component, generating a reinforcement baseline configuration file, reading the reinforcement baseline configuration file, loading reinforcement items according to the reinforcement baseline configuration file, and writing the reinforcement items into a reinforcement item queue; calling a Lua reinforcement resource management component, loading a Lua script resource package, and exporting C++ functions to a Lua environment; encapsulating the functions of the security item management component and the Lua reinforcement resource management component into externally callable interfaces through a dbus system bus; binding the calling request of the dbus interface with a corresponding processing function of the terminal; and loading corresponding binary Lua scripts for reinforcement.

This invention relates to an architecture compatible with cache / tcm for high-speed DSP access to a low-speed bus; it includes: a one-to-two bus switch h1to2 switching module, a two-to-one bus switch h2to1 switching module, a two-to-two system bus interconnect s2to2 module, and a cache; one master terminal of the h1to2 switching module is connected to the DSP, and two slave terminals are respectively connected to the cache and one master terminal of the s2to2 module; two master terminals of the h2to1 switching module are respectively connected to the cache and one slave terminal of the s2to2 module, and one slave terminal is connected to the bus; the remaining master and slave terminals of the s2to2 module are respectively connected to the bus and the cache; by switching the master and slave terminals of the h1to2 and h2to1 switching modules, a data access path from the DSP to the bus via the cache is established in cache mode; or, by combining the access address range of the slave terminals of the s2to2 module, in tcm mode, data flow processing is performed from the DSP to the cache via the s2to2 module, from the DSP to the system bus via the s2to2 module, and from the system bus to the cache via the s2to2 module. This invention supports both cache and TCM working modes.

The application discloses a high-speed encryption and decryption embedded security subsystem and method. The system comprises an SPI interface, a DMA module, an arithmetic core array, a CPU and a system bus; the SPI interface is additionally provided with a transmission ready TR and a receiving ready RR special handshake signal line; the DMA module is divided into a sending DMA and a receiving DMA; the arithmetic core array comprises at least three parallel arranged arithmetic cores. The sending DMA responds to the TR signal to move data into an idle arithmetic core and starts operation; the receiving DMA moves the result to the SPI interface after the operation of the arithmetic core is completed and triggers the RR signal. Through the double DMA cooperation and the multi-arithmetic core pipeline scheduling, the SPI interface realizes the full-duplex parallel transmission of the command issuing and the response uploading, the CPU is only responsible for the initialization and does not participate in the real-time data processing, so that the interface bandwidth utilization and the encryption and decryption throughput are greatly improved, and the system is suitable for high-bandwidth real-time security application scenarios.

The application discloses a processor, a control method of the processor and an electronic device, and belongs to the technical field of computers. The processor provided by the application comprises a processor core, a debugging module, a processor internal bus, and a plurality of tightly coupled components. The debugging module is connected to the processor internal bus through a system bus access (SBA) interface. The processor core and the debugging module both serve as master devices of the processor internal bus, and the plurality of tightly coupled components are all connected to the processor internal bus and serve as slave devices of the processor internal bus. By taking the debugging module as a master device on the processor internal bus, the application provides the access capability of the debugging module to the plurality of tightly coupled components, and is beneficial to improving the debugging capability of the debugging module.

The application discloses a CAN bus fault test system, a CAN bus fault test method, device, equipment, medium and product. The CAN bus fault test system comprises a controller, a plurality of relays, a plurality of CAN buses and an upper computer, the high and low level lines of the CAN buses are connected with the controller, two channels of each relay are connected with the high and low level lines of the CAN buses, and the plurality of relays and the controller are connected with the upper computer. Through the technical scheme, the CAN bus fault test can be automatically performed, the CAN bus fault test efficiency is improved, and the CAN bus fault test accuracy is improved.

The application relates to the technical field of embedded system bus communication and device management, and provides a method for accessing multiple same-address devices by using extended I2C. By constructing a virtual device mapping table, and carrying out access request conversion and channel switching control through channel management middleware, the problem that multiple same-address slave devices on the same I2C bus cannot be concurrently and reliably accessed is solved, the method has the advantages that physical channels can be safely switched during the idle period of the bus, access conflict avoidance and unified management are realized through kernel-level scheduling, and the reliability of multi-device access and the maintainability of the system are improved.

The present application relates to the field of computer system bus design, more particularly to a kind of bridging device and method of AHB bus and PLB bus based on SoC platform.The bridging device provided by the present application includes protocol conversion module, for converting the protocol signal of AHB bus into the protocol signal of PLB bus, and converting the response signal of PLB bus into the response signal of AHB bus;Clock domain spanning module, for synchronously processing the cross-clock domain signal of AHB bus and PLB bus;Address mapping module, for realizing the mapping and address decoding of AHB address space to PLB address space;Data cache module, for caching read-write request, to-be-transmitted data from AHB bus and response data from PLB bus;Error processing module, for detecting and processing exception in data transmission process, and generating corresponding error response signal.The present application realizes seamless protocol conversion and efficient data transmission between AHB and PLB two buses, effectively improves system compatibility.

The invention provides a direct memory access (DMA) controller. The DMA controller has an address register, a data register and transfer circuitry for transferring data over a bus of a computing system. The DMA controller is configured to use the transfer circuitry to read data over the bus from a memory location having a first memory address, wherein the data comprises a second memory address, and store the second memory address in the address register, and use the transfer circuitry to transfer data over the bus between a memory location having the second memory address, or having a memory address derived from the second memory address, and the data register.

This invention relates to a multi-bus data fusion processing method and system based on a logging tool, belonging to the field of oil and gas drilling measurement data transmission technology. The method includes receiving logging data collected by the logging tool's measurement probe and different data packets sent by the system bus; performing preliminary processing on the received logging data, including self-identification, self-diagnosis, and self-correction; identifying and converting the different received data packets; performing real-time fusion processing on the self-identified, self-diagnosed, and self-corrected logging data and the identified and converted data packets; and packaging the real-time fused data according to different communication protocols, and sending the packaged data to the system bus and / or storage unit. This invention forms a multi-bus data fusion processing system, which is embedded in the logging tool connected to the drilling string, enabling data interaction between the logging tool and other instruments in the instrument string, and achieving parallel processing and self-diagnosis of multiple sets of data.

This invention discloses a real-time velocity estimation method and system for humanoid robots based on temporal feature fusion, relating to the field of robotics technology. The method includes: collecting proprioceptive sensory data from the robot's random walks; constructing an LSTM+MLP cascaded hybrid neural network architecture, training and optimizing it to obtain a hybrid neural network model; collecting raw proprioceptive sensory data streams through sensors to obtain standardized feature data; deploying the hybrid neural network model to an embedded main control platform for inference operations, outputting a three-dimensional linear velocity prediction value; performing trapezoidal numerical integration on the three-dimensional linear velocity prediction value to generate displacement odometry information and distributing it to the robot system bus. This invention employs an LSTM+MLP cascaded hybrid neural network architecture, enabling rapid capture of motion physical characteristics. Experimental data shows that the model can achieve a rapid decrease in mean square error and reach stable convergence within a short training period, reducing the migration cost and data dependency of the algorithm across different robot platforms.

This invention provides a bus scheduling optimization method and system utilizing analog circuit mirror feedback, relating to the field of bus transmission scheduling technology. It involves constructing an analog circuit mirror network corresponding to the system bus, where analog branch paths correspond to bus branches in the system bus. The system bus's operating status parameters are monitored in real time and mapped to circuit element parameters in the analog circuit mirror network. The analog circuit mirror network is driven, and current is shunted within it based on Kirchhoff's current law. The shunted current values ​​on each analog branch path are measured, and the operating status parameters of the corresponding bus branches are dynamically adjusted based on these measured values. The advantages include: automatically completing complex load distribution calculations using Kirchhoff's current shunting principle in analog circuits without requiring logical operations; rapid response, avoiding instantaneous congestion; and reusability across different bus architectures.

The application discloses a SOC chip USB interface multiplexing circuit and a control method, and relates to the technical field of SOC chips, in particular to a SOC chip USB interface multiplexing circuit and a control method.The SOC chip USB interface multiplexing circuit comprises a USB interface control module, a storage module, a processor, a multiplexing control module and a peripheral control module; the USB interface control module comprises a USB controller, a JTAG controller and an I2C controller, the USB interface control module is provided with a first IO port and a second IO port; the processor is connected with the JTAG controller, and the processor is connected with a system bus; the storage module comprises a ROM storage unit and a RAM storage unit; the multiplexing control module is used for controlling multiplexing of the first IO port and the second IO port; the peripheral control module is connected with the system bus and the multiplexing control module, and the peripheral control module is provided with a BOOT_CTL register, which is used for temporarily storing a USB interface start control mode. The USB interface can be multiplexed, the SOC chip system-level debugging, mass production testing and burning can be supported without occupying additional pins, and the SOC chip manufacturing cost is reduced.

This application provides a hardware device and method for memory management based on address monitoring. The CPU encapsulates the preset storage address of the pre-received data or the storage address of the already stored data in memory, along with other data information, into a descriptor, and stores the descriptor in memory via the system bus. The system bus can monitor and record the write address signals of the descriptors in memory. The DMA controller can monitor the write address signals of the descriptors recorded on the system bus, determine the number of descriptors based on the monitored write address signals, and update the number of descriptors in the register set. The processing module can retrieve the corresponding descriptor from memory based on the updated number of descriptors and perform data writing or data reading based on the descriptor. In this scheme, the DMA controller can monitor the write address of the memory descriptors through the system bus to know the accurate allocation of descriptors, ensuring that the descriptors have been allocated before updating the register set and triggering the descriptor retrieval operation.

The application discloses a system-on-chip-based peripheral attribute sorting method, which comprises the following steps: establishing communication with peripherals mounted on a system bus through a bridge and distinguishing different types of peripherals; configuring the number of different peripheral attributes in each type of peripheral; and sorting the peripheral attributes of each type of peripheral according to the number of the same type of peripheral attribute. By executing the peripheral attribute sorting method, the system bus is mounted with multiple types of peripherals, and the different peripheral attributes in each type of peripheral are allowed to be configured and sorted according to the number of the same type of peripheral attribute, so that the automatic configuration of the different peripheral attributes in each type of peripheral is completed in the same type of peripheral attribute sorting mode of different peripherals, the peripheral system where the bridge is located is more universal, the demand of different chip interface design projects is compatible, and different application scenarios are adapted.

This invention discloses a pure hardware tactile-force fusion servo closed-loop system, independent of a central processing unit and entirely implemented using combinational logic circuits and finite state machines. It includes a tactile data acquisition interface that directly receives tactile data through an independent channel without going through a system bus; a tactile feature extraction circuit that extracts contact features from the tactile data in real time; a force fusion circuit that fuses the contact features with force sensor data in hardware and outputs a fused force feedback signal; and a slip detection circuit that performs multi-level progressive slip determination based on the contact features. This invention solves the problems of high latency and high system resource consumption caused by software-dependent tactile-force fusion in existing technologies. It achieves a sampling frequency of over 10kHz, making it suitable for precise robot manipulation and human-computer interaction scenarios.

This invention discloses a method, apparatus, and electronic device for fault detection in power systems. The method includes: in response to a power system fault, connecting a preset resistor to the power system and acquiring the zero-sequence voltage of the power system bus and multiple zero-sequence currents at multiple monitoring points in the power system, wherein the preset resistor is connected in parallel with the neutral point of the power system; projecting the multiple zero-sequence currents onto the zero-sequence voltage of the bus to obtain steady-state projections of the multiple zero-sequence currents; determining the correlation coefficient between the zero-sequence currents at any two adjacent monitoring points based on the steady-state projections of the multiple zero-sequence currents; and determining the faulty section from multiple sections of the power system based on the locations of the multiple monitoring points and the correlation coefficient between the zero-sequence currents at any two adjacent monitoring points, wherein the multiple sections are obtained by dividing the power system lines using multiple monitoring points. This invention solves the technical problem of the high difficulty in locating power system faults.

The application discloses a human-shaped robot real-time speed estimation method and system based on time sequence feature fusion, relates to the technical field of robots, and comprises the following steps: collecting body sense data of robot random walk; constructing an LSTM+MLP series hybrid neural network architecture, and obtaining a hybrid neural network model after training and optimization; collecting original body sense data streams through sensors to obtain standardized feature data; deploying the hybrid neural network model to an embedded host platform to perform inference operation, and outputting three-dimensional linear speed prediction values; performing trapezoidal numerical integration processing on the three-dimensional linear speed prediction values to generate displacement odometer information and distribute the information to a robot system bus. The application is provided with the LSTM+MLP series hybrid neural network architecture, so that the motion physical characteristics can be quickly captured, and experimental data show that the model can realize the rapid decline of mean square error and reach stable convergence in a short training period, and the migration cost and data dependence of the algorithm between different robot platforms are reduced.

A system for predictive modeling of sustainability outcomes using economic time series indicators, wherein the system comprises: a data acquisition unit with a variety of input ports, signal conditioning circuits, and synchronization circuits configured to receive time-indexed economic data streams from external sources and align the received data streams based on a common time reference; a buffer storage unit operationally connected to the data acquisition unit and comprising sequential storage registers configured to store the time-aligned data in an ordered sequence corresponding to the time intervals;a preprocessing unit electrically connected to the buffer storage unit, the preprocessing unit comprising filtering, normalization, and interpolation circuits configured to remove noise, scale the data, and compensate for missing or irregular data points in the stored time-series data; a feature extraction unit coupled to the preprocessing unit comprising vector transformation circuits configured to generate temporal feature vectors from the preprocessed data, including trend components, periodic components, and correlation values;a predictive processing unit consisting of a plurality of interconnected arithmetic processing elements, weighted signal multipliers, accumulation registers and activation circuits arranged in layered connections, wherein the predictive processing unit is configured to receive the temporal feature vectors and generate predictive outputs corresponding to the sustainability results; a temporal dependency processing unit consisting of delay elements, shift registers and sequence alignment circuits configured to preserve historical data dependencies over multiple time intervals and provide temporally extended data to the predictive processing unit;a decision processing unit coupled with the prediction processing unit, comprising comparator circuits, threshold evaluation circuits, and classification circuits configured to categorize prediction outputs into predefined sustainability states; an output interface unit consisting of display drivers, communication transceivers, and memory controllers configured to display and transmit the categorized sustainability states to external systems or display devices;a control processor with clock generators, control signal distribution circuits and bus arbitration circuits, configured to coordinate the operation of the data acquisition unit, the preprocessing unit, the feature extraction unit, the predictive processing unit, the temporal dependency processing unit, the decision processing unit and the output interface unit via a system bus; and a power control unit consisting of voltage regulators, current control circuits and thermal sensor elements configured to ensure stable operation of the system under varying load conditions.

The application discloses a kind of distributed chip systems based on star chain type network, comprising: central node and multiple distributed nodes;Wherein, the central node and multiple distributed nodes form 1 or more ring star chain networks, the starting point and end point of each ring star chain network are the central node, and the direction of the ring star chain network passage is reversibly configurable.It can also be configured to the working state of distributed node, to the state of chain or hang chain activation state.The distributed chip system based on star chain type network provided by the embodiment of the application can design the chip system bus into ring star chain network structure, realize low cost, network topology structure is simple, easy to expand and maintain, and by adding star chain passage direction reversibly configurable function and node chain function, the transmission efficiency of bus can be effectively improved, power loss is reduced, and the demand of high-performance chip distributed node efficient access and low latency can be met.

The application discloses a kind of future community digitization management system and method based on real scene three-dimensional map.The system includes perception layer, data layer, twin layer, intelligent layer, application layer and system bus;Method is, S1, real scene three-dimensional visualization;S2, dynamic monomerization query;S3, space-time situation prediction;S4, cross-modal fusion;S5: real scene three-dimensional visualization, dynamic monomerization query, space-time situation prediction and cross-modal fusion capability based on steps S1-S4 are constructed, provide community governance, public service and emergency command business collaborative service.The application introduces three-dimensional Gaussian sputtering efficient representation, point cloud semantic segmentation based on Transformer, space-time graph neural network prediction and cross-modal attention fusion mechanism, solve the problems of low rendering efficiency, poor monomerization accuracy, weak prediction ability and difficult data fusion in prior art.