128 results about "Pass gate" patented technology

A semiconductor memory device, and a semiconductor package and an electronic system including the same are provided. The semiconductor memory device includes a substrate including a plurality of mat regions and a mat separation region between ones of the mat regions, a peripheral circuit structure on the substrate and including peripheral circuits, a cell array structure on the peripheral circuit structure, a first through-via extending into the substrate in the mat separation region, and a second through-via extending into the cell array structure on the mat separation region and electrically connected to the first through-via, wherein the second through-via overlaps the first through-via.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

The utility model relates to the technical field of motors, in particular to a motor back electromotive force automatic bleeder circuit and a swing type quick pass gate. According to the utility model, through arranging the passive back electromotive force discharge unit and the unidirectional conduction unit, when the motor generates back electromotive force, automatic conduction of the back electromotive force discharge unit and automatic cut-off of the unidirectional conduction unit are realized, thereby realizing automatic discharge of the back electromotive force, stably protecting a single-board device from being damaged by the back electromotive force of the motor, and prolonging the service life of the single-board device. Fixed and universal device type selection is realized and is not influenced by a motor type and a voltage withstanding value of a single-board device; and meanwhile, the equipment can still discharge back electromotive force under the condition of power failure, so that the single board is protected.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first trench in a substrate, disposing a first gate electrode in the first trench, and disposing a dummy gate electrode on the first gate electrode in the first trench. The method also includes removing the dummy gate electrode from the first gate electrode and forming a first doped region in the first gate electrode.

Disclosed herein is a frame buffer pixel circuit having a first data pass gate transistor G1, first storage capacitor C1, a voltage boosting line Vb, source follower transistor F, pull-down transistor P, and second data pass gate transistor G2. The pull-down transistor P is connected to the drain of transistor F and source of transistor G2 and the storage capacitor C1 is connected to a voltage boosting line Vb. In the operation, Vb is set to zero volt when data is transferring to C1 capacitor through G1 gate. After the frame data are loaded onto C1 capacitors in all pixels, Vb is set to designed voltage and G2 gates in all pixels are opened to charge Clcd capacitors. Vb is then set to zero volt again before starting to load next frame data onto pixels. Such process is iterated in the liquid crystal on silicon (LCOS) working time.

Exhibiting a semiconductor structure: a lower unit level comprising a first lower field-effect transistor, FET, (FET_1B) of a first conductivity type, a second lower FET (FET_2B) of the first conductivity type, a third lower FET (FET_3B) of the first conductivity type, and a fourth lower FET (FET_4B) of the first conductivity type, wherein the first lower FET (FET_1B) is electrically connected to the second lower FET (FET_2B), the third lower FET (FET_3B) is electrically connected to the fourth lower FET (FET_4B), the first lower FET (FET_1B) is arranged diagonally to the fourth lower FET (FET_4B), the second lower FET (FET_2B) is arranged diagonally to the third lower FET (FET_3B), and the first lower FET (FET_1B) and the fourth lower FET (FET_4B) are pass-gates. are; and an upper unit level stacked above the lower unit level, comprising a first upper FET (FET_1T) of a second conductivity type different from the first conductivity type, arranged directly above the first lower FET (FET_1B), a second upper FET (FET_2T) of the second conductivity type, arranged directly above the second lower FET (FET_2B), a third upper FET (FET_3T) of the second conductivity type, arranged directly above the third lower FET (FET_3B), and a fourth upper FET (FET_4T) of the second conductivity type, arranged directly above the fourth lower FET (FET_4B), wherein the first upper FET (FET_1T) is electrically connected to the second upper FET (FET_2T), and the third upper FET (FET_3T) is electrically connected to the fourth upper FET (FET_4T), and the first upper FET (FET_1T) is a first The dummy transistor is wired for cross-coupling (130) with the third upper FET (FET_3T),and the fourth upper FET (FET_4T) is a second dummy transistor wired for cross-coupling (130) with the second upper FET (FET_2T), and the second lower FET (FET_2B) and the second upper FET (FET_2T) are wired to provide a first inverter, and the third lower FET (FET_3B) and the third upper FET (FET_3T) are wired to provide a second inverter.

According to an embodiment of the present disclosure, a memory device includes a memory cell array including a plurality of planes; a charge pump configured to generate an operating voltage used for an operation on each of the plurality of planes according to a first clock signal having a first cycle; page buffers each configured to store pass data representing whether an operation of each of the plurality of planes has been completed; and an operation control circuit configured to, based on a number of the pass data received from the page buffers, control the charge pump to generate the operating voltage according to a second clock signal having a second cycle that is longer than the first cycle.

Embodiments of the disclosure provide a structure and method to ground a reference voltage generator based on a detected supply voltage. A circuit structure according to the disclosure includes a pass gate. The pass gate includes a pair of transistors each coupled to an input signal. One of the pair of transistors of the pass gate includes a gate coupled to a static reference voltage. An inverter couples an output from the pass gate to a device node. The inverter includes a drain terminal, a gate terminal, and a back-gate terminal coupled to ground.

The present disclosure provides a semiconductor structure comprising a substrate having a front side and a back side; an SRAM circuit having SRAM bit cells formed on a front side of the substrate, where each SRAM bit cell includes two inverters cross-coupled together, two write pass gates coupled to the two inverters, a read pull-down device coupled to the two inverters, and a read pass gate coupled to the read pull-down device, and wherein each SRAM bit cell is connected to the WBL, the WBLB, the RBL, the Vdd, and the Vss; a first subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the front side of the substrate to a first of the SRAM bit cells; a second subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the backside of the substrate to the first SRAM bit cell.

The present disclosure provides a memory device, which includes a memory array, a read-clock generation circuit, and a local input / output circuit. The read-clock generation circuit receives a sense amplifier enable signal, a first sense amplifier pre-charge signal, and a latched write enable signal to generate a first read enable signal. The local input / output circuit includes multiple pairs of column-address pass gates, and a pair of read pass gates. The plurality of pairs of column-address pass gates are configured to receive data from a bit-line pair of the memory cells in a row selected by an address signal. The pair of read pass gates connects a read bit-line pair to the bit-line pair in response to the first read enable signal being in a low-logic state. The first read enable signal is de-asserted after the read bit-line pair connected to the pair of read pass gates are pre-charged.

An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.

The invention relates to a memory cell including a dual anti-fuse device, a memory structure, and a method of operation. A memory cell is disclosed that includes a dual anti-fuse device between a first pass-gate transistor and a second pass-gate transistor. A dual antifuse device includes first and second antifuses having a common terminal and also each having an additional terminal opposite the common terminal. The first pass-gate transistor is connected between the first bit line and an additional terminal for the first pass-gate transistor. The second pass gate transistor is connected between the second bit line and an additional terminal of the second pass gate transistor. A common terminal of the first and second antifuses and gates of the first and second pass-gate transistors are connected to a word line. A memory structure including an array of such memory cells and related methods of operation are also disclosed. Within the array, different word line and bit line bias conditions may be employed to reliably perform program or read operations for selected antifuses in selected cells.

Semiconductor memory device comprising: an LWF leadership (234(j), 234(j+n), 334(j), 434(j), 534(j)); a LWB_bar line (336(j), 436(j), 536(j)) ; a GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)); a GWB bar line (322(j), 332(j), 432(j), 532(j)); a column (207(j), 207(j+n), 307(j), 407(j), 507A(j), 507B(j), 507C(j)) of segments (202A, 202B, 302A, 402A, 502A, 502A''), each segment (202A, 202B, 302A, 402A, 502A, 502A'') bit cells (212A(i,j), 212A(i+m,j+n), 212B(i,j), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(i,j), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)); wherein each of the bit cells (212A(i,j), 212A(i+m,j+n), 212B(ij), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(i,j), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)) comprises a latch circuit (311, 315) and a first and second pass gate (N03, N04; N09, N10) which connect the corresponding LWB and LWB_bar line (234(j), 234(j+n), 334(j), 434(j), 5340); 336(j), 436(j), 536(j)) to the latch circuit (311, 315); and a distributed write driver arrangement comprising a global write driver (224(j), 224(j+n)) and a local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)): where the global write driver (224(j), 224(j+n)) has: a first inverter (340, 440, 540) connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)) and the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)); and a second inverter (342, 442, 542) connected between the GWB_bar line (3220, 3320), 432(j), 532(j)) and the LWB_bar line (336(j), 436(j), 536(j)); and wherein the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is included in each segment (202A, 202B, 302A, 402A, 502A, 502A''), wherein each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is located in an interior of the corresponding segment (202A, 202B, 302A, 402A, 502A, 502A''), wherein each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) comprises: a third inverter (344, 444, 544) connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)) and the LWB line (234(j), 234(j+n), 334(j), 4340), 534(j); and a fourth inverter (346, 446, 546) connected between the GWB_bar line (322(j), 332(j), 432(j), 532(j)) and the LWB_bar line (336(j), 436(j), 536(j)).

1. Name of the Design Product: Quick Pass Gate (KMS-T5523). 2. Use of the Design Product: Used for entrances and exits to control the entry and exit of personnel. 3. Design Key Points of the Design Product: Lies in the shape. 4. Picture or Photograph that Best Illustrates the Design Key Points: Stereogram.

One or more examples relate to a complementary metal-oxide-semiconductor (CMOS) device. The CMOS device includes a CMOS pass gate circuit, a control circuit, and a bootstrap circuit. The CMOS pass gate circuit includes an n-channel transistor and a p-channel transistor. The control circuit may activate and deactivate the CMOS pass gate circuit. The bootstrap circuit may be electrically connected between the CMOS pass gate circuit and the control circuit. The bootstrap circuit may increase a first drive gain of the n-channel transistor and a second drive gain of the p-channel transistor.

The present invention provides an IGBT defect detection method and device based on the gate current signal of the turn-on process, including obtaining the current waveform of the target stage when the IGBT is actually working based on the gate current signal of the IGBT turn-on process; calculating the gate capacitance charging charge of the target stage when the IGBT is actually working according to the current waveform of the target stage when the IGBT is actually working; and analyzing and judging whether the current IGBT has a gate-emitter loop defect according to the gate capacitance charging charge of the target stage when the IGBT is actually working. The present invention analyzes the change of the gate charging charge through the gate current waveform of the IGBT turn-on process, and then judges whether the IGBT has a gate-emitter loop defect, thereby improving the detection efficiency. When there is a defect in the IGBT, the technical solution of the present invention can also be used to know the number of packaged chips with specific defects in the IGBT, and quantitative detection can be achieved.

One or more examples relate to a complementary metal-oxide-semiconductor (CMOS) device. The CMOS device includes a CMOS pass gate circuit, a control circuit, and a bootstrap circuit. The CMOS pass gate circuit includes an n-channel transistor and a p-channel transistor. The control circuit may activate and deactivate the CMOS pass gate circuit. The bootstrap circuit may be electrically connected between the CMOS pass gate circuit and the control circuit. The bootstrap circuit may increase a first drive gain of the n-channel transistor and a second drive gain of the p-channel transistor.

An IC device includes a first complementary field-effect transistor (CFET) static random-access memory (SRAM) cell in a semiconductor wafer, the first CFET SRAM cell including a first internal node and a first pass gate including a first source / drain (S / D) region and a second S / D region electrically connected to the first internal node, and a second CFET SRAM cell in the semiconductor wafer, the second CFET SRAM cell including a second internal node and a second pass gate including a third S / D region and a fourth S / D region electrically connected to the second internal node, wherein the first S / D region is aligned with the third S / D region in a direction perpendicular to a frontside of the semiconductor wafer and a backside of the semiconductor wafer

The quick pass gate with the anti-collision protection structure comprises a stand column, a blocking gate plate and a fixing device, a circular gate plate rotating shaft connecting groove is formed in the center of the stand column, a driving motor is fixed to the center of the bottom of the stand column, and a gate plate rotating shaft connecting piece is fixedly connected to the top of the driving motor; the center of the bottom of the stand column is fixedly connected with an anti-collision rotating shaft, the outer side face of the anti-collision rotating shaft is fixedly connected with a pair of limiting blocks, the bottom of the stand column is provided with a fixing device, the center of the interior of the fixing device is provided with a circular rotating groove, and the opposite angles of the fixing device are fixedly provided with protective electric push rods; according to the utility model, through rotation of the stand column and the fixing device, the stand column drives the blocking flashboard to rotate, so that opening and closing of the blocking flashboard are realized, and injury caused by extrusion of people flow is prevented.

An electronic fuse device includes a substrate, an insulating layer on the substrate, a first fuse gate, a first pass gate, and a first readout electrode. The substrate includes a first doping region, a second doping region, and a third doping region having a first conductivity type, and a highly doped region having a second conductivity type different from the first conductivity type. The first doping region is between the second doping region and the highly doped region. The second doping region is between the first doping region and the third doping region. The first fuse gate is on the insulating layer and between the first doping region and the second doping region. The first pass gate is on the insulating layer and between the second doping region and the third doping region. The first readout electrode is electrically connected to the third doping region.

A semiconductor memory device includes a plurality of conductive layers arranged in a vertical direction, a plurality of active layers connected to the plurality of conductive layers, a plurality of through gates each penetrating the plurality of active layers, and a plurality of through gate insulating layers respectively surrounding sidewalls of the plurality of through gates.

A chamber body includes a ceramic weldment. The ceramic weldment has an upper wall, a sidewall, a lower wall, and a lower wall rib segment. The sidewall is coupled to the upper wall by a sidewall-to-upper wall weld, the lower wall coupled to the sidewall by a sidewall-to-lower wall weld and defining a passthrough, and the lower wall rib segment is coupled to the lower wall plate by a lower wall rib segment weld. The upper wall has an upper wall plate portion and an upper wall rib portion through that define an upper wall unwelded ribbed region, overlay the passthrough, and which is formed using a singular ceramic workpiece using a subtractive manufacturing technique. Chamber arrangements, semiconductor processing systems, and methods of making ceramic weldments are also described.

This application relates to sensing line structures in capacitive sensing NAND memory. An array of memory cells can include: a data line; a source; a plurality of pass gates connected in series between the data line and the source; a plurality of cell column structures each having a respective plurality of series connected non-volatile memory cells connected in series with a respective plurality of series connected field effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series connected non-volatile memory cells and a channel of each field effect transistor of its respective plurality of series connected field effect transistors are selectively connected to one another; and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates.

A static random access memory structure includes a silicon substrate, a shallow trench isolation on the silicon substrate, a first fin structure connected to the silicon substrate and protruding the shallow trench isolation, a first gate structure spanning the first fin structure and a portion of the shallow trench isolation, and a second gate structure spanning the second fin structure and a portion of the shallow trench isolation. A static random access memory includes a first fin-shaped structure, a shallow trench isolation disposed on the first fin-shaped structure, a first gate structure covering a top surface and a portion of a sidewall of the first fin-shaped structure and forming a pass gate transistor (PG) of the static random access memory, and a protruding portion disposed right below the first gate structure and on the shallow trench isolation, the protruding portion covering a portion of a surface of at least one sidewall of the first fin-shaped structure, a top surface of the protruding portion is higher than a top surface of the shallow trench isolation.

An example apparatus includes: pass gate circuitry having a first terminal and a second terminal; process tracker circuitry having a first terminal and a second terminal, the first terminal of the process tracker circuitry coupled to the first terminal of the pass gate circuitry; and temperature compensation circuitry having a first terminal and a second terminal, the first terminal of the temperature compensation circuitry coupled to the second terminal of the process tracker circuitry, and the second terminal of the temperature compensation circuitry coupled to the second terminal of the pass gate circuitry.

A SRAM cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing along with stacked transistors to provide multiple transistors for implementation of inverters and pass gates in a memory cell. Various connection routes between components of the transistors (e.g., gates, sources, and drains) are made to allow cross-coupling between inverters in the memory cell.