85 results about "Pass gate" patented technology

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first trench in a substrate, disposing a first gate electrode in the first trench, and disposing a dummy gate electrode on the first gate electrode in the first trench. The method also includes removing the dummy gate electrode from the first gate electrode and forming a first doped region in the first gate electrode.

Embodiments of the disclosure provide a structure and method to ground a reference voltage generator based on a detected supply voltage. A circuit structure according to the disclosure includes a pass gate. The pass gate includes a pair of transistors each coupled to an input signal. One of the pair of transistors of the pass gate includes a gate coupled to a static reference voltage. An inverter couples an output from the pass gate to a device node. The inverter includes a drain terminal, a gate terminal, and a back-gate terminal coupled to ground.

The present disclosure provides a semiconductor structure comprising a substrate having a front side and a back side; an SRAM circuit having SRAM bit cells formed on a front side of the substrate, where each SRAM bit cell includes two inverters cross-coupled together, two write pass gates coupled to the two inverters, a read pull-down device coupled to the two inverters, and a read pass gate coupled to the read pull-down device, and wherein each SRAM bit cell is connected to the WBL, the WBLB, the RBL, the Vdd, and the Vss; a first subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the front side of the substrate to a first of the SRAM bit cells; a second subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the backside of the substrate to the first SRAM bit cell.

The present disclosure provides a memory device, which includes a memory array, a read-clock generation circuit, and a local input / output circuit. The read-clock generation circuit receives a sense amplifier enable signal, a first sense amplifier pre-charge signal, and a latched write enable signal to generate a first read enable signal. The local input / output circuit includes multiple pairs of column-address pass gates, and a pair of read pass gates. The plurality of pairs of column-address pass gates are configured to receive data from a bit-line pair of the memory cells in a row selected by an address signal. The pair of read pass gates connects a read bit-line pair to the bit-line pair in response to the first read enable signal being in a low-logic state. The first read enable signal is de-asserted after the read bit-line pair connected to the pair of read pass gates are pre-charged.

An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.

The invention relates to a memory cell including a dual anti-fuse device, a memory structure, and a method of operation. A memory cell is disclosed that includes a dual anti-fuse device between a first pass-gate transistor and a second pass-gate transistor. A dual antifuse device includes first and second antifuses having a common terminal and also each having an additional terminal opposite the common terminal. The first pass-gate transistor is connected between the first bit line and an additional terminal for the first pass-gate transistor. The second pass gate transistor is connected between the second bit line and an additional terminal of the second pass gate transistor. A common terminal of the first and second antifuses and gates of the first and second pass-gate transistors are connected to a word line. A memory structure including an array of such memory cells and related methods of operation are also disclosed. Within the array, different word line and bit line bias conditions may be employed to reliably perform program or read operations for selected antifuses in selected cells.

1. Name of the Design Product: Quick Pass Gate (KMS-T5523). 2. Use of the Design Product: Used for entrances and exits to control the entry and exit of personnel. 3. Design Key Points of the Design Product: Lies in the shape. 4. Picture or Photograph that Best Illustrates the Design Key Points: Stereogram.

One or more examples relate to a complementary metal-oxide-semiconductor (CMOS) device. The CMOS device includes a CMOS pass gate circuit, a control circuit, and a bootstrap circuit. The CMOS pass gate circuit includes an n-channel transistor and a p-channel transistor. The control circuit may activate and deactivate the CMOS pass gate circuit. The bootstrap circuit may be electrically connected between the CMOS pass gate circuit and the control circuit. The bootstrap circuit may increase a first drive gain of the n-channel transistor and a second drive gain of the p-channel transistor.

One or more examples relate to a complementary metal-oxide-semiconductor (CMOS) device. The CMOS device includes a CMOS pass gate circuit, a control circuit, and a bootstrap circuit. The CMOS pass gate circuit includes an n-channel transistor and a p-channel transistor. The control circuit may activate and deactivate the CMOS pass gate circuit. The bootstrap circuit may be electrically connected between the CMOS pass gate circuit and the control circuit. The bootstrap circuit may increase a first drive gain of the n-channel transistor and a second drive gain of the p-channel transistor.

An IC device includes a first complementary field-effect transistor (CFET) static random-access memory (SRAM) cell in a semiconductor wafer, the first CFET SRAM cell including a first internal node and a first pass gate including a first source / drain (S / D) region and a second S / D region electrically connected to the first internal node, and a second CFET SRAM cell in the semiconductor wafer, the second CFET SRAM cell including a second internal node and a second pass gate including a third S / D region and a fourth S / D region electrically connected to the second internal node, wherein the first S / D region is aligned with the third S / D region in a direction perpendicular to a frontside of the semiconductor wafer and a backside of the semiconductor wafer

An electronic fuse device includes a substrate, an insulating layer on the substrate, a first fuse gate, a first pass gate, and a first readout electrode. The substrate includes a first doping region, a second doping region, and a third doping region having a first conductivity type, and a highly doped region having a second conductivity type different from the first conductivity type. The first doping region is between the second doping region and the highly doped region. The second doping region is between the first doping region and the third doping region. The first fuse gate is on the insulating layer and between the first doping region and the second doping region. The first pass gate is on the insulating layer and between the second doping region and the third doping region. The first readout electrode is electrically connected to the third doping region.

A semiconductor memory device includes a plurality of conductive layers arranged in a vertical direction, a plurality of active layers connected to the plurality of conductive layers, a plurality of through gates each penetrating the plurality of active layers, and a plurality of through gate insulating layers respectively surrounding sidewalls of the plurality of through gates.

This application relates to sensing line structures in capacitive sensing NAND memory. An array of memory cells can include: a data line; a source; a plurality of pass gates connected in series between the data line and the source; a plurality of cell column structures each having a respective plurality of series connected non-volatile memory cells connected in series with a respective plurality of series connected field effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series connected non-volatile memory cells and a channel of each field effect transistor of its respective plurality of series connected field effect transistors are selectively connected to one another; and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates.

A static random access memory structure includes a silicon substrate, a shallow trench isolation on the silicon substrate, a first fin structure connected to the silicon substrate and protruding the shallow trench isolation, a first gate structure spanning the first fin structure and a portion of the shallow trench isolation, and a second gate structure spanning the second fin structure and a portion of the shallow trench isolation. A static random access memory includes a first fin-shaped structure, a shallow trench isolation disposed on the first fin-shaped structure, a first gate structure covering a top surface and a portion of a sidewall of the first fin-shaped structure and forming a pass gate transistor (PG) of the static random access memory, and a protruding portion disposed right below the first gate structure and on the shallow trench isolation, the protruding portion covering a portion of a surface of at least one sidewall of the first fin-shaped structure, a top surface of the protruding portion is higher than a top surface of the shallow trench isolation.

An example apparatus includes: pass gate circuitry having a first terminal and a second terminal; process tracker circuitry having a first terminal and a second terminal, the first terminal of the process tracker circuitry coupled to the first terminal of the pass gate circuitry; and temperature compensation circuitry having a first terminal and a second terminal, the first terminal of the temperature compensation circuitry coupled to the second terminal of the process tracker circuitry, and the second terminal of the temperature compensation circuitry coupled to the second terminal of the pass gate circuitry.

A SRAM cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing along with stacked transistors to provide multiple transistors for implementation of inverters and pass gates in a memory cell. Various connection routes between components of the transistors (e.g., gates, sources, and drains) are made to allow cross-coupling between inverters in the memory cell.

The invention relates to a self-timing memory circuit. A dummy SRAM cell included in a dummy row of a memory circuit including first and second data storage nodes connected by cross-coupled latch circuitry. The first pass gate transistor has a first source / drain node connected to the first data storage node, a second source / drain node connected to a ground node, and a gate node coupled to a dummy word line. The first data storage node is also connected to a ground node. The second pass gate transistor has a first source / drain node connected to the second data storage node, a second source / drain node connected to the first source / drain node, and a gate node coupled to the dummy word line. The read transistor and the pass transistor are coupled in series. A gate node of the pass transistor is coupled to the dummy read word line, and a source / drain node of the pass transistor is connected to a ground node.

A process for regulating power supply using a low-dropout regulator may include detecting voltage levels based on a predetermined first voltage level as high voltage and a second voltage level as medium voltage, wherein the high voltage is powered up followed by the medium voltage; a shifting bias mechanism when high voltage is detected during the initial power up of the high voltage rail, including turning on the overvoltage protection circuit, lowering actual bias voltage to counter back the required high bias voltage, and applying the actual bias voltage for a feedback system; performing the fix bias mechanism when medium voltage is detected, including turning off the overvoltage protection circuit and applying a fixed voltage reference to an actual pass gate of source follower for the feedback system enabling an instant startup together with the medium voltage when it powers up.

A layout pattern of a static random access memory includes a first region adjacent to a second region, a first SRAM cell located in the first region, the first region including a first diffusion region, a second SRAM cell located in the second region, the second region including a second diffusion region, a gate structure, and a second SRAM cell located in the second region. The gate structure spans the first diffusion region and forms a first pass gate transistor of the first SRAM cell, the gate structure spans the second diffusion region and forms a second pass gate transistor of the second SRAM cell, and the gate structure extends along a first direction; and the first diffusion region and the second diffusion region which are overlapped with the gate structure are not connected in the first direction.

A semiconductor device is provided. The semiconductor device includes a first pull-down transistor, a first pull-up transistor, a second pull-down transistor, a second pull-up transistor, a first pass gate transistor, a second pass gate transistor, a first bit line, a second bit line, a word line and a voltage supply line. The first pull-down transistor and the first pull-up transistor form a first inverter. The second pull-down transistor and the second pull-up transistor form a second inverter. An input of the first inverter is connected to an output of the second inverter through a first node butted contact. The first node butted contact includes a metal contact directly contacted a gate of the first pull-down transistor and the first pull-up transistor and directly contacted a source / drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

A semiconductor structure and a method for forming the same, the structure comprising: a first gate structure, a first channel layer and a first source / drain to form a pull-down transistor, the first gate structure, a second channel layer and a second source / drain to form a pull-up transistor; a gate plug on top of the first gate structure and electrically connected to the first gate structure; a dielectric layer on top of the substrate and covering the pull-down transistor, the pull-up transistor and the gate plug; a metal layer on top of the dielectric layer; a recess through the metal layer, the dielectric layer and a portion of the gate plug; a third channel layer covering the bottom and sidewalls of the recess; a second gate structure in the remaining space of the recess, the gate plug surrounding the second gate structure to serve as a third source / drain, the metal layer surrounding the second gate structure to serve as a fourth source / drain, the second gate structure, the third channel layer, the third source / drain and the fourth source / drain to form a pass gate transistor. The integration of the semiconductor structure is improved.

Advanced protection circuits for Q-factor sensing pads are disclosed. A wireless power system includes a bridge rectifier having first and second inputs coupled to first and second terminals of a coil and an output coupled to a rectified voltage node. An excitation circuit is coupled to the first input. A protection circuit has a first connection node capacitively coupled to the first terminal. The protection circuit clamps the first connection node when the first input is coupled to ground and connects the first connection node to the rectified voltage node when the first input is coupled to a supply voltage in a Q-factor measurement mode. The protection circuit functions as a pin of the rectifier in a wireless power mode. A pass gate circuit is between the first connection node and a sense node to which a sense circuit is connected to measure a Q-factor of the wireless power system when the protection circuit is in the Q-factor measurement mode.

A semiconductor memory device includes a plurality of conductive layers arranged in a vertical direction, a plurality of active layers connected to the plurality of conductive layers, a plurality of pass gates each penetrating the plurality of active layers, and a plurality pass gate insulating layers surrounding sidewalls of the plurality of pass gates, respectively.

1. Name of the Design Product: Express Gate (SG31). 2. Use of the Design Product: Used to control the passage of personnel while performing identity recognition. 3. Design Key Points of the Design Product: Lies in the shape. 4. Picture or Photograph that Best Illustrates the Design Key Points: Perspective view.

The application discloses a valve assembly and a press type straight-through gate valve thereof, and relates to the technical field of straight-through valves.The press type straight-through gate valve comprises an upper shell, a lower shell, a gate piece, a spring, an elastic body and a straight-through pipe.The lower shell is assembled and connected with the upper shell to form a cavity.The gate piece is provided with a circular hole.The spring is arranged on the lower shell.The elastic body is provided with a through hole at one end.The straight-through pipe is symmetrically arranged on the two sides of the lower shell, and the other end of the elastic body is inserted into one end of the straight-through pipe.The other end of the straight-through pipe penetrates through the cavity and is connected with an outer pipe.The gate piece is arranged in the middle of the two elastic bodies.A button is inserted into the cavity through a containing groove.The lower shell is provided with a guide groove.The middle part of the button is clamped with the middle part of the gate piece.In an initial state, the upper shell presses the button and the gate piece and compresses the spring.The circular hole and the through hole are distributed in a staggered manner.When the button is pressed and driven to move downward and the spring is compressed, the circular hole gradually coincides with the through hole.When the gate piece moves downward to the lowermost position, the circular hole completely coincides with the through hole.The device has a compact structure, a better use effect and is convenient for an operator to hold and use with one hand.

A process for regulating power supply using a low-dropout regulator may include detecting voltage levels based on a predetermined first voltage level as high voltage and a second voltage level as medium voltage, wherein the high voltage is powered up followed by the medium voltage; a shifting bias mechanism when high voltage is detected during the initial power up of the high voltage rail, including turning on the overvoltage protection circuit, lowering actual bias voltage to counter back the required high bias voltage, and applying the actual bias voltage for a feedback system; performing the fix bias mechanism when medium voltage is detected, including turning off the overvoltage protection circuit and applying a fixed voltage reference to an actual pass gate of source follower for the feedback system enabling an instant startup together with the medium voltage when it powers up.