44 results about "Pass gate" patented technology

The present disclosure provides a semiconductor structure comprising a substrate having a front side and a back side; an SRAM circuit having SRAM bit cells formed on a front side of the substrate, where each SRAM bit cell includes two inverters cross-coupled together, two write pass gates coupled to the two inverters, a read pull-down device coupled to the two inverters, and a read pass gate coupled to the read pull-down device, and wherein each SRAM bit cell is connected to the WBL, the WBLB, the RBL, the Vdd, and the Vss; a first subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the front side of the substrate to a first of the SRAM bit cells; a second subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the backside of the substrate to the first SRAM bit cell.

The invention relates to a memory cell including a dual anti-fuse device, a memory structure, and a method of operation. A memory cell is disclosed that includes a dual anti-fuse device between a first pass-gate transistor and a second pass-gate transistor. A dual antifuse device includes first and second antifuses having a common terminal and also each having an additional terminal opposite the common terminal. The first pass-gate transistor is connected between the first bit line and an additional terminal for the first pass-gate transistor. The second pass gate transistor is connected between the second bit line and an additional terminal of the second pass gate transistor. A common terminal of the first and second antifuses and gates of the first and second pass-gate transistors are connected to a word line. A memory structure including an array of such memory cells and related methods of operation are also disclosed. Within the array, different word line and bit line bias conditions may be employed to reliably perform program or read operations for selected antifuses in selected cells.

An IC device includes a first complementary field-effect transistor (CFET) static random-access memory (SRAM) cell in a semiconductor wafer, the first CFET SRAM cell including a first internal node and a first pass gate including a first source / drain (S / D) region and a second S / D region electrically connected to the first internal node, and a second CFET SRAM cell in the semiconductor wafer, the second CFET SRAM cell including a second internal node and a second pass gate including a third S / D region and a fourth S / D region electrically connected to the second internal node, wherein the first S / D region is aligned with the third S / D region in a direction perpendicular to a frontside of the semiconductor wafer and a backside of the semiconductor wafer

An electronic fuse device includes a substrate, an insulating layer on the substrate, a first fuse gate, a first pass gate, and a first readout electrode. The substrate includes a first doping region, a second doping region, and a third doping region having a first conductivity type, and a highly doped region having a second conductivity type different from the first conductivity type. The first doping region is between the second doping region and the highly doped region. The second doping region is between the first doping region and the third doping region. The first fuse gate is on the insulating layer and between the first doping region and the second doping region. The first pass gate is on the insulating layer and between the second doping region and the third doping region. The first readout electrode is electrically connected to the third doping region.

A semiconductor memory device includes a plurality of conductive layers arranged in a vertical direction, a plurality of active layers connected to the plurality of conductive layers, a plurality of through gates each penetrating the plurality of active layers, and a plurality of through gate insulating layers respectively surrounding sidewalls of the plurality of through gates.

This application relates to sensing line structures in capacitive sensing NAND memory. An array of memory cells can include: a data line; a source; a plurality of pass gates connected in series between the data line and the source; a plurality of cell column structures each having a respective plurality of series connected non-volatile memory cells connected in series with a respective plurality of series connected field effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series connected non-volatile memory cells and a channel of each field effect transistor of its respective plurality of series connected field effect transistors are selectively connected to one another; and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates.

A static random access memory structure includes a silicon substrate, a shallow trench isolation on the silicon substrate, a first fin structure connected to the silicon substrate and protruding the shallow trench isolation, a first gate structure spanning the first fin structure and a portion of the shallow trench isolation, and a second gate structure spanning the second fin structure and a portion of the shallow trench isolation. A static random access memory includes a first fin-shaped structure, a shallow trench isolation disposed on the first fin-shaped structure, a first gate structure covering a top surface and a portion of a sidewall of the first fin-shaped structure and forming a pass gate transistor (PG) of the static random access memory, and a protruding portion disposed right below the first gate structure and on the shallow trench isolation, the protruding portion covering a portion of a surface of at least one sidewall of the first fin-shaped structure, a top surface of the protruding portion is higher than a top surface of the shallow trench isolation.

A SRAM cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing along with stacked transistors to provide multiple transistors for implementation of inverters and pass gates in a memory cell. Various connection routes between components of the transistors (e.g., gates, sources, and drains) are made to allow cross-coupling between inverters in the memory cell.

The invention relates to a self-timing memory circuit. A dummy SRAM cell included in a dummy row of a memory circuit including first and second data storage nodes connected by cross-coupled latch circuitry. The first pass gate transistor has a first source / drain node connected to the first data storage node, a second source / drain node connected to a ground node, and a gate node coupled to a dummy word line. The first data storage node is also connected to a ground node. The second pass gate transistor has a first source / drain node connected to the second data storage node, a second source / drain node connected to the first source / drain node, and a gate node coupled to the dummy word line. The read transistor and the pass transistor are coupled in series. A gate node of the pass transistor is coupled to the dummy read word line, and a source / drain node of the pass transistor is connected to a ground node.

A layout pattern of a static random access memory includes a first region adjacent to a second region, a first SRAM cell located in the first region, the first region including a first diffusion region, a second SRAM cell located in the second region, the second region including a second diffusion region, a gate structure, and a second SRAM cell located in the second region. The gate structure spans the first diffusion region and forms a first pass gate transistor of the first SRAM cell, the gate structure spans the second diffusion region and forms a second pass gate transistor of the second SRAM cell, and the gate structure extends along a first direction; and the first diffusion region and the second diffusion region which are overlapped with the gate structure are not connected in the first direction.

A semiconductor device is provided. The semiconductor device includes a first pull-down transistor, a first pull-up transistor, a second pull-down transistor, a second pull-up transistor, a first pass gate transistor, a second pass gate transistor, a first bit line, a second bit line, a word line and a voltage supply line. The first pull-down transistor and the first pull-up transistor form a first inverter. The second pull-down transistor and the second pull-up transistor form a second inverter. An input of the first inverter is connected to an output of the second inverter through a first node butted contact. The first node butted contact includes a metal contact directly contacted a gate of the first pull-down transistor and the first pull-up transistor and directly contacted a source / drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

Advanced protection circuits for Q-factor sensing pads are disclosed. A wireless power system includes a bridge rectifier having first and second inputs coupled to first and second terminals of a coil and an output coupled to a rectified voltage node. An excitation circuit is coupled to the first input. A protection circuit has a first connection node capacitively coupled to the first terminal. The protection circuit clamps the first connection node when the first input is coupled to ground and connects the first connection node to the rectified voltage node when the first input is coupled to a supply voltage in a Q-factor measurement mode. The protection circuit functions as a pin of the rectifier in a wireless power mode. A pass gate circuit is between the first connection node and a sense node to which a sense circuit is connected to measure a Q-factor of the wireless power system when the protection circuit is in the Q-factor measurement mode.

A semiconductor memory device includes a plurality of conductive layers arranged in a vertical direction, a plurality of active layers connected to the plurality of conductive layers, a plurality of pass gates each penetrating the plurality of active layers, and a plurality pass gate insulating layers surrounding sidewalls of the plurality of pass gates, respectively.

A process for regulating power supply using a low-dropout regulator may include detecting voltage levels based on a predetermined first voltage level as high voltage and a second voltage level as medium voltage, wherein the high voltage is powered up followed by the medium voltage; a shifting bias mechanism when high voltage is detected during the initial power up of the high voltage rail, including turning on the overvoltage protection circuit, lowering actual bias voltage to counter back the required high bias voltage, and applying the actual bias voltage for a feedback system; performing the fix bias mechanism when medium voltage is detected, including turning off the overvoltage protection circuit and applying a fixed voltage reference to an actual pass gate of source follower for the feedback system enabling an instant startup together with the medium voltage when it powers up.

A sensing circuit and a control method of the sensing circuit are provided. The sensing circuit includes a data line, a complementary data line, a read bit line, a complementary read bit line, a read pass gate circuit and logic circuit. The logic circuit enables the read pass gate circuit when a voltage level on the read bit line and a voltage level on the complementary read bit line are pre-charged to a first voltage level, and disable the read pass gate circuit when one of the voltage level on the read bit line and the voltage level on the complementary read bit line is pull to a second voltage level different from the first voltage level. The read pass gate circuit is enabled to connect the data line to the read bit line and connect the complementary data line to the complementary read bit line.

The utility model discloses a kind of video anti-tailing fast pass gate machines, including two gate machine bodies, the adjacent side of two The rear gate and front gate of gate machine body are rotatably connected, the upper end of the gate machine body located in right side is fixedly connected with second camera, the front side of two The fixed block is fixedly connected with in gate machine body, the lower end of The fixed block located in right side is fixedly connected with motor mounting box, servo motor is installed in the motor mounting box, the output shaft end of servo motor penetrates fixed block and is fixedly connected with first camera. Through setting double camera dynamic monitoring, pressure sensor real-time response, adjustable pneumatic rod gate and other innovative structures, the accurate identification of personnel passing state, the effective interception of trailing behavior and the safety protection of passing process are realized, so as to solve many pain points of traditional gate machine body in nuclear power plant application, provide more reliable technical support for nuclear facility personnel access management.

This semiconductor device comprises: a first inverter comprising a first transistor and a second transistor; a second inverter comprising a third transistor and a fourth transistor and cross-connected to the first inverter; a first intermediate transistor and a second intermediate transistor; and a second pass gate transistor and a first pass gate transistor having a conductivity type opposite to that of the intermediate transistors. Respective gate electrodes of the intermediate transistors and respective gate electrodes of the pass gate transistors have respectively common word lines.

An IC device comprises CFETs configured as SRAM. The first CFET includes pull-down and pull-up transistors on a first and second level along a first direction. The second and third CFETs include pass gates on the first level and are aligned perpendicular to the first direction with the first pull-down transistor in a second and third direction, respectively. A fourth CFET includes second pull-down and pull-up transistors on the first and second levels and are aligned with the pass gates in the second and third directions. The first and second bit lines run along a third level in the third direction and are electrically connected to the S / D structures of the pass gates. A reference voltage line runs between the bit lines on the third level and is electrically connected to the S / D structure of a pull-down transistor.

A Content-Addressable Memory (CAM) cell has a latch of cross-coupled inverters and transmission gates to bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing. A node in the latch is applied to a gate of a data transistor in series with a select transistor to discharge a match line when select and latch data mismatch. Second data and select transistors receive inverse data from the latch for a CAM but receive data from a second cell latch for a Ternary Content-Addressable Memory (TCAM) cell with two latches per pair of select lines. When mismatches occur, even cells discharge the match line using n-channel data and select transistors while odd cells charge a complement match line using p-channel data and select transistors. The total number of p-channel and n-channel transistors in the cell can be equal when using complementary match lines.

A semiconductor device including a substrate including an active area and an isolation structure surrounding the active area, an active gate structure disposed in the active area, a passing gate structure disposed in the isolation structure, and a storage node disposed between the passing gate structure and the active gate structure. The isolation structure is a bi-layer structure, and an average dielectric constant of the isolation structure is less than 3.9. A method of forming a semiconductor device is also disclosed.

This application relates to memory array structures for capacitive sensing NAND memory. An array of memory cells includes a plurality of sense lines, each sense line having a respective plurality of pass gates connected in series between a second data line and a source, and having a respective subset of cell column structures coupled to a first channel of its respective plurality of pass gates, wherein for each sense line of the plurality of sense lines, each cell column structure of its respective subset of cell column structures is connected to a respective first data line of a respective subset of first data lines.

The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; a SRAM circuit having SRAM bit cells formed on the frontside of the substrate, wherein each of the SRAM bit cells includes two inverters cross-coupled together, two write pass gates coupled to the two inverters, a read pull-down device coupled to the two inverters, and a read pass gate coupled to the read pull-down device, and wherein each of the SRAM bit cells is connected to a WBL, a WBLB, a RBL, a Vdd and a Vss; a first subset of WBL, WBLB, RBL, Vdd and Vss is connected to a first SRAM bit cell of the SRAM bit cells from the frontside of the substrate; and a second subset of WBL, WBLB, RBL, Vdd and Vss is connected to the first SRAM bit cell from the backside of the substrate.

The embodiment of the invention provides a memory circuit, a memory device and a manufacturing method thereof. The memory circuit includes a first array including first memory cells, a second array alongside the first array in a first direction and including second memory cells, a first input / output circuit opposite the second array in the first direction, a second input / output circuit opposite the second array in the second direction, and a bit line connected to the first input / output circuit and the second input / output circuit. The second input / output circuit is opposite to the second array along the first direction with respect to the first array, and the bit line is coupled to the first input / output circuit, the first pass gate transistor of the first memory cell, and the second pass gate transistor of the second memory cell. A first of the first memory cells has a gate of a first length extending in a second direction perpendicular to the first direction, a first of the second memory cells has a gate of a second length extending in the second direction, the first length being shorter than the second length.

The present disclosure provides a semiconductor device including an SRAM cell which is implemented with eight transistors capable of improving read and write performance without increasing the area as compared to an SRAM cell which is implemented with six transistors. Each memory cell includes a first inverter, a second inverter, a first pass gate transistor, and a second pass gate transistor. In addition, each memory cell includes a first additional transistor that is connected between the first pass gate transistor and the second inverter, and a second additional transistor that is connected between the second pass gate transistor and the first inverter.

The utility model relates to access control equipment technical field discloses an adjustable interval's wisdom park pass gate, including bottom plate, the bottom plate top is provided with four gate main parts, four the gate main part top front and back both sides are all fixedly connected with inductor, four the gate main part top all rotatoryly connected with display screen, four the display screen front side all are fixedly connected with camera, four the gate main part inner top wall all are fixedly connected with spherical joint, four the spherical joint bottom all are fixedly connected with intercepting rod. In the utility model, the adjustment of interval is realized through air cylinder and telescopic link, when air cylinder retracts and drives telescopic link to stretch, pushes out extension piece and reduces gate interval, limits one person one gate pass, when air cylinder pushes out and makes telescopic link retract, extension piece is received in storage groove, expands interval and facilitates pedestrian to pass through fast, solved when the problem of time -consuming and labor -intensive of manual adjustment when the interval adjustment of gate.

Integrated circuit memory devices, resistive memory devices, and methods of operating the same are disclosed. The resistive memory device includes an array of resistive memory cells, a row decoder and a column decoder, a control circuit, and a write / read circuit coupled to the column decoder and the control circuit. The first resistive memory cell includes: a variable resistor element having a first terminal coupled to a first source line; and a first select transistor and a second select transistor configured in combination as a CMOS pass gate having a first current-carrying terminal coupled to the first bit line, a second current-carrying terminal coupled to the second terminal of the variable resistor element, and a gate terminal coupled to the first word line. A first write driver within the write / read circuit is configured to selectively perform a set write operation and a reset write operation on the variable resistor element.

The invention provides a layout pattern of static random access memory (SRAM) cell, which at least comprises an SRAM cell in a region, wherein the SRAM cell comprises a plurality of fin structures on a substrate, wherein a plurality of gate structures span the plurality of fin structures so as to form a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first pass gate transistor PG1A, a second pass gate transistor PG1B, a third pass gate transistor PG2A and a pass gate transistor PG2B are located on the substrate, wherein the first pull-up transistor PU1 and the second pull-up transistor PU2 are aligned with each other in a Y direction when viewed from a top view.

The present disclosure relates generally to imaging circuitry, comprising: a first semiconductor layer comprising: a photodiode; a global shutter memory node for a global shutter mode; and a first pass gate coupled between the photodiode and the global shutter memory node; and a second pass gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer comprising the pixel amplifier; and a third semiconductor layer comprising analog-to-digital conversion circuitry.

A static random-access memory (SRAM) device a read-port coupled to a voltage-to-time (VTC) conversion block. The read-port comprises a first transistor coupled to a pair of cross-coupled inverters. A pass gate transistor is coupled to the first transistor. A current-source transistor is coupled to the pass gate transistor. A row of the SRAM device is configured to generate a read wordline signal multiplied by one or more SRAM stored weights in response to receiving a voltage vector. The row is further configured to generate analog outputs for a multiply and compute operation (MAC).

A static random access memory (SRAM) cell of the present disclosure includes a first pull-down device, a second pull-down device, a first pass gate device, and a second pass gate device disposed in a first p-well on a substrate; a third pull-down device, a fourth pull-down device, a third pass gate device, and a fourth pass gate device disposed in a second p-well on the substrate; a first pull-up device and a second pull-up device disposed in an n-well disposed between the first p-well and the second p-well; and a first landing pad between the second pull-down device and the first pull-up device. The first landing pad is electrically coupled to a gate structure of the second pass gate device by way of a first gate via.