17 results about "Fin width" patented technology

The invention provides a trench gate silicon carbide MOSFET device integrated with a FinFET structure and a manufacturing method. The device structurally comprises an N + substrate, an N-epitaxial layer, an N + buffer layer, a P-type well region, a carrier expansion layer (CSL layer), an N + source region, a P + shielding region, a polycrystalline silicon gate, a source trench, source metal and drain metal. According to the invention, the FinFET structure with the fin width less than 300nm is integrated into the gate trench of the trench gate silicon carbide MOSFET. The integrated FinFET increases the channel density of the device, meanwhile, the carrier distribution is more uniform due to the extremely narrow Fin-shaped table top, the influence of interface scattering on the carriers is weakened, and the channel mobility is increased. Therefore, after the FinFET structure is integrated, the specific on-resistance of the trench gate silicon carbide MOSFET is obviously reduced. Meanwhile, the device is provided with a source trench which is deep and is wrapped by a P + shielding region, and the P + shielding region prevents the oxide layer at the corner of the trench from being broken down in advance.

Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.

Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. One or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). After fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. A liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.

A vertical fin-based field effect transistor (FinFET) device includes an array of FinFETs comprising a plurality of rows and columns of fins, each of the fins having a fin length and a fin width measured laterally with respect to the fin length and including a first fin tip disposed at a first end of the fin; a second fin tip disposed at a second end of the fin opposing the first end; a bridging structure connecting the first fin tip to an adjacent fin; a central region disposed between the first fin tip and the second fin tip and characterized by an electrical conductivity; and a source contact electrically coupled to the central region. The FinFET device also includes a gate region surrounding the fins.

Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.

FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

Procedures, encompassing the following: Obtaining a structure (100) which includes the following: a substrate (102) comprising a first well region (104A) with a first doping type and a second well region (104B) with a second doping type, which is opposite to the first doping type; and fins (106) which protrude from the substrate (102); Forming a structured etch mask (202, 204) on the structure (100), wherein the structured etch mask (202, 204) provides an opening (206) which is directly above a first fin (106b) of the fins (106), wherein the first fin (106b) is directly above the first trough area (104A); Etching of the structure (100) through the structured etching mask (202, 204), wherein the etching removes the first fin (106b) and forms a depression (302) in the substrate (102) which extends from the first depression area (104A) to the second depression area (104B); and Forming a dielectric material (402) between remaining sections of the fins (106) and within the depression (302), wherein a second fin (106c) of the fins (106) is immediately above the second depression area (104B) and is closest to the first fin (106b) along a fin width direction, and the opening (206) is immediately above a first section of the second depression area (104B) between the first fin (106b) and the second fin (106b), and a width of the first section is less than a width of the second depression area (104B) between the first fin (106b) and the second fin (106c) along the fin width direction.

The embodiment of the invention provides a comprehensive evaluation index determination method and device, a storage medium and electronic equipment, and the method comprises the steps: sampling fin parameters of a cold plate fin to obtain s groups of first sample points, the fin parameters comprise the fin length, the fin width and the fin spacing, and the s groups of first sample points comprise the fin length, the fin width and the fin spacing; the s groups of first sample points are used for indicating numerical value combinations of various fin parameters, and s is a positive integer; performing a fitting test on the cold plate fin according to the s groups of first sample points, and determining a harmonic parameter of a comprehensive evaluation index of the cold plate fin according to an obtained fitting test result, the comprehensive evaluation index being used for performing comprehensive evaluation on thermal performance and hydraulic performance of the cold plate fin, the harmonic parameters are used for indicating the importance degree of the dimensionless temperature gradient and the flow resistance loss of the cold plate fin, the dimensionless temperature gradient is used for evaluating the thermal performance of the cold plate fin, and the flow resistance loss is used for evaluating the hydraulic performance of the cold plate fin; and determining comprehensive evaluation indexes of the cold plate fins according to the harmonic parameters.

A vertical, FinFET device includes an array of FinFETs comprising a plurality of rows and columns of fins. Each of the fins has a fin length and a fin width, a first fin tip, a second fin tip, and a central region disposed between the first fin tip of a first row of the plurality of rows and the second fin tip of a second row of the plurality of rows. The central region is characterized by an electrical conductivity. The FinFET device also includes a neutralized region including the first fin tip, a region between the first row of the plurality of rows and the second row of the plurality of rows, and the second fin tip. The neutralized region is characterized by a second electrical conductivity less than the electrical conductivity of the central region. The FinFET device further includes an electrical conductor disposed over the neutralized region.

A microcooler device and formation thereof. The microcooler device includes: a first set of fins having a first fin width; a second set of fins having a second fin width, wherein the first set of fins alternate between the second set of fins; and a set of channels located between the first set of fins and the second set of fins.

Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.

A vertical, FinFET device includes an array of FinFETs comprising a plurality of rows and columns of fins. Each of the fins has a fin length and a fin width, a first fin tip, a second fin tip, and a central region disposed between the first fin tip of a first row of the plurality of rows and the second fin tip of a second row of the plurality of rows. The central region is characterized by an electrical conductivity. The FinFET device also includes a neutralized region including the first fin tip, a region between the first row of the plurality of rows and the second row of the plurality of rows, and the second fin tip. The neutralized region is characterized by a second electrical conductivity less than the electrical conductivity of the central region. The FinFET device further includes an electrical conductor disposed over the neutralized region.

The present disclosure relates to fin thinning controlled by feedback. A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is located between the isolation regions. The method also includes recessing the isolation regions so that the top of the semiconductor strip protrudes above the top surface of the isolation region to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etching scheme based on the fin width, and performing a thinning process on the semiconductor fin using the etching scheme.

The invention provides a lead frame and a chip packaging structure. The lead frame comprises a frame unit with a pin array pair; the middle ribs are arranged between the adjacent frame units and comprise at least one middle rib entity, the middle rib entity is used for connecting the pin arrays of the two adjacent frame units, and the entity cutting width of the middle rib entity in the width direction of the middle rib or the sum of the entity cutting widths is smaller than or equal to half of the width of the middle rib. The chip packaging structure comprises a lead frame. By designing the medium rib entity in the medium rib area and limiting the sum of the entity cutting width or the total cutting width of the medium rib entity in the width direction of the medium rib not to exceed half of the width of the medium rib, when the frame unit is cut along the medium rib, the total amount of metal entities in the cutting channel area, especially the cutting channel area at the pin position can be effectively reduced. And the copper stacking phenomenon caused by copper layer stacking in the cutting process can be relieved, so that the occurrence of burr abnormity is reduced, and the product yield is improved.

A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

A heat sink for cooling computing devices is disclosed. The heat sink includes a plurality of fin stages arranged in spaced relation between an intake side and an exhaust side. The plurality of fin stages each include a plurality of fins extending along a flow direction. At least one of the plurality of fin stages is distinct in fin width and / or fin height from another one of the plurality of fin stages.