24925 results about "Protection layer" patented technology

A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A low-k material is then deposited to fill the gaps between metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A protective layer is deposited on top of the metal lines and the low-k material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photo-resist, and to clean the vias. The protective layer is then selectively etched away to make contact between a via plug and the metal lines.

A method for protecting a layer includes: providing a substrate having a target layer and forming a protective layer on the target layer, said protective layer contacting and covering the target layer and containing a hydrocarbon-based layer constituting at least an upper part of the protective layer, which hydrocarbon-based layer is formed by plasma-enhanced atomic layer deposition (PEALD) using an alkylaminosilane precursor and a noble gas without a reactant.

A stack type semiconductor package, and a method of fabricating the same are provided. The stack type semiconductor package may include a lower unit package and an upper unit package. The lower unit package may include a substrate, and a semiconductor chip on an upper surface of the substrate. A bump may be on an upper surface of the substrate, and a protecting layer, covering the semiconductor chip, may be formed. The protecting layer may include a via hole partially exposing the bump. The upper unit package may be on the protecting layer, and may include an internal connection solder ball on a lower surface of the upper unit package. The internal connection solder ball may be inserted into the via hole and connected to the bump.

The present invention provides a system for creating an application software environment without changing an operating system of a client computer, the system comprising an operating system abstraction and protection layer, wherein said abstraction and protection layer is interposed between a running software application and said operating system, whereby a virtual environment in which an application may run is provided and application level interactions are substantially removed. Preferably, any changes directly to the operating system are selectively made within the context of the running application and the abstraction and protection layer dynamically changes the virtual environment according to administrative settings. Additionally, in certain embodiments, the system continually monitors the use of shared system resources and acts as a service to apply and remove changes to system components. The present thus invention defines an “Operating System Guard.” These components cover the protection semantics required by .DLLs and other shared library code as well as system device drivers, fonts, registries and other configuration items, files, and environment variables.

There is provided a thin-film transistor including at least a substrate, a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, a drain electrode and a protective layer, wherein the oxide semiconductor layer is an amorphous oxide containing at least one of the elements In, Ga and Zn, the gate electrode-side carrier density of the oxide semiconductor layer is higher than the protective layer-side carrier density thereof, and the film thickness of the oxide semiconductor layer is 30 nm±15 nm.

A proximity sensor for controlling a component that may be installed on a window, on an interior or exterior pillar of a vehicle, on a control panel or any suitable location on a vehicle or any other structure. The sensor includes a substrate and a conductive layer disposed on the substrate. The conductive layer is formed from a conductive ink composition with the conductive layer defining at least one circuit for controlling the component when a user is in proximity to the conductive layer. A protective layer is disposed over the conductive layer. At least one of the conductive layer and the protective layer defines a graphic formed through the layer for visual identification to the user.

An electro-optic display comprises a backplane; a layer of electro-optic material disposed adjacent the backplane; a protective layer; and a sealing layer of a metal or a ceramic extending between the backplane and the protective layer, and thus sealing the layer of electro-optic material from the outside environment.

Transistors are fabricated by forming a protective layer having a first opening extending therethrough on a substrate, forming a dielectric layer on the protective layer having a second opening extending therethrough that is wider than the first opening, and forming a gate electrode in the first and second openings. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. Related devices and fabrication methods are also discussed.

An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Methods and devices are provided for improved environmental protection for photovoltaic devices and assemblies. In one embodiment, the device comprises of an individually encapsulated solar cell, wherein the encapsulated solar cell includes at least one protective layer coupled to at least one surface of the solar cell and the protective layer may be formed from a substantially inorganic material. The protective layer has a chemical composition that prevents moisture from entering the solar cell and wherein light passes through the protective layer to reach an absorber layer in the solar cell.

Provided is a bottom gate type thin film transistor including on a substrate (1) a gate electrode (2), a first insulating film (3) as a gate insulating film, an oxide semiconductor layer (4) as a channel layer, a second insulating film (5) as a protective layer, a source electrode (6), and a drain electrode (7), in which the oxide semiconductor layer (4) includes an oxide including at least one selected from the group consisting of In, Zn, and Sn, and the second insulating film (5) includes an amorphous oxide insulator formed so as to be in contact with the oxide semiconductor layer (4) and contains therein 3.8×10¹⁹ molecules/cm³ or more of a desorbed gas observed as oxygen by temperature programmed desorption mass spectrometry.

Various embodiments provide semiconductor devices including a package structure and methods of forming the semiconductor devices. In one embodiment, the package structure can include a through-hole at least partially filled by one or more layers of material(s) to form a through-hole interconnect between semiconductor devices in the package structure. The through-hole can be filled by an insulating layer, a diffusion barrier layer, a metal interconnect layer, and/or a protective layer having a total thickness from the sidewall of the through-hole of less than or equal to the radius of the through-hole.

A foundation layer increasing adhesive properties to a substrate, another foundation layer controlling orientation of an antiferromagnetic layer, the antiferromagnetic layer including a disordered alloy of IrMn, a pinning layer, and a cap protection layer are formed in the order on the substrate. The pinning layer includes two layers having an exchange coupling giving layer which exchange-couples to the antiferromagnetic layer and an exchange coupling enhancement layer which enhances the exchange coupling, the exchange coupling giving layer is made of a ferromagnetic material including Co or a Co100-XFeX alloy (O<=X<25) having face-centered cubic structure. The exchange coupling enhancement layer is made of Fe or a Co100-YFeY alloy (25<=Y<=100) having body-centered cubic structure.

The invention relates to an infrared detector with a micro-bridge structure, which belongs to the technical field of micro-electromechanics, and comprises a silicon substrate as a read-out circuit of the infrared detector; a metal reflecting layer deposited on the silicon substrate; a dielectric layer which is deposited in a groove of the metal reflecting layer and has the height being consistentwith that of the metal reflecting layer; a sacrifice layer and a first release protection layer used as protection of release of the sacrifice layer which are deposited on the dielectric layer and the metal reflecting layer and form through holes by lithography and etching; a copper or tungsten pier which is deposited in the through hole of the sacrifice layer; a metal electrode deposited on the copper or tungsten pier and the first release protection layer; and a sensitive material detecting layer which is deposited on the metal electrode and the first release protection layer. A Cu-column micro-bridge structure is manufactured by using the damascene process, and a flat micro-bridge plane is manufactured by introducing the chemical mechanical polishing process (CMP), thereby being conductive to the follow-up process and improving the performances.

This invention relates to preparation method gas phase siliconizing technique preparing high compact fiber reinforcement SiC group composite material. Protection layer interface is formed on fiber surface through gas phase or liquid phase, then they are dipped and cracked through nm SiC slime to make certain density precast body of fiber reinforcement SiC group. Carbon is added into the body through dipping and cracking way to form group body with certain pore, the group body penetrates inner part of the multi-hole body through gas phase silicon after it is high temperature treated, then it reacts with carbon and fills the pore to get compact basal body. The density of the material can reach 2.25-2.30g/cm3, open porosity is 3-6 percent; it is large more higher than traditional method of getting Cf/SiC material.

The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.

Transistors are fabricated by forming a protective layer having an opening extending therethrough on a substrate, and forming a gate electrode in the opening. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion. Related devices. and fabrication methods are also discussed.