392 results about "Integrated circuit manufacturing" patented technology

The invention discloses an integrated circuit equipment data optimization monitoring system and method based on big data, and relates to the technical field of integrated circuit manufacturing. The method is used for solving the problems of insufficient multi-physical field monitoring, difficulty in abnormal traceability and lack of closed-loop control in plasma etching. A plasma sheath thickness inversion model and an etching selection ratio model are constructed by collecting radio frequency reflection phase, mass spectrum ion strength and wafer temperature data, and process parameter-plasma state dynamic coupling is established. Interference image distortion features and electron microscope size data are fused, micro-groove geometric parameters are analyzed, morphology instability risk indexes are generated, and nanoscale early warning is achieved. And designing a dual-channel fusion network, embedding a physical constraint attention mechanism, and generating an etching rate optimization instruction. On the basis of incremental learning, model parameters are updated online, a'monitoring-decision-feedback 'closed-loop system is formed, anomaly detection sensitivity and decision reliability are improved, and technical support is provided for intelligence of integrated circuit equipment.

The invention belongs to the technical field of integrated circuit manufacturing, and relates to an etching device for a thick copper PCB. Comprising a shell, material holes are formed in the two sides of the shell, a liquid conveying pipe is arranged on the upper side of the shell, the liquid conveying pipe is communicated with liquid distribution pipes which are distributed at equal intervals, the liquid distribution pipes penetrate through the shell and are communicated with spraying pipes, the lower sides of the spraying pipes are communicated with spraying heads which are distributed at equal intervals, a gas conveying pipe is arranged on the upper side of the shell, and the gas conveying pipe is communicated with the spraying heads. The air conveying pipe is communicated with air distributing pipes distributed at equal intervals, the air distributing pipes penetrate through the shell and are communicated with air spraying pipes, and the air spraying pipes are used for guiding air flow in the air spraying pipes to flow downwards. According to the invention, the vertical downward air flow is applied by means of the air injection pipe, and downward acting force is applied to the PCB by means of blowing of the air flow, so that the stability of the PCB in the etching process is kept while a supporting roller on the upper side of the PCB is omitted, and the etching efficiency and the etching uniformity are improved.

The invention relates to the field of integrated circuit manufacturing, in particular to a light source mask collaborative optimization method and device, and the method comprises the steps: obtaining an initial light source and an initial mask pattern; the initial mask pattern is a binary image; determining the adjusted initial light source and the adjusted initial mask pattern corresponding to the minimum function value of the light source mask collaborative optimization loss function as an optimized light source and an optimized mask pattern; the light source mask collaborative optimization loss function comprises a main pattern edge error item and a sub-resolution auxiliary pattern printing item; obtaining a simulation photoetching image, and judging whether a sub-resolution auxiliary pattern is printed in the simulation photoetching image or not; when the printed sub-resolution auxiliary pattern exists, outputting the latest optimized mask pattern as a process iteration mask pattern; calculating a proportion value; and when the proportion value does not exceed the qualified upper limit value, outputting an optimized light source and process iteration mask pattern. The method can ensure that no sub-resolution auxiliary pattern is printed and a larger process window is reserved.

The invention discloses a method for controlling CMP (chemical mechanical polishing) dish-shaped pits, corrosion pits and interface corrosion of ruthenium barrier layer copper wiring, which is suitable for a manufacturing process of integrated circuits of 14 nanometers and below. According to the method, a specifically synthesized TTAK corrosion inhibitor is introduced into a polishing solution system, the oriented adsorption characteristic of the molecular structure of the TTAK corrosion inhibitor is utilized, the corrosion reaction of copper is selectively inhibited, meanwhile, the normal material removal efficiency of a ruthenium barrier layer and a TEOS dielectric layer is maintained, and cooperative regulation and control of the removal rate of the Cu / Ru / TEOS material are achieved. By means of the method, dished pits, corrosion pits and Fang type interface defects generated in the fine polishing and barrier layer polishing process can be effectively eliminated, and copper / ruthenium interface corrosion is improved. According to the method, the global planarization quality of the copper interconnection ruthenium barrier layer is remarkably improved, the interface bonding strength and the electrical reliability of an interconnection circuit are enhanced, and an effective solution is provided for performance optimization of an advanced process integrated circuit device.

The invention discloses a logic chip mask defect detection method, and relates to the technical field of integrated circuit manufacturing, and the method comprises the following steps: S1, constructing a scattering response model of sub-wavelength inorganic particles on the surface of a mask, and constructing a scattering response model of sub-wavelength inorganic particles on the surface of the mask under a set multi-angle polarized light incidence condition; non-linear disturbance influence of inorganic particles with different particle sizes on the reflected light phase in each incident polarization state is simulated, and a scattering response template containing standard phase disturbance characteristics is generated; and S2, based on a scattering response template, carrying out pixel-by-pixel matching analysis on the acquired multi-angle polarization phase diagram on the surface of the mask, identifying a local area matched with the template, and marking the local area as a suspected scattering interference area. According to the method, through construction of the scattering response template and multi-angle polarization consistency analysis, accurate distinguishing of artifacts and real defects is achieved, the recognition precision and stability under complex interference are improved in combination with structure retention type phase reconstruction and dynamic threshold recognition, and mask quality control and photoetching yield improvement are facilitated.

The invention relates to the technical field of integrated circuit manufacturing, in particular to a soaking device for a PCB. Comprising a box body, a feeding carrier roller set and a discharging carrier roller set are installed on the box body, a soaking pool, a liquid storage pool and a power pool are arranged in the middle of the box body, a power carrier roller set is obliquely arranged in the soaking pool, a motor is installed in the box body, a rotating roller is rotationally connected in the power pool, and a motor is installed in the rotating roller. An output shaft of the motor penetrates through the power pool and is fixedly connected with the rotating roller, and the rotating roller is slidably connected with moving strips which are evenly distributed in the circumferential direction. According to the PCB soaking device, the PCB is driven to move through the power carrier roller set in the soaking pool, the liquid medicine is driven to flow through the rotating rollers and the moving strips, the liquid medicine penetrates through or bypasses the PCB to circularly flow, the problem of poor cohesion between different processes in the PCB production process is solved, and the treatment efficiency of the PCB soaking process is improved through the structural design.

The invention discloses a high-efficiency intelligent card wire end burying positioning and distance adjusting device, and relates to the technical field of integrated circuit manufacturing. The high-efficiency intelligent card wire end burying positioning and distance adjusting device comprises a fixed winding unit, a guide adjusting unit, a conveying unit and a wire burying unit; a guide adjusting unit is fixedly installed on the fixed winding unit, a conveying unit is fixedly installed on the guide adjusting unit, and the conveying unit is connected with the fixed winding unit. According to the invention, through the flow cooperation of the fixed winding unit, the conveying assembly and the adjusting assembly, the precise conveying of the copper wire to the wire embedding assembly and the wire embedding operation of the intelligent card are realized, and during the spacing adjustment, by means of the cooperative driving of the guide assembly and the adjusting assembly, the multi-unit linkage distance adjustment of the wire embedding assembly can be realized, and the single wire embedding assembly can be finely adjusted independently; and meanwhile, the control modes of manual reference setting of thread end burying and other electric adjustment, touch screen one-key distance adjustment and single-head fine adjustment are matched.

The invention relates to the technical field of circuit board analysis, in particular to an integrated circuit defect analysis method and system, and the method comprises the steps: extracting and screening E-test data of a target product from a big data platform for integrated circuit manufacturing; performing defect classification modeling processing on the screened E-test test data; calculating a defect correlation index according to the classification accuracy and the correlation metric value of each candidate E-test item; determining a defect judgment threshold value and a numerical value distribution direction related to the defect based on a logic regression classifier result of the key test item, and generating a binary defect distribution diagram corresponding to each jointed board; calculating the image similarity between the bad jointed board graph and each good jointed board graph; judging whether the image similarity is higher than a preset threshold value or not, and adding the jointed boards of the good jointed board graph into a virtual bad jointed board list; and based on the virtual bad jointed board list, analyzing and comparing the manufacturing process flow data of the virtual bad jointed board and the original defective jointed board, and determining the potential root cause causing the defect. According to the method, the problems that in the E-test scene of the circuit board, the number of defect samples is extremely small, categories are extremely unbalanced, an experience threshold value is difficult to set, and root causes are difficult to trace can be solved.

The invention relates to the field of integrated circuit manufacturing, and particularly discloses a semiconductor photoelectric horizontal sensor and a preparation method and application thereof, the sensor is a sheet-shaped body, and the sensor comprises a substrate which comprises a plurality of photoelectric sensing diodes which are uniformly distributed on a circular ring with a first circle center axis perpendicular to the substrate as an axial symmetry axis; the annular cavity is positioned on the substrate and vertically corresponds to a circular ring formed by the plurality of photoelectric sensing diodes, and a rollable microgravity ball is arranged in the annular cavity; and the first signal light introduction part is located on the annular cavity, is annular, vertically corresponds to the annular cavity and is used for vertically introducing the annular signal light which is actively irradiated into the annular cavity. According to the invention, the rollable microgravity ball can freely roll at the lowest point of the annular cavity under the action of gravity, meanwhile, the actively irradiated annular signal light is vertically guided into the annular cavity, and the accurate angular position of the rollable microgravity ball is accurately sensed by the plurality of photoelectric sensing diodes.

The invention discloses a wafer defect atlas intelligent identification and classification method and system, and relates to the technical field of semiconductor integrated circuit manufacturing and detection, and the method comprises the steps: obtaining a detection point set, an original image and standard reference attribute data; constructing a space weight matrix based on reference data; calculating a generalized connection cost based on a path weighted cumulative value, constructing an initial graph model, and performing probability sparsification; determining verification points based on the weight matrix and extracting local gradient features of the original image; correcting the connection probability by using a Bayesian inference model, and updating a graph topological structure; and finally, outputting a classification result according to the connected sub-graph features. According to the method, layout physical attributes and image microscopic features are combined, and accurate reconstruction and classification of defect forms under a complex background are realized.

The invention provides an electric wiring component, a consumable chip and an ink box, and relates to the technical field of integrated circuit manufacturing and integrated circuit design. The electrical wiring member includes a plurality of contact points for contacting a contact pin of the image forming apparatus; the plurality of contact points comprise a plurality of corner contact points and a plurality of non-corner contact points; at least two corner contacts are suspended contacts, and the suspended contacts are in contact with the contact pins but are not electrically connected with the printing head chip; according to the invention, at least two corner contacts are suspended contacts, so that the number of corner contacts electrically connected with the imaging equipment is reduced, and the problems that the corner contacts cannot be normally and electrically connected with corresponding contact pins due to pollution, so that the contact between the consumable chip side and the terminal of the imaging equipment main body side is insufficient, and the service life of the imaging equipment is prolonged are solved. And the consumable chip and the imaging equipment cannot be in normal contact and electrical connection.

The invention discloses a film stripping and cleaning device for PCB production, and belongs to the technical field of integrated circuit manufacturing. Comprising a supporting frame, a roller conveying module is arranged on the supporting frame, two sets of spraying modules are arranged in the supporting frame, each spraying module comprises a liquid inlet pipe, the liquid inlet pipes are fixedly connected to the supporting frame in a penetrating mode, and the liquid inlet pipes and the supporting frame are jointly and rotationally connected with symmetrically-distributed spraying pipes. The spraying pipes are fixedly connected with connecting gears, rack frames which are symmetrically distributed are slidably connected into the supporting frame, the connecting gears are meshed with the corresponding rack frames, and a pushing assembly is arranged on the supporting frame. The connecting gears drive the corresponding rotating liquid pipes to swing in a reciprocating mode, the rotating liquid pipes swing in a reciprocating mode to drive the nozzle sets on the rotating liquid pipes to swing synchronously, then the cleaning positions of the nozzle sets on the circuit board are continuously changed, and therefore the cleaning uniformity of the multiple nozzle sets on the circuit board is improved.

The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a wafer wet etching method and a wafer produced thereby. The wafer comprises a substrate and a composite metal layer; the composite metal layer covers a preset surface of the substrate; the composite metal layer comprises a first metal layer and a second metal layer; and the first metal layer covers the surface of the second metal layer. By means of the wet etching process provided by the present invention, different masks are provided for different metal layers and the widths of transparent areas of the masks are controlled, so that the problem of dimensional distortion of a bottom metal layer when a conventional process is used for wet etching of a composite metal film is effectively solved, thereby improving the dimensional precision of the bottom layer during wet etching of the composite metal film, and also improving the yield rate and reliability of wafer production.

The invention relates to the field of integrated circuit manufacturing, in particular to a mask process correction method, device and equipment and a storage medium. Inputting the target mask pattern as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model; determining a mask layer bottom simulation pattern size and a mask layer top simulation pattern size corresponding to each edge section in the simulation electron beam exposure pattern to obtain a corresponding side wall included angle; according to the size of the simulation pattern at the bottom of the mask layer, determining a size-included angle comparison data set corresponding to each edge section to obtain an included angle offset; further determining a target size offset; and adjusting the position of a corresponding edge section in the simulation pattern at the bottom of the mask layer according to the target size offset. The similarity between a wafer pattern obtained by carrying out a photoetching process on the mask layer corrected by the method and a photoetching target pattern is greatly improved.

The invention discloses a grid system for a plasma etching system and the plasma etching system, and belongs to the field of integrated circuit manufacturing, the grid system comprises a grid mesh close to a discharge outlet side of a discharge chamber,..., an Nth middle grid mesh and a grid mesh close to a dry etching part side which are arranged in sequence, and each grid mesh comprises a substrate, a plurality of grid mesh holes are uniformly distributed in the substrate, a first film layer with low surface energy and low sputtering yield is arranged on the outer surface of the substrate, and a second film layer with low surface energy and low sputtering yield is arranged on the inner wall of each grid mesh hole; n is an integer greater than or equal to 0. The invention can delay the loss of the grid mesh and delay the adsorption pollution on the surface of the grid mesh.

The invention relates to the technical field of integrated circuit manufacturing, and provides wafer thinning equipment and a wafer thinning method. The wafer thinning equipment comprises a grinding device and an adsorption platform, the adsorption platform is used for bearing a wafer and driving the wafer to rotate, the grinding device is arranged above the adsorption platform in a lifting mode, and a grinding wheel used for grinding the wafer is arranged on the lower portion of the grinding device. The grinding wheel comprises a base material and a plurality of grinding blocks, and the grinding blocks are fixed to the base material through adhesive layers. The grinding block comprises spiral calcium carbonate containing a Si-O-Ca structure and is used for dispersing stress during grinding. According to the technical scheme, the problem that the flatness of the thinned wafer is poor in the prior art is solved.

The invention relates to a PINN-based negative development photoresist deformation parameter extraction method, belongs to the technical field of integrated circuit manufacturing, and solves the problem that deformation parameters of negative development photoresist are difficult to measure in the prior art. The negative developing photoresist deformation parameter extraction method comprises the following steps: determining center coordinate data of negative developing photoresist in a plurality of exposure areas before and after a photoetching process; inputting each piece of center coordinate data into a PINN model for training; in the PINN model, predicting according to each center coordinate to obtain a predicted thickness displacement corresponding to each center coordinate and a predicted deformation parameter of the negative developing photoresist; judging whether a loss function value of the PINN model reaches a loss threshold value or not; and if so, stopping training the PINN model, and outputting a predicted deformation parameter of the negative developing photoresist by the PINN model as a final deformation parameter of the negative developing photoresist. Therefore, the deformation parameters of the negative developing photoresist are extracted.

Using “in-situ on-die time-domain reflectometry (TDR)” with data signal paths of integrated circuits, printed circuit boards, and data processing equipment and systems allows testing, verification and troubleshooting of data channel signal path impedance variations including the package, escape routing, socket, board, and cable / connectors provides fast characterization thereof. Operation of “in-situ on-die TDR” uses existing analog-to-digital converter (ADC) and data transmitter (TX) drivers of an integrated circuit to act as a TDR sampling head by performing a user interface-based TDR sampling with a step-waveform generated by an integrated circuit TX driver. Then sampling the step-waveform with the ADC of the integrated circuit using spline interpolation to obtain the over-sampled waveform. Once the sampled step-waveform is obtained, the TDR profile of the sampled data channels may be calculated. Large amounts of impedance variation data may thus be collected during either integrated circuit manufacturer or customer-built data communications channel testing.

The invention relates to the field of computer vision and semiconductor manufacturing detection, in particular to a multi-scale feature fusion wafer defect detection method, which comprises the following steps of: acquiring a wafer image, and labeling particle defects existing in the image by using a manual labeling tool; the marked image is preprocessed; and constructing and training a defect intelligent identification model based on the convolutional neural network, and performing defect detection on the processed wafer image by using the model. The wafer particle defect intelligent detection method provided by the invention has remarkable advantages in the aspects of detection precision, recognition speed, defect classification, system stability, deployability and the like, can be widely applied to multiple fields of integrated circuit manufacturing, semiconductor packaging, silicon wafer detection and the like, and has good popularization and application prospects and industrial value.

The invention relates to the field of integrated circuit manufacturing, in particular to the technical field of manufacturing of semiconductor device special equipment such as a photoetching machine and an etching machine special for production, and provides a through hole filling electroplating method and system for a printed circuit board. The method comprises the following steps: carrying out laser micro-through-hole processing on the printed circuit board; carrying out glue removal treatment on the printed circuit board with the micro through hole; carrying out black hole treatment or direct electroplating treatment on the degummed printed circuit board; performing porefilling electroplating on the treated printed circuit board by using an acidic copper plating porefilling special liquid medicine; in the hole filling electroplating process, a multi-stage electroplating current parameter program is adopted, in-hole pre-plating is carried out at low current density in the initial stage, it is ensured that hole walls are evenly covered, after the main hole filling stage is started, pulse or periodic reverse current is adopted, the current density is increased in a stepped mode, and through holes are filled with acid copper plating hole filling special liquid medicine; and parameters are adjusted at the last stage of filling to ensure that the copper thickness of the hole surface is uniform, and dished pits or excessive recesses are avoided.

The invention relates to the field of integrated circuit manufacturing, in particular to a high-precision positioning jig for an SMT (surface mount technology) mounting line, which comprises a tray for bearing a circuit board, the positioning mechanism is arranged on the tray and comprises a pressing assembly and a wedge-shaped assembly, and the wedge-shaped assembly is used for triggering the pressing assembly to press and position the circuit board before solder paste printing; according to the invention, the tray is used for bearing the circuit board, and the wedge-shaped assembly in the positioning mechanism is used for triggering the pressing assembly to carry out horizontal pressing positioning on the circuit board, so that the assembly is ensured to be flush with the upper surface of the tray in a non-working state, and the requirement of solder paste printing and component surface mounting for no projection interference is met; the steel mesh attaching gap or visual identification interference is avoided; and a limiting assembly is triggered by a shifting assembly in the reinforcing mechanism to tightly press the circuit board in the vertical direction, so that the fixed dimension is supplemented, and multidirectional stress generated by thermal expansion of the circuit board at high temperature in reflow soldering is effectively counteracted.

The invention relates to the field of integrated circuit manufacturing, in particular to an optical proximity correction method and device. Determining a target wafer grid image according to a preset grid size and the target wafer pattern; taking the target wafer pattern as a current mask pattern; inputting the current mask pattern into a pre-trained three-dimensional optical proximity correction model, and obtaining an emulational wafer grid image with the assistance of a grid size; calculating an edge height error corresponding to each edge section; judging whether the edge height error exceeds a preset adjustment threshold value or not; when the edge height error exceeds a preset adjustment threshold value, adjusting the position of each edge section in the corresponding normal direction according to the edge height error to obtain an updated current mask pattern; and the step 4 to the step 7 are cycled until the edge height error does not exceed the adjustment threshold value. According to the invention, the defects of photoresist height loss and the like are reduced, and the yield of finished products is improved.

This invention discloses a method for manufacturing a flexible circuit board and a flexible circuit board, relating to the field of integrated circuit manufacturing technology. The method includes the following steps: providing a flexible copper-clad laminate (CCL) having a pre-processed area; drilling holes in the CCL to form positioning holes, the positioning holes partially overlapping with the pre-processed area and forming a semi-circular notch in the overlapping area; providing a punching die to punch the flexible CCL, the area covered by the projection of the punching die along the punching direction forming a first projection pattern, the first projection pattern partially overlapping with the pre-processed area and forming a pad half-hole in the overlapping area, the pad half-hole completely covering the semi-circular notch, and the sidewall of the pad half-hole forming a sidewall copper-plated area. By forming a larger sidewall copper-plated area formed by the sidewall of the pad half-hole, sufficient and stable solder volume can be provided for soldering, reducing the risk of cold solder joints and improving the yield of integrated circuit manufacturing, production of dedicated lithography machines, and etching machines.

The utility model relates to an integrated circuit printing device in the technical field of integrated circuit printing, which comprises a body and an adsorption platform, the adsorption platform is provided with a plurality of vacuum holes, the side edge of the body is provided with side edge vacuum holes, and the body is internally provided with a limiting pin. According to the utility model, an optimization mode that the PCB units are in one-to-one correspondence with the vacuum holes is adopted, so that the adsorption effect is greatly enhanced, the phenomena of substrate warping, shaking and the like caused by vacuum adsorption weakness in the printing process are effectively avoided, the solder paste printing balling quality is greatly improved, the defective rate of products is remarkably reduced, and the production efficiency is improved. And the production efficiency is greatly improved, and considerable economic benefits are created for integrated circuit manufacturing enterprises.

The invention relates to the field of integrated circuit manufacturing, in particular to an integrated circuit and a packaging method thereof. Etching an open groove in the blank area; embedding the embedded core particles into the open groove to obtain an integrated chip; a graphical insulation blocking layer is arranged on the upper surface of the integrated chip; obtaining a top wiring layer on the basis of the insulation blocking layer; inversely mounting external core particles on the top wiring layer; the external core particles are electrically connected with the embedded core particles through the top wiring layer. The core particles and the chip are silicon-based integrated circuits, thermal expansion coefficients are highly matched, and heat dissipation is facilitated; on one hand, the integration level of the core particles of the packaging device is improved, and on the other hand, vertical short-distance interconnection between the core particles is provided, so that the signal quality is guaranteed; through silicon vias penetrating through the embedded core particles are prevented from being formed in the embedded core particles, so that the signal transmission path is shortened, and meanwhile, the low production cost and the high embedded core particle setting flexibility are guaranteed.

The application provides a laser annealing method and system, and relates to the field of integrated circuit manufacturing. The method comprises the following steps: a first laser module is used to emit a first laser beam with a first wavelength to a wafer, and a second laser module is used to emit a second laser beam with a second wavelength to the wafer; the reflectivity of the wafer to the laser beams with the first wavelength and the second wavelength is measured, and a reflectivity ratio is obtained; the annealing temperature of the wafer is measured; according to the measured annealing temperature and a target annealing temperature, a target total power is determined, and according to the reflectivity ratio and the target total power, the power of the first laser module and the second laser module is adjusted. According to the method, the reflectivity of the wafer to the laser beams with the two wavelengths is complementary to a certain extent, so that the pattern effect can be improved, and the annealing temperature uniformity of the wafer is improved. According to the measurement results of the annealing temperature and the reflectivity, the power is adjusted, so that the annealing temperature non-uniformity of the wafer is corrected, and the annealing temperature uniformity of the wafer is further improved.

The application discloses a kind of integrated circuit surface defect classification methods based on differential manifold, including: microscopic imaging acquisition system, image pre-processing system and defect image classification system, first, the integrated circuit image after pre-processing is mapped to Riemann manifold space;Second, the feature descriptor of image is constructed, the characteristic vector is obtained, that is, covariance matrix can be constructed and corrected as the positive definite symmetric matrix of Lie group manifold;Then, further map the matrix to low-dimensional Lie group space, design Lie group kernel function;Finally, realize the accurate classification of integrated circuit surface diversity defect image.The application solves the problem of rapid classification of integrated circuit surface diversity defect image, improves the reliability in the process of integrated circuit manufacturing, and guarantees the quality of integrated circuit downstream application industry.

This invention relates to the field of CMOS integrated circuit manufacturing processes and discloses a method for fabricating a PIP capacitor. First, the WSi of the lower electrode of the PIP capacitor is reduced by implantation. x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

The invention relates to the technical field of semiconductor packaging and integrated circuit manufacturing, belongs to the field of ultrasonic welding in metal wire bonding, and discloses a gold wire high-strength bonding structure and method on an organic substrate. One end of the gold bonding wire is welded on the chip, the other end of the gold bonding wire is welded on the substrate, and the welding end of the gold bonding wire on the substrate is fixed between the gold wire ball unit groups through superposition. According to the invention, the technical problems of two-welding crescent exposure, low bonding strength and poor reliability in the prior art are solved.

The application discloses a temperature control device and a system for integrated circuit manufacturing. The temperature control device comprises at least two circulating flow channels connected to a load to provide circulating liquid to the load; a semiconductor refrigerating sheet group for cooling or heating the circulating liquid in the circulating flow channels; a pump for pressurizing and conveying the circulating liquid; an information acquisition unit for acquiring physical quantity data of the circulating liquid; a control center for issuing adjustment instructions according to the physical quantity data and preset temperature values; a control valve group for connecting corresponding circulating flow channels to the load according to the adjustment instructions; and an adjustable direct-current power supply for controlling the working mode and output temperature of the semiconductor refrigerating sheet group according to the adjustment instructions.