77 results about "Integrated circuit manufacturing" patented technology

The application provides a laser annealing method and system, and relates to the field of integrated circuit manufacturing. The method comprises the following steps: a first laser module is used to emit a first laser beam with a first wavelength to a wafer, and a second laser module is used to emit a second laser beam with a second wavelength to the wafer; the reflectivity of the wafer to the laser beams with the first wavelength and the second wavelength is measured, and a reflectivity ratio is obtained; the annealing temperature of the wafer is measured; according to the measured annealing temperature and a target annealing temperature, a target total power is determined, and according to the reflectivity ratio and the target total power, the power of the first laser module and the second laser module is adjusted. According to the method, the reflectivity of the wafer to the laser beams with the two wavelengths is complementary to a certain extent, so that the pattern effect can be improved, and the annealing temperature uniformity of the wafer is improved. According to the measurement results of the annealing temperature and the reflectivity, the power is adjusted, so that the annealing temperature non-uniformity of the wafer is corrected, and the annealing temperature uniformity of the wafer is further improved.

The embodiment of the application discloses a kind of circuit systems based on cascaded bidirectional gallium nitride, it is applied to integrated circuit manufacturing and production special photoetching machine, etching machine and other semiconductor device special equipment manufacturing field.Circuit system includes the first field effect tube, bidirectional gallium nitride device and second field effect tube connected in series, substrate selection switch between the substrate electrode of connecting bidirectional gallium nitride device and the source of each field effect tube, negative voltage grid drive network for driving each substrate selection switch, and clamping holding network for clamping or keeping the voltage of one end of each substrate selection switch, to inhibit "self-triggering" caused by device body capacitance charging under voltage rate of change (i.e. dv / dt), avoid two substrate selection switches to form straight-through while being turned on simultaneously.Especially suitable for the demand of strategic emerging industry high-performance integrated circuit and semiconductor special equipment manufacturing.

A computer-implemented method of processing first metrology data of a patterned portion of a substrate patterned using a wafer processing apparatus to generate predicted second metrology data of the, or another corresponding, patterned portion of the substrate, the first metrology data comprising metrology data from a first metrology domain which obtains metrology data using a first metrology process. The method comprises obtaining the first metrology data of the patterned portion of the substrate, and generating predicted second metrology data of the patterned portion of the substrate, or of the corresponding patterned portion of the substrate, based on the output of a first trained diffusion model conditioned on the first metrology data, the predicted second metrology data comprising predicted metrology data from a second metrology domain which obtains metrology data using a second metrology process.

This invention relates to the field of integrated circuit manufacturing, specifically disclosing a semiconductor photoelectric level sensor, its fabrication method, and its application. The sensor is a sheet-like structure comprising: a substrate including multiple photodiodes evenly distributed on a ring with a first circular axis perpendicular to the substrate as its axis of symmetry; a circular cavity located on the substrate, perpendicularly corresponding to the ring formed by the multiple photodiodes, and containing a rollable microgravity sphere; and a first signal light guide located on the circular cavity, also circular in shape and perpendicularly corresponding to the cavity, for vertically guiding actively irradiated circular signal light into the cavity. This invention utilizes the lowest point of the circular cavity where the rollable microgravity sphere can freely roll under gravity, and simultaneously guides actively irradiated circular signal light vertically into the cavity, with the multiple photodiodes accurately sensing the precise angular position of the rollable microgravity sphere.

According to some embodiments, methods, systems, and media for using synthetic images are presented. In some embodiments, a method involves obtaining a set of images related to an integrated circuit fabrication chamber, where the set of images includes at least a subset of synthetic images. Each synthetic image of the subset of synthetic images is a photo-realistic synthetic image. In some embodiments, at least a portion of the synthetic images presents an abnormal condition related to the fabrication chamber, and each image in the set of images presents at least one of: 1) a component of the fabrication chamber; 2) a process occurring in the fabrication chamber; or 3) a wafer property of a wafer being processed in the fabrication chamber. The method can also involve using the set of images to train a machine learning model, where the trained machine learning model can be used to predict the abnormal condition.

The application provides a surface plasmon photolithography device and a preparation method for improving imaging aspect ratio, which can be applied to the fields of integrated circuit manufacturing and photolithography technology. The surface plasmon photolithography device comprises a metal reflection layer, an optical metamaterial photoresist layer and a mask layer which are sequentially stacked from bottom to top; wherein the optical metamaterial photoresist layer comprises a photoresist and a metal nanoparticle array embedded in the photoresist, the metal nanoparticle array comprises at least one metal nanoparticle layer, and the metal nanoparticle layer is composed of metal nanoparticles arranged periodically; the metal nanoparticle layer is arranged in parallel to the mask layer, wherein when the metal nanoparticle layer comprises a plurality of metal nanoparticle layers, the different metal nanoparticle layers are located in different planes. The application further provides a preparation method of the surface plasmon photolithography device for improving imaging aspect ratio.

The utility model discloses a wafer film covering device for integrated circuit manufacturing relates to the field of integrated circuit manufacturing, including closed box, be provided with the film covering mechanism in the upper end in closed box, be provided with wafer bearing mechanism in the lower end in closed box, be provided with the loading positioning mechanism in closed box, and the loading positioning mechanism includes the positioning support, a plurality of circumferentially uniformly arranged deflection rods are rotationally connected on the positioning support, the cross connecting disc is fixed in the top of deflection rod, and the adjacent cross connecting disc is hinged through the connecting rod, and the other end fixed with the material receiving tray of deflection rod, and the material receiving tray is fixed with the positioning ring, and the positioning cylinder is hinged between one deflection rod on the positioning support. The beneficial effect lies in: before loading, the wafer is supported through a plurality of circumferentially uniformly arranged material receiving trays, and then a plurality of positioning rings synchronous movement is centered clamped to the wafer, thereby realizing the centring positioning of wafer, and this positioning mode has high centring accuracy, positioning speed is fast, and is convenient for taking and placing.

This invention relates to the field of semiconductor manufacturing technology, specifically to a low-damage, rapid curing equipment for photoresist in driver IC production, used in semiconductor integrated circuit manufacturing. It includes a main body, a wafer processing chamber, a conveyor belt, and semiconductor wafers. It also includes an ultraviolet (UV) adjustment mechanism, an infrared (IR) adjustment mechanism, an infrared radiation source, a UV radiation source, a linkage mechanism, a zoned curing mechanism, and a reinforcement mechanism. The UV and IR adjustment mechanisms are connected within the wafer processing chamber. The UV and IR radiation sources are respectively connected to the UV and IR adjustment mechanisms. The linkage mechanism is connected to the UV adjustment mechanism. This invention adjusts the power density of the irradiation received by the semiconductor wafer through variations in the infrared ultraviolet radiation intensity. Simultaneously, by using zoned irradiation to cure the photoresist on the semiconductor wafer in zones, it can improve the curing quality of the semiconductor wafer and further enhance its curing efficiency.

The present application relates to the technical field of integrated circuit manufacturing, and in particular to a chemical vapor deposition machine, which comprises a reaction cavity, a shower head and a wafer pedestal arranged in the reaction cavity, the wafer pedestal comprises a bearing part for bearing a wafer, the bearing part is arranged opposite to the shower head, and the bearing part can rotate relative to the shower head to adjust the included angle between the wafer and the spraying direction of the shower head. By driving the bearing part to rotate relative to the shower head, the wafer is driven to rotate relative to the shower head, and the included angle between the wafer and the spraying direction of the shower head is adjusted, so that multiple film layer test points with different thicknesses can be obtained on a wafer at the same time, the optimal film layer thickness can be efficiently determined by further testing the multiple film layer test points, the development speed of the film layer process of a new product is greatly improved, the number of wafers used in development is reduced, and the development cost is saved.

This invention relates to the field of integrated circuit manufacturing technology and discloses a digital self-calibration circuit and method for a SAR ADC capacitor array. In the process of integrated circuit manufacturing and on-chip analog-to-digital conversion circuit implementation, by causing the target capacitor to generate excitations with opposite polarities and corresponding amplitudes in odd-numbered and even-numbered calibration cycles, the DC offset components of the comparator cancel each other out during the difference calculation. By generating bit decisions through multiple statistical methods for the comparison results of each bit of the sub-ADC, the disturbance of thermal noise to the final calibration result is reduced at the bit decision level. By alternating between odd and even calibration cycles and performing pairing and difference calculation in a short time, the influence of flicker noise in adjacent calibrations is reduced. By solving the capacitor weights of each bit sequentially from low to high bits, the propagation of errors at each level is reduced. By digitally reconstructing the output result after all weights have been solved, the final output of the SAR ADC is made closer to the actual capacitor array weight relationship.

The present application belongs to the technical field of integrated circuit manufacturing, and particularly relates to a preparation method of a TMV chip. The method comprises the following steps: forming a sandwich structure adhesive layer on a re-wiring layer structure; the sandwich structure adhesive layer comprises a first photoresist layer, a DAF film layer and a second photoresist layer which are stacked in sequence; patterning the sandwich structure adhesive layer to form an electroplating mold cavity which penetrates through the first photoresist layer, the DAF film layer and the second photoresist layer, and exposes a pad area on the re-wiring layer structure; and electroplating to form a copper pillar with a large cross section and a high aspect ratio in the electroplating mold cavity. The present application can controllably form a copper pillar with a large cross section and a high aspect ratio in a mold sealing medium, realize low resistance, high current carrying capacity, good heat dissipation and mechanical support capacity, and also consider the morphology consistency, coplanarity and reliability under mass production conditions.

This invention relates to the technical field of integrated circuit manufacturing, specifically to a composite heat dissipation and filtering integrated device for power PCBs, comprising a heat dissipation platform one, multiple plungers, a thermally conductive microcapsule layer, a thermal pusher strip, a heat dissipation platform two, a metal thermally conductive block, and a linkage mechanism; the heat dissipation platform one is mounted on the upper surface of the power device, and the heat dissipation platform one has multiple mounting holes with bottom openings; by setting up an array of plungers and thermal pusher strips, the thermal expansion effect is used to achieve adaptive balance of the heat dissipation clamping force of the power device, eliminating local hot spots; the pressure-triggered microcapsule rupture mechanism releases thermally conductive grease as needed, dynamically compensating for contact thermal resistance; the metal thermally conductive block and linkage mechanism convert the plunger displacement into synchronous clamping force on the filter capacitor, effectively suppressing the failure of the filter capacitor due to microcracks caused by PCB bending or vibration, realizing coordinated adaptive adjustment of heat dissipation and filtering, and significantly improving the long-term reliability of the power PCB under harsh operating conditions.

This invention discloses a chip quality anomaly analysis method and system that integrates timing resistance data, relating to the field of integrated circuit manufacturing and testing technology. The method includes: obtaining circuit component manufacturing parameters, predicting resistance, and obtaining circuit component resistance values; building a graph neural network based on chip circuit component design data, training a digital chip with circuit component resistance values ​​and test input timing signals as node inputs, and generating a predicted output timing signal; comparing the predicted output timing signal and the test output timing signal to obtain a signal timing deviation coefficient; and returning a chip quality anomaly signal to the chip manufacturing end when the signal timing deviation coefficient is greater than or equal to a deviation coefficient threshold. This invention performs virtualized quality prediction before chip physical manufacturing, reducing material waste caused by traditional testing and forming a closed loop from testing to process optimization, thereby improving the quality control capability and process regulation efficiency of the manufacturing process.

The application discloses a transverse-alternating PCB board splitter and belongs to the technical field of integrated circuit manufacturing equipment, which comprises a workbench arranged horizontally, a mechanical hand arranged on the top of the workbench and used for clamping a PCB board, a board splitting table arranged on one side of the workbench and used for placing the PCB board to facilitate splitting of the PCB board, a conveying device arranged on one side of the board splitting table, a slide rail arranged directly above the conveying device, a sliding block horizontally and slidably connected to the slide rail and arranged at the groove end of the slide rail, a cutting device arranged at the bottom of the sliding block, a driving assembly arranged on the slide rail, a righting and dredging device arranged on the sliding block, and a lubricating device arranged in the sliding block. The application can remove impurities in the area where the slide rail is jammed in the first time when the slide rail mechanism is jammed or the sliding block is deflected, right the deflected sliding block, lubricate the area after the impurities are removed, facilitate smooth movement of the cutting device, and improve the effect of PCB board splitting quality.

This invention relates to the field of integrated circuit manufacturing, and particularly to a photomask slicing layout, comprising an island distribution pattern. The island distribution pattern includes multiple island columns arranged along a first direction, and each island column includes multiple island cells along a second direction. The first direction is perpendicular to the second direction. The island cells in adjacent island columns are staggered, such that the projection of any island column in the first direction does not completely overlap with the projection of the adjacent island column in the first direction. This invention, by staggering multiple island columns in the island distribution pattern, significantly increases the probability of cutting the feature pattern (i.e., the island cell) when the photomask slicing layout is manually sliced, thereby increasing the probability of successful manual slicing profile characterization and ensuring low testing costs and high testing efficiency in slicing testing.

The application belongs to the field of integrated circuit manufacturing, and particularly relates to a single-layer diffusion barrier layer with low resistivity and high failure temperature for copper interconnection. The diffusion barrier layer is a copper interconnection diffusion barrier layer, which is located between copper and a silicon substrate, and contains M and N elements, wherein M is selected from one of Zr and Hf. The copper interconnection diffusion barrier layer is prepared by a magnetron sputtering process, and the nitrogen content accounts for 18% to 25% of the working gas content during the preparation of the copper interconnection diffusion barrier layer by magnetron sputtering. The single-layer nitride diffusion barrier layer prepared by magnetron sputtering has an ultra-thin thickness, a resistivity lower than 40 micro-ohm per centimeter (even lower than 10 micro-ohm per centimeter) at 600 degrees Celsius, and a failure temperature higher than 600 degrees Celsius. The application has reasonable component design, simple and controllable process, and is convenient for industrial application.

The application belongs to the technical field of integrated circuit manufacturing, and relates to a circuit board drilling device with a stable clamping structure. The device comprises a shell, the shell is fixedly connected with a connecting frame, the connecting frame is slidably connected with a first electric sliding frame, the first electric sliding frame is slidably connected with a second electric sliding frame, the second electric sliding frame is slidably connected with a third electric sliding frame, the third electric sliding frame is fixedly connected with a shell body, the shell body is rotationally connected with a rotating shaft, the rotating shaft is provided with a drill bit, the rotating shaft is slidably and rotationally connected with a rotating cylinder, the rotating cylinder is rotationally connected with an upper pressing plate, the upper pressing plate is slidably connected with a lower pressing plate, and the lower pressing plate is rotationally connected with a rotating pressing ring. The circuit board is clamped by the rotating pressing ring and the supporting frame. When the circuit board is twisted around the drilling position under stress, the clamping block no longer clamps the circuit board. The circuit board drives the rotating pressing ring to rotate, reduces the stress damage of the circuit board drilling position, and even reduces the probability of deformation of the circuit board, so as to guarantee the accuracy of the circuit board drilling and improve the quality of the circuit board drilling.

The application provides a kind of corrective etching method and equipment, it is related to integrated circuit manufacturing technical field.The method comprises the following steps: providing etched wafer; the surface of the wafer is non-destructive measurement, obtains the surface parameter of each surface area of wafer; based on the surface parameter and collation target value, the required correction etching amount of each surface area of wafer is calculated; the surface of wafer is irradiated by focused light beam to induce etching; based on the position information and the correction etching amount, the light irradiation parameter of the focused light beam is adjusted accordingly, different irradiation amount is applied to each surface area of wafer, to obtain the required correction etching amount, the light irradiation parameter includes light intensity and / or irradiation time length.The application can correct the surface of etched wafer, so that the size of each area of wafer surface is consistent, improve etching uniformity, so as to improve the performance and yield of final product.

This application relates to the field of semiconductor integrated circuit manufacturing technology, specifically to an SOI-LDMOS device and its fabrication method. The SOI-LDMOS device includes: a substrate layer, a buried oxide layer, and an epitaxial layer stacked sequentially from bottom to top; a drift region is formed in the epitaxial layer; a source region and a drain region are formed on both sides of the drift region; a doped polysilicon field plate is formed on the drift region, and a vertical heterojunction is formed between the doped polysilicon field plate and the drift region. When the device is in the off state, the vertical heterojunction is depleted; one end of the doped polysilicon field plate contacts and overlaps with the source region to form a vertical homojunction; the other end of the doped polysilicon field plate is doped with a first conductivity type impurity to form a first conductivity type doped region; the main body of the doped polysilicon field plate forms a lateral heterojunction with the first conductivity type doped region; the doped polysilicon field plate contacts the metal electrode of the drain region through the heterojunction. The fabrication method is used to fabricate the above-mentioned SOI-LDMOS device.

This application relates to the field of integrated circuit manufacturing and discloses a wafer processing technology, including: obtaining a wafer after back cleaning; cleaning the back side of the wafer with an alkaline solution to neutralize the acidic substances remaining on the back side of the wafer after back cleaning; and performing photolithography on the wafer after cleaning with the alkaline solution. This application cleans the back side of the wafer with an alkaline solution before performing photolithography on the back side of the wafer after back cleaning. The alkaline solution can neutralize the acidic substances remaining on the back side after back cleaning. Because the acidic substances remaining after back cleaning are neutralized and removed, even if there are chemical residues at the edge of the back side after photolithography, white crystal defects will not be generated at the edge of the back side of the wafer, improving wafer quality and avoiding the risk of subsequent wafer breakage. Furthermore, this application also provides a wafer with the above advantages.

This application relates to a method for reducing native defects in silicon single crystals after growth for integrated circuits. It discloses a method that utilizes the dual coupling effect of high-frequency eddy current temperature control and DC electric field on the carrier regularization in the crystal to fully dissolve the native defects in the crystal and make them diffuse in a directional and uniform manner, so that the nucleation sites of the native defects are evenly distributed at high temperatures. During the cooling process, a rapid cooling method is used to control the nucleation size of the native defects and restrict their aggregation and diffusion under the action of DC electric field, thereby achieving the purpose of reducing the size of the native defects in the silicon single crystal and making them evenly distributed, thus meeting the requirements of advanced integrated circuit manufacturing processes.

A substrate-integrated microwave circulator and its fabrication method are disclosed, belonging to the field of microwave devices and integrated circuit manufacturing. The circulator includes an integrated substrate, a planar rectangular waveguide, and a gyromagnetic core. The integrated substrate includes input and output port regions located within a hexagonal functional region. Three sets of through slots form three mutually spaced 120° side length regions within the hexagonal functional region. The input and output port regions include three metallized conductors extending along the directions of the three side length regions. The planar rectangular waveguide is formed by a metal layer on the surface of the integrated substrate, metal sidewalls of the through slots, and a metal ground layer on the back side. The gyromagnetic core is embedded in the center of the integrated substrate. This invention utilizes a closed cavity formed by metallization of the substrate's inner wall to construct three sets of planar rectangular microwave guides distributed at 120° intervals, which are highly integrated with the central gyromagnetic core. This device has a compact structure, low loss, and its fabrication process is highly compatible with semiconductor integrated circuit processes, making it suitable for the mass production of high-performance microwave integrated systems.

The application discloses a method for neural network online training and reasoning based on a CMOS transistor hybrid memory circuit, which adopts a CMOS transistor synapse device and a CMOS capacitor to form a synapse unit, replaces a traditional memristor and a ferroelectric capacitor, the writing durability of the CMOS transistor synapse device is far superior to that of the traditional memristor, the reading operation of the CMOS capacitor is non-destructive, the life loss caused by data rewriting is avoided, the whole process is realized based on a standard CMOS process, is fully compatible with an existing integrated circuit manufacturing process, and the hardware production cost is reduced, only analog weights are called in the reasoning stage to perform operation, and there is no additional data transmission; in the weight transmission stage, an external DAC is not needed, digital-to-analog conversion is realized by using a circuit parasitic parameter, and the energy consumption of an edge device is greatly reduced.

This disclosure provides a hard mask structure for integrated circuit manufacturing and a method for manufacturing integrated circuit devices, relating to the field of pattern transfer technology in chip manufacturing processes. The hard mask structure includes a first hard mask layer and a second hard mask layer stacked from top to bottom, wherein: the surface of the first hard mask layer is used to form a noble metal and serves as a pattern transfer sacrificial layer; the second hard mask layer serves as a protective layer for etching the pattern material to be transferred; the first and second hard mask layers are made of different materials and both are resistant to corrosion by strong oxidizing chemical solutions that remove the noble metal; the second hard mask layer is resistant to wet etching of the chemical solution that removes the first hard mask layer and ensures a preset corrosion rate selectivity for the first hard mask layer. This disclosure can avoid the damage to devices caused by noble metal ions, enabling the use of noble metal thin films in the manufacture of large-scale integrated circuits.

According to the disclosure, a position detection system using laser light interferometry is proposed, capable of measuring the positions and displacements of an object relative to and within an XYZ system of coordinates.By directing the Y laser light beam parallel to the XY plane to and from a Y measuring mirror positioned perpendicular to the XY plane and directing the Z laser light beam under an angle α relative to the XY plane to and from a Z measuring mirror, the optics of the position detection system can be simplified as any additional Z measuring mirror can be obviated. Particularly, this results in less occupied work volume in the direct vicinity where semiconductor and integrated circuit manufacturing processes.

The application provides an electrical wiring component, a consumable chip and an ink cartridge, and relates to the technical field of integrated circuit manufacturing and integrated circuit design. The electrical wiring component comprises a plurality of contact points for contacting a stylus of an imaging device. The plurality of contact points comprises a plurality of corner contact points and a plurality of non-corner contact points. At least two of the corner contact points are suspended contact points that contact the stylus but are not electrically connected to a printhead chip. By making at least two of the corner contact points suspended contact points, the number of corner contact points that are electrically connected to the imaging device is reduced, thereby reducing the risk that the corner contact points will be contaminated and unable to normally electrically connect to the corresponding stylus, resulting in insufficient contact between the terminals on the consumable chip side and the imaging device main body side, and the risk that the consumable chip and the imaging device will not be normally electrically connected.