Air-gap grapheme transistor and manufacturing method thereof

Abstract

The invention belongs to the technical field of carbon integrated circuit manufacturing, in particular relates to an air-gap grapheme transistor and a manufacturing method thereof. In the method, gate electrodes and gate medium grow on a silicon base and then source and drain graphics are formed; grapheme is transformed to the formed source and drain graphics so as to separate the grapheme from the gate medium; and the air-gap is used to separate the grapheme from the gate medium so as to eliminate the growth process of a buffer layer on the grapheme, thus high mobility of carriers in the grapheme is retained maximally, and deterioration for the surface properties of the grapheme is reduced, thereby further improving electrical properties of grapheme devices.

Description

technical field [0001] The invention relates to a graphene transistor and a preparation method thereof, in particular to a novel air-gap graphene transistor and a preparation method thereof, and belongs to the technical field of carbon-based integrated circuit manufacturing. Background technique [0002] According to Moore's Law, the integration level of chips doubles every 18 months to 2 years, that is, the processing line width is reduced by half. The processing limit of silicon materials is generally considered to be a line width of 10 nanometers. Silicon-based integrated circuits cannot break through its physical limitations after 11 nanometers, including current transmission loss, quantum effects, thermal effects, etc., so it is difficult to produce stable performance and higher integration. product. With the continuous development of semiconductor technology, the size of silicon-based integrated circuit devices is getting closer and closer to its physical limit. [0...

AI Technical Summary

Problems solved by technology

[0004] At present, graphene transistors still face two main problems: 1) the bandgap width of graphene is zero; 2) since the surface of graphene is basically chemically inert except for the edge, it is impossible to use atomic layer deposition method on graphene Direct Deposited Gate Dielectric on Surface

However, the scattering of ionized impurities related to the buffer layer or the scattering of phonons related to the oxide interface will seriously reduce the carrier mobility in graphene, degrading the electrical properties of graphene transistors.

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