466 results about "Electrical interconnect" patented technology

A package includes a first die with a bridging element with a first interconnect region, a first photonic transceiver portion, a second interconnect region, a first photonic path to an optical interface (OI), and a second photonic path from the OI to the first photonic transceiver portion. The first interconnect region electrically couples the first photonic transceiver portion to a second photonic transceiver portion in an analog / mixed-signal die (AMS die), while the second interconnect region connects a third photonic transceiver portion in a general die to the second photonic transceiver portion using an electrical coupling embedded in the first die. The electrical interconnects in the first interconnect region are less than two millimeters in length.

A package includes a first die with a compute element and first region, a second die with a compute element and second region, and a bridging element connecting the first and second dies. The bridging element includes interconnect regions for electrical coupling, a first photonic path from the first interconnect region to the second, and a second photonic path in the reverse direction. A photonic transceiver is integrated into the bridging element, with one portion sending and receiving optical signals via the photonic paths, and the other portion located in an AMS block in the first die or second die near the memory and compute elements. The transceiver portions are connected by a short electrical interconnect (less than 2 mm).

A charging system comprises a local energy storage disposed at a charging site; an electric coupling configured to provide an electrical interconnect between the charging site and an electric vehicle (EV); and one or more controllers configured to: (i) detect a condition related to availability of electrical energy at the charging station, (ii) in response to the detecting of the condition: (a) estimate a number of EVs to which a charge remaining at the local energy storage is to be distributed within a certain time interval, (b) initiate a charging session for transferring electric energy from the local energy storage to the EV, via the electric coupling, and (c) limit an amount of electrical energy in the charging session in view of at least the estimated number of EVs.

An antenna apparatus includes an antenna substrate with opposite first and second surfaces; and a PCB having opposite first and second surfaces. Antenna elements are disposed at the first surface of the antenna substrate. Electrically conductive columns, each having a first end attached to the second surface of the PCB and a second end attached to the second surface of the antenna substrate, secure the PCB to the antenna substrate and provide an electrical interconnect between the PCB and the antenna substrate. RFIC chips are each attached to the second surface of the antenna substrate and are coupled to the antenna elements. At least one circuit element is attached to the first surface of the PCB and electrically coupled to at least one of the RFIC chips through at least one of the electrically conductive columns.

A method of fabricating a wearable and elastically stretchable thermoelectric generator or other thermoelectric device can involve arranging thermoelectric pellets and printing a thermal insulation material alongside and / or around the thermoelectric pellets to form a core layer. The core layer can be cured, and a liquid metal can be selectively deposited on the thermoelectric pellets to form contact points. Printing conductive ink can form stretchable electrical interconnects that define connections among the thermoelectric pellets via the contact points to form an initial middle layer that includes the stretchable electrical interconnects. Printing a thermal interface material may form an initial outer layer positioned between the initial outer layer and an initial side of the core layer to form a layered assembly. The layered assembly may be inverted and receive additional printed layers building away from the core layer, such as an additional interconnect layer and an additional thermal interface layer.

The invention relates to a three-dimensional stacked high-power multi-channel dual-polarization airtight packaging T / R assembly, which comprises a power supply modulation layer, a multifunctional processing layer and a power amplifier low-noise amplifier layer which are sequentially stacked from bottom to top, and electrical interconnection among the three circuit layers and with the outside is realized by adopting the BGA solder balls. The three circuit layers adopt LTCC (Low Temperature Co-Fired Ceramic) or HTCC (High Temperature Coefficient Chip) to realize an integrated packaging structure with a cavity; the interior of the integrated structure is divided into a plurality of same independent cavities so as to accommodate circuits and structures of the channels; a signal transmission structure and a grounding through hole array are arranged in the cavity wall of the integrated structure, so that electrical interconnection, impedance matching and electromagnetic shielding inside and outside the package are realized; each cavity is sealed in an independent airtight mode through a metal cover plate. When necessary, a wave-absorbing material is added in the cavity to prevent self-excitation of the assembly. According to the invention, the product structure and the production process are simplified, the production efficiency, the packaging efficiency and the yield are improved, and the cost is reduced; the power capacity and the reliability of the product are improved, and the maintainability is good.

A package includes a bridging element (an OMIB), and first and second photonic paths, forming a bidirectional photonic path. The OMIB has first and second interconnect regions to connect with one or more dies. Third and fourth unidirectional photonic paths may couple between the first interconnect region and an optical interface (OI). A photonic transceiver has a first portion in the OMIB and a second portion in one of the dies. The first and the second portions may be coupled via an electrical interconnect less than 2 mm in length. The die includes compute elements around a central region, proximate to the second portion. The OMIB may include an electro-absorption modulator fabricated with germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), or a III-V material based on gallium arsenide (GaAs). The OMIB may include a temperature compensation for the modulator.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

Various embodiments include an image sensor package for a camera with sensor shift actuation. The camera may include one or more actuators (e.g., a voice coil motor (VCM) actuator) for moving the image sensor package relative to a lens group of the camera. The image sensor package may include an image sensor and a substrate. The image sensor may be electrically connected to a ledge surface of a lower portion of the substrate, via one or more wire bond electrical interconnects.

An acoustic device includes circuit elements, such as analog circuit components, between the first and second substrate and coupled to an acoustic resonator to form an acoustic filter within the acoustic device. In some examples, forming the circuit elements between the first substrate and the second substrate includes forming the first circuit elements in insulating material on the second substrate before coupling the second substrate to a first side of the first substrate. The circuit elements disposed between the first and second substrates may include capacitors, inductors, and electrical interconnects coupled to the acoustic resonator on the first substrate. Additional features may be included in the insulating material. The acoustic device avoids the need for bulky analog components coupled to the acoustic resonator via long interconnects through a package substrate, making it possible to reduce an acoustic device's package size.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

A moveable micromachined member of a microelectromechanical system (MEMS) device includes an insulating layer disposed between first and second electrically conductive layers. First and second mechanical structures secure the moveable micromachined member to a substrate of the MEMS device and include respective first and second electrical interconnect layers coupled in series, with the first electrically conductive layer of the moveable micromachined member and each other, between first and second electrical terminals to enable conduction of a first joule-heating current from the first electrical terminal to the second electrical terminal through the first electrically conductive layer of the moveable micromachined member.

The embodiment of the invention discloses a chip packaging system and electronic equipment. The chip packaging system comprises a PCB, a local interconnection component and a plurality of core particles, the local interconnection component is arranged on a board of the PCB, and each core particle is electrically interconnected with the PCB; the local interconnection component comprises a dielectric layer and a high-density interconnection circuit layer which are arranged in a stacked mode, and at least two core particles are electrically interconnected through the local high-density interconnection circuit. Thus, the core particles and the local interconnection parts are installed on the PCB to form a chip board-level system, and the installability, reliability and supptability of the system are effectively improved while the high-density layout requirement is met. Meanwhile, on the basis of the structural characteristic that the core particles are installed on the surface of the PCB through the local interconnection components, link loss caused by conventional packaging can be reduced, and system cost can be reduced.

A package substrate includes a first dielectric layer, a second dielectric layer and a core layer. The first dielectric layer includes first electrical interconnect. The second dielectric layer includes second electrical interconnect. The core layer is situated between the first dielectric layer and the second dielectric layer, and includes a plurality of semiconductor dies stacked one above another between the first dielectric layer and the second dielectric layer. A first semiconductor die of the semiconductor dies is a capacitor die electrically connected to the first electrical interconnect of the first dielectric layer.

An electrically conductive brickwork module configured to be used in an electrically heated thermal energy storage system and / or a resistive heating system to heat a fluid flowing across a dimension of the electrically conductive brickwork module from an input to an output. The module includes a plurality of electrically interconnected sets of electrically conductive bricks configured to be heated when electricity flows there through and a plurality of electrically insulating bricks separating each pair of adjacent sets of the plurality of electrically interconnected sets. There are and a plurality of flow paths defined by the plurality of electrically insulating and physically separated from the electrically conductive bricks to direct a fluid flowing from the input to the output.

An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a host wafer, and the chiplets have interconnections to host wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The host wafer has at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The host wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the host wafer circuit to the chiplet circuit.

The present disclosure relates to implantable medical devices having protective structures with integrated electrical interconnects. Particularly, aspects of the present disclosure are directed to a medical device that includes a first nest portion and a second nest portion mateable with the first nest portion to form a nest housing. The nest housing includes an interior surface and an exterior surface with a component cavity defined by the interior surface. An electronics module is disposed within a first region of the component cavity. A power source is disposed within a second region of the component cavity. An electrical interconnect is formed on or embedded within the first nest portion, the second nest portion, or a combination thereof. The electrical interconnect electrically connects the electronics module to the power source.

A conformable piezoelectric transducer array for performing ultrasound or the like includes a silicone elastomer substrate and a silicone elastomer superstrate. A plurality of piezoelectric transducer elements are disposed between the substrate and superstrate. A first electrical interconnect layer electrically interconnects a first surface of the transducer elements adjacent to the substrate and a second electrical interconnect layer electrically interconnecting a second surface of the transducer elements adjacent to the superstrate.

A method for testing a packaging substrate with at least one electron beam column is described, wherein the packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; directing at least one electron beam of the at least one electron beam column on at least a first portion of the packaging substrate; directing the at least one electron beam of the at least one electron beam column on at least a second portion of the packaging substrate; detecting signal electrons emitted upon impingement of the at least one electron beam for testing a first device-to-device electrical interconnect path of the packaging substrate; and illuminating at least a third portion of the packaging substrate with UV radiation.

The invention belongs to the field of microelectronic packaging, and discloses an integrated chip near-node diamond micro-channel heat dissipation packaging structure and a preparation method thereof.The integrated chip near-node diamond micro-channel heat dissipation packaging structure comprises an electrical interconnection structure, a 3D integrated chip and a heat dissipation module which are stacked in sequence, and the electrical interconnection structure is connected with the 3D integrated chip through a contact of the 3D integrated chip; the heat dissipation module comprises a heterogeneous bonding layer, a diamond substrate, a metal circuit layer and a copper-based diamond micro-channel layer which are stacked in sequence, and the heterogeneous bonding layer is in contact with one surface, close to the node side, of the 3D integrated chip; a micro-channel structure is arranged in the copper-based diamond micro-channel layer; and the micro-channel structure is filled with liquid metal. The heat dissipation module is arranged on the side, close to the node, of the 3D integrated chip, and based on the design of the high-heat-conductivity heat dissipation material and the heat dissipation structure in the heat dissipation module, the effect that the compatible heat dissipation efficiency of the 3D integrated chip is improved and the 3D integrated chip is convenient to use can be achieved by integrally manufacturing the micro-channel structure.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

Methods and apparatuses for plasma treatment of electrical interconnects of electronic assemblies for integrated circuits such as flip chips are disclosed. A method of interconnect bonding includes applying a plasma comprising activated hydrogen via an atmospheric pressure plasma applicator to a metallic contact supported on a substrate to remove oxidation and create a newly deoxidized metal surface. The metallic contact can be bonded to another via reflow or thermocompression bonding. An inert gas environment can be formed within an enclosure for application of the plasma and / or bonding of the metallic contact.

A modular, electronic shelf label (201, 203, 205, 207, 209, 218, 219, 221-224) mounted on, above or below, a merchandise shelf, including a host unit (231 ) including a housing (232, 233), a communicator (244) located within the housing (232, 233) for receiving label data for merchandise (110-118) on the shelf (101-109) from a server computer (150), sending data to the server (150), and communicating with communicators (244) in other host units (231 ), a first connection slot (251 ) in a top or front surface of the housing (232, 233), a second connection slot (272) in a rear or bottom surface of the housing (232, 233), first electrical interconnection functionality located within the housing for connecting a first module (235) to the communicator (244) via the first connection slot (251 ), and second electrical interconnection functionality located within the housing for connecting a second module (235) to the communicator (244) via the second connection slot (272), a first module (235) connected to the host unit (231 ) via the first connection slot (251 ), and a second module (235), connected to the host unit (231 ) via the second connection slot (272).

The present invention relates to a TSV electrical interconnect structure having a high aspect ratio and method of manufacturing it. In the method, a backside via and a backside contact pad connected to the backside via are formed on a backside of the semiconductor base. A front-side via connected to the backside via is then formed in the front side of the semiconductor base, obtaining a TSV which electrically connects the front side and backside of the semiconductor base that has a thickness greater than or equal to 150 μm. The TSV has an aspect ratio higher than 20, which can meet the requirements of package-level matching. The TSV electrical interconnect structure having a high aspect ratio can be connected to a package substrate or a PCB board through the backside contact pad. A rewiring layer on the front side of the semiconductor base is connected to the front-side via, and the TSV electrical interconnect structure having a high aspect ratio can provide an interconnection through the rewiring layer. Moreover, one or more other semiconductor bases may be stacked on the front side.

An apparatus may include a microfluidic chip including at least one microfluidic channel and a first at least one electrical interconnect. An apparatus may include a circuit board having at least one interface interconnect and a second at least one electrical interconnect electrically coupled with the first at least one electrical interconnect of the microfluidic chip. An apparatus may include a cartridge enclosing the microfluidic chip and the circuit board, the cartridge including at least one opening allowing access to the at least one microfluidic channel on the microfluidic chip and the at least one interface interconnect.

The utility model discloses a low-inductance power module, which comprises an insulating shell, a heat dissipation bottom plate and a plurality of power conversion units, and is characterized in that the heat dissipation bottom plate is connected with the insulating shell; the plurality of power conversion units are arranged on the heat dissipation bottom plate, each power conversion unit comprises a substrate, a plurality of copper clamps and a plurality of chips, the front surfaces of the plurality of chips are provided with source electrodes and are respectively connected with the first conductive layer through the copper clamps, and the back surfaces of the plurality of chips are provided with drain electrodes and are connected with the second conductive layer; grid electrodes of a plurality of chips are connected with the third conductive layer through metal leads, the adopted chips are metal oxide semiconductor field effect transistors, source electrodes of the chips adopt copper clamp structures to achieve electrical interconnection between the chips and the substrate, and compared with a connection mode of the metal leads, the copper clamps can offset more magnetic flux generated by current, so that the reliability of the device is improved. The chip and the substrate, the chip and the copper clamp, and the copper clamp and the substrate are interconnected by adopting a nano-metal sintering process, so that the thermal reliability of the interconnection part is improved, the copper clamp and nano-metal sintering process is conveniently realized through the overall layout design of the substrate, the effect of low parasitic inductance of the module is realized, and the reliability of the module is improved. And module reliability is improved.

A method for testing a packaging substrate with at least one electron beam column is described, wherein the packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; directing at least one electron beam of the at least one electron beam column on at least a first portion of the packaging substrate; directing the at least one electron beam of the at least one electron beam column on at least a second portion of the packaging substrate; detecting signal electrons emitted upon impingement of the at least one electron beam for testing a first device-to-device electrical interconnect path of the packaging substrate; and illuminating at least a third portion of the packaging substrate with UV radiation.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.