264 results about "Electrical interconnect" patented technology

An antenna apparatus includes an antenna substrate with opposite first and second surfaces; and a PCB having opposite first and second surfaces. Antenna elements are disposed at the first surface of the antenna substrate. Electrically conductive columns, each having a first end attached to the second surface of the PCB and a second end attached to the second surface of the antenna substrate, secure the PCB to the antenna substrate and provide an electrical interconnect between the PCB and the antenna substrate. RFIC chips are each attached to the second surface of the antenna substrate and are coupled to the antenna elements. At least one circuit element is attached to the first surface of the PCB and electrically coupled to at least one of the RFIC chips through at least one of the electrically conductive columns.

A package includes a bridging element (an OMIB), and first and second photonic paths, forming a bidirectional photonic path. The OMIB has first and second interconnect regions to connect with one or more dies. Third and fourth unidirectional photonic paths may couple between the first interconnect region and an optical interface (OI). A photonic transceiver has a first portion in the OMIB and a second portion in one of the dies. The first and the second portions may be coupled via an electrical interconnect less than 2 mm in length. The die includes compute elements around a central region, proximate to the second portion. The OMIB may include an electro-absorption modulator fabricated with germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), or a III-V material based on gallium arsenide (GaAs). The OMIB may include a temperature compensation for the modulator.

Various embodiments include an image sensor package for a camera with sensor shift actuation. The camera may include one or more actuators (e.g., a voice coil motor (VCM) actuator) for moving the image sensor package relative to a lens group of the camera. The image sensor package may include an image sensor and a substrate. The image sensor may be electrically connected to a ledge surface of a lower portion of the substrate, via one or more wire bond electrical interconnects.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

A conformable piezoelectric transducer array for performing ultrasound or the like includes a silicone elastomer substrate and a silicone elastomer superstrate. A plurality of piezoelectric transducer elements are disposed between the substrate and superstrate. A first electrical interconnect layer electrically interconnects a first surface of the transducer elements adjacent to the substrate and a second electrical interconnect layer electrically interconnecting a second surface of the transducer elements adjacent to the superstrate.

A method for testing a packaging substrate with at least one electron beam column is described, wherein the packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; directing at least one electron beam of the at least one electron beam column on at least a first portion of the packaging substrate; directing the at least one electron beam of the at least one electron beam column on at least a second portion of the packaging substrate; detecting signal electrons emitted upon impingement of the at least one electron beam for testing a first device-to-device electrical interconnect path of the packaging substrate; and illuminating at least a third portion of the packaging substrate with UV radiation.

The invention belongs to the field of microelectronic packaging, and discloses an integrated chip near-node diamond micro-channel heat dissipation packaging structure and a preparation method thereof.The integrated chip near-node diamond micro-channel heat dissipation packaging structure comprises an electrical interconnection structure, a 3D integrated chip and a heat dissipation module which are stacked in sequence, and the electrical interconnection structure is connected with the 3D integrated chip through a contact of the 3D integrated chip; the heat dissipation module comprises a heterogeneous bonding layer, a diamond substrate, a metal circuit layer and a copper-based diamond micro-channel layer which are stacked in sequence, and the heterogeneous bonding layer is in contact with one surface, close to the node side, of the 3D integrated chip; a micro-channel structure is arranged in the copper-based diamond micro-channel layer; and the micro-channel structure is filled with liquid metal. The heat dissipation module is arranged on the side, close to the node, of the 3D integrated chip, and based on the design of the high-heat-conductivity heat dissipation material and the heat dissipation structure in the heat dissipation module, the effect that the compatible heat dissipation efficiency of the 3D integrated chip is improved and the 3D integrated chip is convenient to use can be achieved by integrally manufacturing the micro-channel structure.

The present invention relates to a TSV electrical interconnect structure having a high aspect ratio and method of manufacturing it. In the method, a backside via and a backside contact pad connected to the backside via are formed on a backside of the semiconductor base. A front-side via connected to the backside via is then formed in the front side of the semiconductor base, obtaining a TSV which electrically connects the front side and backside of the semiconductor base that has a thickness greater than or equal to 150 μm. The TSV has an aspect ratio higher than 20, which can meet the requirements of package-level matching. The TSV electrical interconnect structure having a high aspect ratio can be connected to a package substrate or a PCB board through the backside contact pad. A rewiring layer on the front side of the semiconductor base is connected to the front-side via, and the TSV electrical interconnect structure having a high aspect ratio can provide an interconnection through the rewiring layer. Moreover, one or more other semiconductor bases may be stacked on the front side.

An apparatus may include a microfluidic chip including at least one microfluidic channel and a first at least one electrical interconnect. An apparatus may include a circuit board having at least one interface interconnect and a second at least one electrical interconnect electrically coupled with the first at least one electrical interconnect of the microfluidic chip. An apparatus may include a cartridge enclosing the microfluidic chip and the circuit board, the cartridge including at least one opening allowing access to the at least one microfluidic channel on the microfluidic chip and the at least one interface interconnect.

A method for testing a packaging substrate with at least one electron beam column is described, wherein the packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; directing at least one electron beam of the at least one electron beam column on at least a first portion of the packaging substrate; directing the at least one electron beam of the at least one electron beam column on at least a second portion of the packaging substrate; detecting signal electrons emitted upon impingement of the at least one electron beam for testing a first device-to-device electrical interconnect path of the packaging substrate; and illuminating at least a third portion of the packaging substrate with UV radiation.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

A guided vehicle that includes a body having a first end, a second end opposite to the first end, a longitudinal axis defined between the first end and the second end, and a payload disposed inside of the body between the first end and the second end. The guided vehicle also includes a guidance kit that is configured to guide the guided vehicle, an adapter that mechanically connects the payload and the guidance kit with one another, and an electrical interconnection system that electrically connects the guidance kit and the payload with one another inside of the adapter. When the payload and the guidance kit are mechanically connected with one another and electrically connected with one another, the payload and the guidance kit are angularly aligned at a same clock position measured relative to the longitudinal axis or angularly displaced at different clock positions measured relative to the longitudinal axis.

An electrical interconnect system is described having an adapter mounted in an opening in a connector interface of a faceplate of an electronic enclosure. A sealing member can be used to prevent foreign matter, such as liquid, gas, or dust particles, from entering the enclosure and into a mating region between the adapter and a mating plug connector. The sealing member can include a base and a sidewall configured to surround an outer boundary of the adapter. The sealing member can be configured to form a first sealing interface with the faceplate and a second sealing interface with the plug connector. The first and second sealing interfaces can be orthogonal to each other. The sealing member can be made of an elastomeric material.

An integrated device includes one or more dies and a substrate. The substrate includes on-package contacts coupled to the one or more dies and off-package contacts configured to be coupled to a printed circuit board (PCB). The integrated device also includes a first set of electrical interconnects electrically coupled to a first subset of the off-package contacts and that form a ball grid array (BGA). The integrated device also includes a second set of electrical interconnects electrically coupled to a second subset of the off-package contacts and that form a land grid array (LGA).

A laser system comprises a femtosecond laser, and a beam delivery system configured to deliver and scan a laser beam emanating from the femtosecond laser onto wood, based on a desired graphene design, wherein graphene is formed on the wood by the laser beam. A device capable of being fabricated by the laser system may include a temperature sensor which detects a temperature by measuring resistance of the graphene, a heater or a boiler which converts electrical energy to thermal energy, or electrical interconnects.

An apparatus having at least one interconnect is provided. In one aspect, an apparatus includes a first media providing a first signal channel, a second media providing a second signal channel, and an interconnect. The interconnect includes a first mating structure that includes a first electrode mounted to the first media and a thin film dielectric disposed on the first electrode. The interconnect also includes a second mating structure having a second electrode mounted to the second media. The first mating structure is connectable with the second mating structure to connect the interconnect so that, when connected, the first electrode, the thin film dielectric, and the second electrode form a thin film capacitor between the first media and the second media and connect the first signal channel and the second signal channel to form a connected signal channel.

The invention relates to the technical field of wireless communication, and provides a silicon-based constant-temperature surface acoustic wave filter and a preparation method thereof, and the preparation method comprises the following steps: carrying out monocrystalline silicon ion implantation on a silicon substrate to respectively form an n-type thermocouple pair and a p-type thermocouple pair; manufacturing a dielectric layer; a thermocouple pair interconnection layer is manufactured, so that the n-type thermocouple pair and the p-type thermocouple pair are connected to form a path; manufacturing a passivation adhesion layer on the surface, far away from the silicon substrate, of the dielectric layer; manufacturing an acoustic layer on the surface, far away from the silicon substrate, of the passivation adhesion layer; windowing the acoustic layer to form a first groove and a second groove, and exposing the n-type thermocouple pair and the p-type thermocouple pair respectively; a first electrical interconnection layer and a second electrical interconnection layer are manufactured in the first groove and the second groove respectively, an interdigital structure is manufactured on the surface, away from the silicon substrate, of the acoustic layer, and the silicon-based constant-temperature surface acoustic wave filter is obtained. According to the silicon-based constant-temperature surface acoustic wave filter, the temperature stability and the power tolerance performance can be improved.

The application relates to the fields of microelectronic packaging and novel display technology, and discloses a packaging method suitable for a hybrid device packaging structure of a MicroLED, which comprises the following steps: preparing a wide-bandgap semiconductor driving chip, a logic control chip and a light-emitting pixel chip; transferring and fixing the wide-bandgap semiconductor driving chip, the logic control chip and the light-emitting pixel chip on the surface of a carrier plate in a coplanar mode; depositing a dielectric layer on the surface of the carrier plate to expose electrode contacts; manufacturing metal wires to build an internal electrical interconnection structure and lead out a peripheral interface; coating a packaging material on the surface of the carrier plate to insulate and coat the internal electrical interconnection structure; curing and cutting to separate an independent pixel packaging body; and assembling the pixel packaging body to a display panel substrate and connecting the peripheral interface to a global power supply network. The application suppresses the hot carrier effect under high-temperature working conditions, solves the problem of thermal failure, reduces the parasitic capacitance of high-frequency driving interconnection, removes potential failure products before macroscopic mounting, and improves the assembly yield of a display panel array.

A device, method, and hybrid computing architecture for a Symbolic Photonic Logic Gate (SPLG) system that performs data processing primarily in the optical domain. The system comprises a photonic substrate, including silicon-photonics, indium phosphide, or similar optically active materials, patterned with optical waveguides and interferometric structures configured to implement logic operations through controlled optical interference, phase modulation, or non-linear optical effects. The SPLG system is configured to execute Boolean and symbolic logic functions without requiring intermediate optical-to-electrical signal conversion. In operation, information is encoded into one or more optical parameters including phase, polarization, wavelength, or amplitude, and processed within a Symbolic Optical Core optimized for linear algebraic operations such as matrix multiplication and vector transformation. The architecture further comprises an electronic control layer configured to initialize, configure, and monitor the photonic logic elements while allowing the majority of computational operations to occur within the optical domain, thereby reducing electrical interconnect congestion and resistive heating relative to fully electronic processors.

This application discloses an inductor structure and its fabrication method, equipment, and dielectric. The inductor structure includes an inductor winding, a magnet, and a metal frame. The magnet encloses the inductor winding to form a cuboid inductor body. The metal frame covers the top and / or bottom of the cuboid inductor body and connects to the inductor winding terminals that are extended and bent to the top and / or bottom of the cuboid inductor body. By adding a metal frame to the inductor surface, an inductor structure with electrical interconnect design is achieved, which is compatible with mature molding inductor manufacturing methods and semiconductor processes. Advanced system-in-package (SIIP) requires higher dimensional accuracy than general inductor manufacturing capabilities, limiting the flexibility of package design. The electrode reconfiguration method provided by this invention can solve this accuracy mismatch and improve design flexibility.

The invention relates to the technical field of signal switching, in particular to a signal switching structure, and solves the problems that in the prior art, a signal switching and assembling structure of an AC / DC circuit board is complex in assembling process, and assembling consistency is difficult to guarantee. The AC power terminal and the DC power terminal are installed in the socket shell, the low-voltage connector is used for collecting and leading out temperature signals, a DC cavity and an AC cavity are formed in the socket shell, the side edges of the DC cavity and the side edges of the AC cavity are communicated, and a circuit board assembly is arranged in the socket shell; the circuit board assembly comprises an AC circuit board installed in the AC cavity and a DC circuit board installed in the DC cavity, and the AC circuit board and the DC circuit board are electrically interconnected and mechanically fixed through a plug-in. The integrated circuit board assembly has the advantages that the AC circuit board and the DC circuit board are connected and fixed in advance through the plug-in to form the integrated circuit board assembly, synchronous assembly of the AC circuit board and the DC circuit board is achieved through the integrated structure, the assembly process is simplified, and deviation accumulation caused by step-by-step assembly is avoided.

A semiconductor device includes a first row of doped wells formed in a semiconductor body, the first row including first conductivity type wells arranged alternatingly with second conductivity type wells in a first direction of the semiconductor body, first and second contact pads disposed over the upper surface of the semiconductor body, a primary electrical interconnect network that electrically couples semiconductor device structures formed by groups of the first conductivity type wells and the second conductivity type wells from the first row between the first and second contact pads, and a secondary electrical interconnect network that forms a node that is independent from the primary electrical interconnect network and electrically connects each of the first conductivity type wells in the first row together.

Direct-bonded optoelectronic interconnects for high-density integrated photonics are provided. A combined electrical and optical interconnect enables direct-bonding of fully-processed optoelectronic dies or wafers to wafers with optoelectronic driver circuitry. The photonic devices may be III-V semiconductor devices. Direct-bonding to silicon or silicon-on-insulator (SOI) wafers enables the integration of photonics with high-density CMOS and other microelectronics packages. Each bonding surface has an optical window to be coupled by direct-bonding. Coplanar electrical contacts lie to the outside, or may circumscribe the respective optical windows and are also direct-bonded across the interface using metal-to-metal direct-bonding, without interfering with the optical windows. Direct hybrid bonding can accomplish both optical and electrical bonding in one overall operation, to mass-produce mLED video displays. The adhesive-free dielectric-to-dielectric direct bonding and solder-free metal-to-metal direct bonding creates high-density electrical interconnects on the same bonding interface as the bonded optical interconnect. Known-good-dies may be used, which is not possible conventionally, and photolithography over their top surfaces can scale to high density.

A connection unit according to the invention for a drive system comprises a cuboid-shaped housing in which a positive conductor, having a positive input terminal and a positive output terminal, a negative conductor, having a negative input terminal and a negative output terminal, and an earth conductor, having an earth input terminal and an earth output terminal, are arranged; an outer insulating body for receiving a positive busbar and a negative busbar; and a mounting plate for attaching the housing to a mounting plate in a control cabinet. The outer insulating body is arranged on a front wall of the housing, and the mounting plate is arranged on a rear wall of the housing opposite the front wall.A drive system according to the invention comprises an electrical intermediate circuit to which a DC voltage is applied, at least one axis module which generates an AC voltage for an electric motor from the DC voltage of the intermediate circuit, and at least one connection unit according to the invention. The positive input terminal and the negative input terminal of the connection unit are connected to the intermediate circuit. The intermediate circuits of several rows of the drive system according to the invention in a control cabinet are electrically interconnectable.

A multi-chip package includes two electronic components bonded to each other via features on corresponding faces of the components that are directly opposite each other. The components are encapsulated in a volume of molding material that can include upper and lower sets of redistribution layers disposed on upper and lower surfaces of the volume of molding material that include electrical interconnects. The package includes one or more internal interconnects that pass through an aperture in the first electronic component to electrically couple an electrical contact on a surface of the package to the second electronic component.

The invention relates to a three-dimensional stacked microsystem for communication, navigation and electromagnetic spectrum monitoring application. The three-dimensional stacked microsystem comprises a high-density interconnection substrate; the plurality of functional core particles comprise radio frequency direct sampling core particles and digital baseband processing core particles; the at least one radio frequency channel micro module is arranged on the first side of the high-density interconnection substrate; area array vertical electrical interconnection among the radio frequency channel micro module, the functional core particles and the high-density interconnection substrate and among the functional core particles is realized through micro salient points. The internal structure of the microsystem does not comprise a lead bonding structure. According to the invention, a lead bonding process can be abandoned, a full-flip and wafer-level stacking technology is adopted, and the limitation of volume, weight and signal bandwidth is further broken through through a more optimized radio frequency direct acquisition layout and a full-silicon-based cavity structure, so that the urgent demand of a lightweight unmanned platform on a conduction, guidance and supervision integrated load is met; the system has the characteristics of high performance, miniaturization and low power consumption.

The invention relates to a liquid-helium-conduction-free cooling quantum resistance device carrying platform, and the carrying platform comprises a cold conduction column which is provided with a heat conduction thread at the outer edge of the bottom and is used for binding a cold conduction belt; the center of the bottom of the chip carrying table is fixedly connected with the top of the cold conduction column; the circuit board group comprises an interface circuit board, a first carrier plate, a second carrier plate, a third carrier plate and a fourth carrier plate which are stacked from top to bottom and are electrically connected with one another through gold-plated contact pins; the first carrier plate is fixed below the interface circuit board through an isolated interface, the second carrier plate and the third carrier plate are fixedly mounted on the upper side of the chip carrier, and the fourth carrier plate is fixedly connected below the third carrier plate; the resistor chip is fixed on the upper surface of the chip carrier and is electrically connected with the gold-plated patch on the surface of the second carrier through a bonding lead; and the gold-plated patch and the gold-plated pin form a path. The operation complexity is obviously reduced, long-term stable operation of the quantum resistor in a liquid-helium-free environment is realized, and the traceability precision of resistance value transmission is ensured.

Power Electrical Circuit This description relates to a power electrical circuit (100), comprising at least: - several power supply sources (102, 103); - an electrical interconnection bus (104) coupled to the power supply sources (102, 103); - switching devices (114–120) each comprising at least one thyristor (124, 128, 132, 136) and one field-effect transistor (122, 126, 130, 134) connected in parallel with each other, and configured to connect the power supply sources (102, 103) in series or in parallel. Figure for the abbreviation: Fig. 1

The invention discloses a board-level patch type liquid metal interconnection structure, and relates to the technical field of electronic packaging interconnection. The structure comprises a PDMS (Polydimethylsiloxane) elastic accommodating body, a gallium-based liquid metal core material, a symmetrical one-way valve, a copper pin header cap, a PCB (Printed Circuit Board) with a concave bonding pad, a chip and a crimping packaging shell. A cavity for containing liquid metal is formed in the PDMS elastic containing body, and symmetrical one-way valves are integrated at the two ends to achieve filling and zero-leakage sealing of the liquid metal. One end of the copper pin header cap is crimped with the elastic accommodating body, and the other end of the copper pin header cap is crimped with the concave bonding pad of the PCB to form a conductive path. The design concept of mechanical bonding and electrical interconnection decoupling is adopted, traditional rigid welding spots are replaced with liquid metal, vibration stress is dispersed through flexible buffering of the PDMS elastomer, and the problem that reliability of the traditional welding spots is insufficient due to stress concentration in the vibration environment is solved. The structure has the advantages of being low in contact resistance, excellent in vibration resistance, compatible with an existing SMT production line and the like, and is suitable for a board-level vertical interconnection packaging scene.

A method includes: providing an active photonic component of a photonic integrated circuit (PIC); attaching two electrodes to the active photonic component of the PIC; providing a first landing pad on a front surface of the PIC, wherein, when viewed from a direction perpendicular to the front surface of the PIC, a center of the active photonic component of the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 μm; and electrically connecting the first landing pad to one of the two electrodes.