908 results about "Electrical interconnect" patented technology

Metal films are deposited with uniform thickness and excellent step coverage. Copper metal films were deposited on heated substrates by the reaction of alternating doses of copper(I) NN′-diisopropylacetamidinate vapor and hydrogen gas. Cobalt metal films were deposited on heated substrates by the reaction of alternating doses of cobalt(II) bis(N,N′-diisopropylacetamidinate) vapor and hydrogen gas. Nitrides and oxides of these metals can be formed by replacing the hydrogen with ammonia or water vapor, respectively. The films have very uniform thickness and excellent step coverage in narrow holes. Suitable applications include electrical interconnects in microelectronics and magnetoresistant layers in magnetic information storage devices.

The present invention generally provides an apparatus and method for selectively forming a metallized feature, such as an electrical interconnect feature, on a electrically insulating surface of a substrate. The present invention also provides a method of forming a mechanically robust, adherent, oxidation resistant conductive layer selectively over either a defined pattern or as a conformal blanket film. Embodiments of the invention also generally provide a new chemistry, process, and apparatus to provide discrete or blanket electrochemically or electrolessly platable ruthenium or ruthenium dioxide containing adhesion and initiation layers. In general, aspects of the present invention can be used for flat panel display processing, semiconductor processing, solar cell device processing, or any other substrate processing, being particularly well suited for the application of stable adherent coating on glass as well as flexible plastic substrates. This invention may be especially useful for the formation of electrical interconnects on the surface of flat panel display or solar cell type substrates where the line sizes are generally larger than semiconductor devices or where the formed feature are not generally as dense.

A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, an exit through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, a bonding element forming a seal between the first and second substrates and forming a space between the first and second substrate, and a coolant channel formed in the space between the first and second substrates such that a fluid entering the entrance through-hole transits the coolant channel and the exit through-hole to provide cooling to the circuit element. The method supplies a fluid through the entrance through-hole, flows the fluid through the coolant channel between the first substrate and second substrates, and removes the fluid from the coolant channel through the exit through-hole.

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

A module comprises an electrical device having at least one memory device. A plurality of electrical contacts provide electrical signals to the electrical device. The memory apparatus also includes an optical interface, and an optical-to-electrical signal converter is coupled to receive optical signals from the optical interface and provide electrical signals to the electrical device.

A fabrication method and a product for the deposition of a conductive barrier or other liner layer in a vertical electrical interconnect structure. One embodiment includes within a a hole through a dielectric layer a barrier layer of RuTaN, an adhesion layer of RuTa, and a copper seed layer forming a liner for electroplating of copper. The ruthenium content is preferably greater than 50 at % and more preferably at least 80 at % but less than 95 at %. The barrier and adhesion layers may both be sputter deposited. Other platinum-group elements substitute for the ruthenium and other refractory metals substitute for the tantalum. Aluminum alloying into RuTa when annealed presents a moisture barrier. Copper contacts include different alloying fractions of RuTa to shift the work function to the doping type.

Methods of fabricating a Micro-Electromechanical System (MEMS) in a hermetically sealed cavity formed at a substrate level are provided. Generally, the method comprises: (i) forming a number of first open cavities in a surface of a first substrate and a number of second open cavities in a surface of a second substrate corresponding to the first open cavities; (ii) forming an actuator/sensor layer including a number of MEMS devices with electrically conductive regions therein; (iii) bonding the first substrate and the second substrate to the actuator/sensor layer so that at least one of the number of the first and second open cavities align with at least one of the number of MEMS devices to form a sealed cavity around the MEMS; and (iv) electrically connecting the electrically conductive regions of the MEMS device to a pad outside of the sealed cavity through an electrical interconnect. Other embodiments are also described.

An electrical interconnect apparatus has a mounting member with a plurality of sides. The mounting member is formed from an insulator as a cuboid. Moreover, the mounting member also may be formed from a flexible circuit. Among other things, the plurality of sides includes an interface side. At least two of the plurality of sides are in electrical communication with the interface side.

Compounds, and oligomers of the compounds, are synthesized with cyclic amine ligands attached to a metal atom. These compounds are useful for the synthesis of materials containing metals. Examples include pure metals, metal alloys, metal oxides, metal nitrides, metal phosphides, metal sulfides, metal selenides, metal tellurides, metal borides, metal carbides, metal silicides and metal germanides. Techniques for materials synthesis include vapor deposition (chemical vapor deposition and atomic layer deposition), liquid solution methods (sol-gel and precipitation) and solid-state pyrolysis. Suitable applications include electrical interconnects in microelectronics and magnetoresistant layers in magnetic information storage devices. The films have very uniform thickness and high step coverage in narrow holes.

A solar cell sub-module (100) for a photovoltaic device, including a plurality of elongate solar cells (slivers) (101) mounted in a structure that maintains the elongate solar cells in a longitudinally parallel and generally coplanar configuration, the structure providing one or more conductive pathways (201) electrically interconnecting the elongate solar cells (101). Also claimed are inventions related to releasing elongate substrate from a wafer frame; providing a plurality of mutually spaced elongate storage bins with a particular spacing; dispensing elongate solar cells into an alignment jig and attaching the cells to a substrate; engaging a length of electrical interconnect with an engagement tool having spaced engagement sections and applying a cutting tool; forming an electrical connection in a photovoltaic module with a conductor defining an indirect path between locations to compensate for thermal expansion; maintaining the solar cell orientation of sliver solar cells when releasing them from a wafer frame; engaging only opposing faces of elongate substrates, interconnected by a wafer frame, when releasing them; storing elongate substrate in a stacked configuration with a translation mechanism.

An electrical interconnection system with high speed, differential electrical connectors. The connector is assembled from wafers containing columns of conductive elements, some of which form differential pairs. Each column may include ground conductors adjacent pairs of signal conductors. The ground conductors may be wider than the signal conductors, with ground conductors between adjacent pairs of signal conductors being wider than ground conductors positioned at an end of at least some of the columns. Each of the conductive elements may end in a mating contact portion positioned to engage a complementary contact element in a mating connector. The mating contact portions of the signal conductors in some of the pairs may be rotated relative to the columns. The printed circuit board to which the differential signal connector is mounted may be constructed with elongated antipads around pairs of signal conductors.

The present invention provides electronic circuits, devices and device components including one or more stretchable components, such as stretchable electrical interconnects, electrodes and/or semiconductor components. Stretchability of some of the present systems is achieved via a materials level integration of stretchable metallic or semiconducting structures with soft, elastomeric materials in a configuration allowing for elastic deformations to occur in a repeatable and well-defined way. The stretchable device geometries and hard-soft materials integration approaches of the invention provide a combination of advance electronic function and compliant mechanics supporting a broad range of device applications including sensing, actuation, power storage and communications.

A modular connector assembly includes a modular frame having a first holes, second holes, and third holes formed at evenly spaced intervals. A plurality of modular interconnect components, fixable within the modular frame, have a back surface projection formed thereon. Each modular interconnect includes a contact housing made of electrically insulating material, an exterior of the contact housing comprising first and second side surfaces, a back surface, and a top surface. Contact signal pins are fixed within and electrically insulated from the contact housing.

An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

A method for forming an electrical interconnect on an integrated lead suspension or suspension component of the type formed from a laminated sheet of material having a stainless steel layer, a conductive lead layer and an insulating layer separating the stainless steel and conductive lead layers. An aperture is formed through at least the insulating layer to expose the stainless steel layer at an interconnect site. An interconnect mask is applied around the interconnect site. Conductive material is electroplated onto the stainless steel layer at the interconnect site to form a plated interconnect. The mask is then removed. The method is used to form an interconnect bond pad on the same side of the stainless steel layer as the conductive lead layer in one embodiment. In another embodiment the aperture is formed through the insulator layer and the stainless steel layer, and conductive material is built up on the stainless steel layer during the electroplating step until it meets and plates onto the conductive lead layer to form a stainless steel side interconnect. In yet another embodiment the aperture is formed through the insulator layer and the conductive lead layer, and conductive material is built up on the stainless steel layer during the electroplating step until it meets and plates onto the conductive lead layer to form a conductive lead side interconnect.

Disclosed is an electrical interconnect system using multiple grounding methods to reduce or prevent spurious signals from interfering with high density contacts carrying high speed transmissions. A first connector includes an insulative pillar partially surrounded by a plurality of signal contacts. A ground contact is at least partially located within the insulative pillar. A second connector includes a corresponding plurality of flexible signal contacts for mating with the signal contacts adjacent the insulative pillar. The second connector also includes a ground contact for receiving the ground contact of the first connector. The ground contacts provide a first method of providing a ground path to reduce spurious signals from entering the signal path. An electrically conducting shield is located outside the signal contacts when the first and the second connectors are mated. The first connector includes a member which provides a ground path between the first connector and the electrically conducting shield. Advantageously, the electrical interconnect system has two grounding methods which are particularly important in a high density electrical interconnect system where the contacts are closely spaced and susceptible to noise and other spurious signals.

An electrical interconnection system with high speed, differential electrical connectors. The connectors are formed with columns of conductive elements, some of which carry signals some of which act as ground conductors. The conductive elements may contain projections to secure the conductive elements in a housing or to facilitate desirable current flow patterns. To avoid impedance discontinuities caused by the projections, adjacent conductive elements may be formed with complementary portions to provide a relatively uniform edge-to-edge spacing between signal and ground conductors along the length of the signal conductor. To manufacture such a connector in which both the signal and the ground conductive elements contain projections, the conductive elements carrying signals may be inserted into a housing from one side and the conductive elements acting as ground conductors may be inserted from an opposite side.

An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening.

A method for assembling an electronic system with a plurality of layers. Recesses in formed in one or more dielectric layers and electronic components are positioned within the recesses. One or more layers containing the components are placed on a host substrate containing host circuits. Electrical interconnects are provided between and among the electronic components in the dielectric layers and the host circuits. The layers containing the components may also be provided by growing the electronic devices on a growth substrate. The growth substrate is then removed after the layer is attached to the host substrate.

Method and system for fabricating an electrical interconnect capable of supporting very high current densities (10⁶–10¹⁰ Amps/cm²), using an array of one or more carbon nanotubes (CNTs). The CNT array is grown in a selected spaced apart pattern, preferably with multi-wall CNTs, and a selected insulating material, such as SiO_w or Si_uN_v, is deposited using CVD to encapsulate each CNT in the array. An exposed surface of the insulating material is planarized to provide one or more exposed electrical contacts for one or more CNTs.

A printed circuit board for coupling surface mounted optoelectric semiconductor devices within a computer system is disclosed. The printed circuit board includes at least one substantially planar surface. There are multiple electrically conductive sites located on the substantially planar surface for connection to a surface mounted semiconductor electronic device. The electrically conductive sites are also connected to electrical interconnects embedded within the printed circuit board. In addition, there are multiple optical pathways terminated at the substantially planar surface for coupling a surface mounted semiconductor optoelectric device.

A disk drive electrical interconnect assembly and additive method therefor. The interconnect assembly has a supporting or fifth layer of metal, a fourth layer of a polyimide precursor or a polyimide with a first face directed away from the fifth layer, a third layer directly attached to the first face and defining a first subset of one or more conductive trace pair members, a second layer on the third and fourth layers of a polyimide precursor or a polyimide with a second face directed away from the third layer, and a first layer directly attached to the second layer and defining a second subset of one or more conductive trace pair members in spaced, paired and laterally offset relation respectively with one or more of the first subset pair members.