34 results about "Electrical interconnect" patented technology

The application relates to the fields of microelectronic packaging and novel display technology, and discloses a packaging method suitable for a hybrid device packaging structure of a MicroLED, which comprises the following steps: preparing a wide-bandgap semiconductor driving chip, a logic control chip and a light-emitting pixel chip; transferring and fixing the wide-bandgap semiconductor driving chip, the logic control chip and the light-emitting pixel chip on the surface of a carrier plate in a coplanar mode; depositing a dielectric layer on the surface of the carrier plate to expose electrode contacts; manufacturing metal wires to build an internal electrical interconnection structure and lead out a peripheral interface; coating a packaging material on the surface of the carrier plate to insulate and coat the internal electrical interconnection structure; curing and cutting to separate an independent pixel packaging body; and assembling the pixel packaging body to a display panel substrate and connecting the peripheral interface to a global power supply network. The application suppresses the hot carrier effect under high-temperature working conditions, solves the problem of thermal failure, reduces the parasitic capacitance of high-frequency driving interconnection, removes potential failure products before macroscopic mounting, and improves the assembly yield of a display panel array.

A device, method, and hybrid computing architecture for a Symbolic Photonic Logic Gate (SPLG) system that performs data processing primarily in the optical domain. The system comprises a photonic substrate, including silicon-photonics, indium phosphide, or similar optically active materials, patterned with optical waveguides and interferometric structures configured to implement logic operations through controlled optical interference, phase modulation, or non-linear optical effects. The SPLG system is configured to execute Boolean and symbolic logic functions without requiring intermediate optical-to-electrical signal conversion. In operation, information is encoded into one or more optical parameters including phase, polarization, wavelength, or amplitude, and processed within a Symbolic Optical Core optimized for linear algebraic operations such as matrix multiplication and vector transformation. The architecture further comprises an electronic control layer configured to initialize, configure, and monitor the photonic logic elements while allowing the majority of computational operations to occur within the optical domain, thereby reducing electrical interconnect congestion and resistive heating relative to fully electronic processors.

Power Electrical Circuit This description relates to a power electrical circuit (100), comprising at least: - several power supply sources (102, 103); - an electrical interconnection bus (104) coupled to the power supply sources (102, 103); - switching devices (114–120) each comprising at least one thyristor (124, 128, 132, 136) and one field-effect transistor (122, 126, 130, 134) connected in parallel with each other, and configured to connect the power supply sources (102, 103) in series or in parallel. Figure for the abbreviation: Fig. 1

This disclosure provides an apparatus for modulating light, the apparatus comprising a substrate having a plurality of electrical interconnects disposed on its top surface and an array of optical modulation elements disposed on the substrate. The optical modulation elements of the apparatus include an array of optical modulation elements, the array including a bottom electrode disposed on the substrate, wherein the bottom electrode is coupled to an electrical interconnect among the plurality of electrical interconnects, a bottom surface of a first dielectric layer is located above the bottom electrode, and a quantum well layer covering the top surface of the first dielectric layer. A second dielectric layer is then configured to cover the top surface of the quantum well layer, wherein each optical modulation element of the optical modulation element array is spatially separated from each of the other optical modulation elements of the array, and the top electrode is located on top of the optical modulation element array.

The application relates to a wafer-level injection molding method of a plastic through-hole packaging substrate and the plastic through-hole packaging substrate, and relates to the technical field of integrated circuit packaging. The method comprises the following steps: coating a polyimide (PI) layer on the upper surface of a carrier plate; preparing first wiring and scribe lane copper wires on the upper surface of the PI layer; preparing at least one copper column structure on the first wiring; obtaining a cutting structure; performing injection molding treatment on the cutting structure, so that the injection molding layer is flush with the surface of the copper column structure; preparing second wiring on the upper surface of the copper column structure, wherein the second wiring is a copper circuit; thinning the carrier plate and the PI layer in the cutting structure to expose the first wiring, so as to obtain the plastic through-hole packaging substrate after injection molding. Through flexible use of a scribing process, the wafer-level injection molding of a core-free TMV substrate is realized by combining a rewiring process, a wafer-level TMV process and an injection molding process. Compared with a traditional resin film pressing method, the interlayer bonding strength of the injection molding method is greatly improved, and higher-density electrical interconnection can be realized.

An electrical interconnection architecture for electrically connecting stacked square battery modules in various combinations of parallel and series configurations distributes heat sources (e.g., heat conduction through busbars, and internal resistance heating from short circuits) to multiple battery cells, rather than a single adjacent battery cell, reducing thermal skew propagation. Examples of the interconnection architecture include various combinations of interleaved bus and bypass bus configurations. A dual parallel module configuration can have two series submodules, with battery cells connected in an interleaved interconnection pattern. A bus connection pattern can allow negative inlet and positive outlet to be on the same end of the battery module. Battery cells can be interconnected such that parallel battery cells are not adjacent battery cells. Various combinations of resistors and fuses can also be used to reduce overheating from short circuits.

This utility model relates to the field of ceramic packaging technology and discloses a ceramic packaging internal and external electrical interconnection structure, including a ceramic substrate, a metal frame, a cover plate, a metal circuit layer, a chip, a metal through-hole, a U-shaped interconnect, an external lead, and an internal lead. The metal through-hole is disposed on the ceramic substrate, and the U-shaped interconnect passes through the metal through-hole. The chip is mounted on the metal circuit layer, and the chip and the metal circuit layer are located inside the metal frame. The metal frame is used to cover the chip and the metal circuit layer and is sealed by the cover plate. In this utility model, the U-shaped interconnect passes through the metal through-hole, and then the internal lead of the metal frame connects to one end of the U-shaped interconnect and the chip, while the other end of the U-shaped interconnect is powered through the external lead. This achieves the effect of internal and external electrical interconnection through the U-shaped structure, solving the problem of traditional ceramic packaging requiring external holes for wiring and improving the integrity of the ceramic packaging.

This invention provides a low-voltage fully integrated intelligent power module and an electronic device. The module includes: a metal frame; a first base island, a second base island, a third base island, and a fourth base island spaced apart along a first direction; the first and fourth base islands, and the second and third base islands spaced apart along a second direction; and terminals disposed on the outer periphery of each base island; a control unit and a low-voltage drive unit disposed on the first base island; a first and fourth low-voltage power transistor disposed on the second base island; a second and fifth low-voltage power transistor disposed on the third base island; and a third and sixth low-voltage power transistor disposed on the fourth base island; wherein each unit, each low-voltage power transistor, and each terminal are electrically interconnected; and a plastic encapsulation body, at least disposed on the metal frame, to encapsulate the control unit, the low-voltage drive unit, and each low-voltage power transistor. This invention solves the problems of high manufacturing difficulty, high cost, and low power density in existing modules.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

A compliant contact array for interconnecting conductive components in an electrical interconnect. The compliant contact array may include a plurality of features for contacting the conductive components. These and other features of the contact array may be relatively fine, such that contact arrays may make connections in a high density interconnection system or position metal to improve signal integrity, enabling high speed connectors. Further, features of the contact array may be shaped or positioned to provide desired mechanical properties such as a desired range of compliance and / or contact pressure. Features may control wall thickness of contact regions or enable telescoping or control the direction of flow of an elastomeric base region. The contact regions may be convex on one side and concave on another side. The compliant contact array may have a conductive layer applied thereon for electrically connecting the electrical connector to the conductive components.

Heat transfer couplers, which can also be referred to as nozzles, for semiconductor manufacturing are provided. The heat transfer couplers can include a cavity on a side that is opposite the side a semiconductor chip is attached to during an assembly process. In the assembly process, the semiconductor chip can be electrically coupled to a package substrate forming electrical interconnects. The assembly process can be a thermocompression bonding process in which first level interconnects are formed.

The invention relates to an electrical interconnector (19) for an electronic device such as an on-board vehicle charger, the electrical interconnector (19) comprising: a body (101) made of insulating material, in particular a plastic material, one or more electrical contact elements, in particular of the male or female type, arranged in said body (101) and configured to transmit electrical signals or power, at least one grounding tab (103), in particular metallic, integral with said body (101), said grounding tab (103) being configured to be, on the one hand, fixed, in particular soldered, to an electronic board, in particular in contact with a grounding trace of said electronic board, and, on the other hand, in contact with a conductive portion of a cover or metallic housing of the electronic device,ensuring ground continuity between the electronic board and the cover or housing. Figure for the abbreviation: Fig. 5,

The present invention discloses a method for fabricating a driver chip based on hybrid bonding and heterogeneous integration. First, a first wafer is provided, and multiple first chips, each containing a high-voltage analog driver circuit and / or a medium-voltage analog driver circuit, are fabricated on the first wafer using a first process node. Then, a second wafer is provided, and multiple second chips, each containing digital logic circuits and memory cells, are fabricated on the second wafer using a second process node. The first process node is a more mature process node than the second process node. Finally, the first and second wafers are bonded together using a wafer-level hybrid bonding process to form the driver chip, and electrical interconnects are formed at the bonding interface. This achieves an optimal combination of the high-voltage / medium-voltage driver portion and the logic / memory portion at different process nodes.

An electrical interconnect structure and its formation method, as well as a panel-level packaging structure, are disclosed. The electrical interconnect structure includes: several conductive structures, the surfaces of which have been roughened to form micro-pit structures; and a molding compound layer covering the sidewalls of the conductive structures. The roughened sidewalls of the conductive structures form micro-pit morphologies. This three-dimensional porous structure significantly increases the actual contact area between the conductive structures and the molding compound layer, enabling a tight mechanical bond at the interface of the two dissimilar materials. After the molding compound layer completely covers the roughened sidewalls of the conductive structures, the molding compound material is embedded within the micro-pit structures, generating a significant anchoring effect and effectively suppressing interface delamination. When the packaging structure experiences temperature changes or is subjected to external mechanical loads, the increased interfacial adhesion can uniformly disperse stress, preventing excessive stress concentration at the interface between the conductive structures and the molding compound layer, thereby preventing the generation and propagation of cracks and significantly improving the long-term reliability and failure resistance of the packaging structure.

A guided vehicle that includes a body having a first end, a second end opposite to the first end, a longitudinal axis defined between the first end and the second end, and a payload disposed inside of the body between the first end and the second end. The guided vehicle also includes a guidance kit that is configured to guide the guided vehicle, an adapter that mechanically connects the payload and the guidance kit with one another, and an electrical interconnection system that electrically connects the guidance kit and the payload with one another inside of the adapter. When the payload and the guidance kit are mechanically connected with one another and electrically connected with one another, the payload and the guidance kit are angularly aligned at a same clock position measured relative to the longitudinal axis or angularly displaced at different clock positions measured relative to the longitudinal axis.

This invention discloses a method for fabricating an interlayer heat dissipation structure integrated between stacked chips, belonging to the field of advanced packaging technology. The method includes: forming a first conductor and a first thermally conductive structure on a first surface of a first wafer to obtain a first chip wafer; forming a second thermally conductive structure, a redistribution layer, and a third conductor in a cavity shape on the surface of a first substrate layer of a second wafer to obtain a second chip wafer; aligning and bonding the first chip wafer and the second chip wafer in the chip stacking direction; wherein, the first and second thermally conductive structures are nested in a partially staggered manner to form staggered microchannels, and a portion of the third conductor is welded to the first conductor to form a flow channel sealing structure, thus obtaining the interlayer heat dissipation structure; and a portion of the third conductor and the first conductor are welded in a corresponding manner to form an interlayer electrical interconnect structure. This method can improve the integration of stacked chips, adjust for different heat dissipation requirements, and reduce the difficulty of the bonding process.

A piezoresistive transistor device includes a first transistor cell having a first piezoelectric material body and a first piezoresistive material body arranged in a stacked configuration. A first electrical resistance of the first piezoresistive material body is dependent upon a voltage applied across the first piezoelectric material body by way of a pressure applied by the first piezoelectric material body to the first piezoresistive material body. A second transistor cell includes a second piezoelectric material body and a second piezoresistive material body arranged in a stacked configuration. A second electrical resistance of the second piezoresistive material body is dependent upon a voltage applied across the second piezoelectric material body by way of a pressure applied by the second piezoelectric material body to the second piezoresistive material body. An internal electrical interconnect is configured to electrically connect the first electrical resistance and the second electrical resistance in series or in parallel.

A semiconductor structure includes a substrate, one or more electrical interconnects disposed in through-substrate vias extending vertically from an upper surface of the substrate to a lower surface of the substrate, one or more optical interconnects embedded in the substrate between the upper surface of the substrate and the lower surface of the substrate, and one or more optical connector pin holes extending from at least one side of the substrate between the upper surface of the substrate and the lower surface of the substrate.

A three-dimensional heterogeneous integrated (3DHI) package includes a plurality of electrically interconnected active layers stacked on one another, and a cooling block at a lower end of the active layers. Each of the active layers includes a semiconductor element, and at least one of the active layers includes an embedded heat spreader. The cooling block has a plurality of cooling channels formed therein, and the cooling channels do not extend through any of the active layers.

Techniques are provided for fabricating a flexible electrical interconnect. A methodology implementing the techniques according to an embodiment includes performing additive manufacturing to fabricate a chain comprising a plurality of link structures. Each link structure is shaped in a continuous and seamless loop and is coupled to at least one adjacent link structure such that a portion of each link structure traverses through an interior of the loop of the adjacent link structure. The method also includes coupling a first tensioner to a first of the link structures at a first end of the chain. The first tensioner is configured to electrically connect the first link structure to a circuit element. The method further includes coupling a second tensioner to a second of the link structures at a second end of the chain. The second tensioner is configured to electrically connect the second link structure to another circuit element.

A fabrication method for a photoelectric module is provided, comprising the following steps: A temporary substrate, a first lens, and a second lens are provided, with the first lens and the second lens embedded in the temporary substrate; a first photoelectric element is placed on the first lens; a second photoelectric element is placed on the second lens; an electrical interconnect structure is formed on the first and second photoelectric elements; the temporary substrate is removed to expose the first lens and the second lens.

A compliant contact array for interconnecting conductive components in an electrical interconnect. The compliant contact array may include a plurality of features for contacting the conductive components. These and other features of the contact array may be relatively fine, such that contact arrays may make connections in a high density interconnection system or position metal to improve signal integrity, enabling high speed connectors. Further, features of the contact array may be shaped or positioned to provide desired mechanical properties such as a desired range of compliance and / or contact pressure. Features may control wall thickness of contact regions or enable telescoping or control the direction of flow of an elastomeric base region. The contact regions may be convex on one side and concave on another side. The compliant contact array may have a conductive layer applied thereon for electrically connecting the electrical connector to the conductive components.

The present application relates to the alignment of the electrical interconnection structure of a radio frequency assembly, and in particular to a horizontal alignment device and method for the electrical interconnection structure of a tile radio frequency assembly, comprising a base for placing the component to be aligned, the base containing the component to be aligned through a positioning cavity, and a positioning plate arranged at the positioning cavity; the base is provided with a plurality of horizontal abutting components, a plurality of horizontal adjusting components, and a plurality of pressing components for pressing the component to be aligned. The base simulates the packaging box body, ensuring that the alignment between the cover plate of the tile component to be aligned and the upper substrate is consistent with the actual assembly state, and the alignment precision is high; during the horizontal alignment process, the operation logic is clear, and it is convenient to observe, and only three degrees of freedom are needed to complete the adjustment of X, Y and the rotation angle around the Z axis, and the efficiency is high; through the adjustment of the horizontal abutting component and the pressing component, the pressure acting on the upper substrate is controlled, and damage caused by the operation process is avoided.

Heat transfer couplers, which can also be referred to as nozzles, for semiconductor manufacturing are provided. The heat transfer couplers can include a cavity on a side that is opposite the side a semiconductor chip is attached to during an assembly process. In the assembly process, the semiconductor chip can be electrically coupled to a package substrate forming electrical interconnects. The assembly process can be a thermocompression bonding process in which first level interconnects are formed.

The application relates to the technical field of semiconductor packaging, and discloses a multi-chip parallel silicon carbide power module based on a copper clamp, in which a copper clamp connecting assembly is used to connect an upper bridge arm DBC substrate and a lower bridge arm DBC substrate in a multi-chip parallel silicon carbide power module body, and replaces traditional aluminum bonding wires, so that the electrical interconnection between the power source poles of silicon carbide power semiconductor chips and the upper surface metal regions of the DBC substrates is completed, the parasitic parameters of the interconnection parts are reduced, the reliability of the interconnection structure is improved, and an additional top heat dissipation path is added for the silicon carbide power semiconductor chips, so that the heat dissipation capacity of the silicon carbide power module is enhanced, the parasitic inductance of the power source poles of the parallel chips is balanced by adjusting the structural parameters of the copper clamp, and the uneven dynamic current distribution problem existing in the use of the multi-chip parallel silicon carbide power module is optimized in combination with the symmetry of the layout.

Heat transfer couplers, which can also be referred to as nozzles, for semiconductor manufacturing are provided. The heat transfer couplers include non-continuous channels on opposite faces. In an assembly process, semiconductor chips can be electrically coupled to a devices forming electrical interconnects. The assembly process can be a thermocompression bonding process in which first level interconnects are formed.

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

A rechargeable battery pack includes: a plurality of battery cells, each battery cell of the plurality of battery cells having a positive terminal and a negative terminal, an upper surface and a lower surface, the positive and negative terminals being arranged on a same side on the upper or lower surface or alternatively arranged on the upper and lower surface, the plurality of battery cells being arranged in a first direction and in a second direction, orthogonal to the first direction; a mechanical support structure for the battery cells; at least two printed circuit boards for electrical interconnection of the battery cells arranged on the upper surface or the lower surface, or both; and means of electrical interconnection by contact and without welding between the battery cells and the printed circuit boards allowing a connection of the battery cells in series and / or in parallel.

A kind of power module packaging structure based on embedded glass substrate.The present application relates to the field of power semiconductor device packaging technology, provide a kind of low parasitic parameter, high reliability and high interconnect density embedded power module packaging scheme.With multilayer stacked glass substrate as core carrier, including top plate, bottom plate and middle layer plate with cutout.Semiconductor chip is embedded in the cutout of middle layer plate, and the thickness of plate layer is adapted to the thickness of chip.The top surface of top plate has exposed pads, and the bottom surface of bottom plate has flat exposed copper layer.The surface of glass substrate is processed with rewiring layer, and is integrated with vertical via through glass substrate, to lead out the gate, source and drain of chip, to realize three-dimensional interconnection.The present application is different from mainstream embedded packaging, uses glass substrate to replace PCB organic substrate, makes full use of its low loss, high insulation, high thermal stability and the advantages such as more matched thermal expansion coefficient with SiC material.In addition, with the help of glass via glass via technology, smaller aperture and higher aspect ratio can be realized, which significantly improves the electrical interconnection density.

A monolithic substrate integrates compliant elastic springs formed from the substrate material and conductive structures extending across the springs to interconnect mounted components. The springs elastically deform under thermomechanical stress while maintaining electrical continuity of conductors composed of metal, alloy, or advanced conductive materials such as carbon nanotubes or graphene. Springs may be V-Beam or other flexural geometries produced in silicon for wafer-scale or glass for panel-scale substrates. The compliant-spring interconnect fabric enables wafer- or panel-scale electrical connectivity across large areas without fracture or delamination, supporting compute systems delivering up to or exceeding one zettaFLOPS per rack within practical power limits.