335 results about "Electrical interconnect" patented technology

A charging system comprises a local energy storage disposed at a charging site; an electric coupling configured to provide an electrical interconnect between the charging site and an electric vehicle (EV); and one or more controllers configured to: (i) detect a condition related to availability of electrical energy at the charging station, (ii) in response to the detecting of the condition: (a) estimate a number of EVs to which a charge remaining at the local energy storage is to be distributed within a certain time interval, (b) initiate a charging session for transferring electric energy from the local energy storage to the EV, via the electric coupling, and (c) limit an amount of electrical energy in the charging session in view of at least the estimated number of EVs.

An antenna apparatus includes an antenna substrate with opposite first and second surfaces; and a PCB having opposite first and second surfaces. Antenna elements are disposed at the first surface of the antenna substrate. Electrically conductive columns, each having a first end attached to the second surface of the PCB and a second end attached to the second surface of the antenna substrate, secure the PCB to the antenna substrate and provide an electrical interconnect between the PCB and the antenna substrate. RFIC chips are each attached to the second surface of the antenna substrate and are coupled to the antenna elements. At least one circuit element is attached to the first surface of the PCB and electrically coupled to at least one of the RFIC chips through at least one of the electrically conductive columns.

A method of fabricating a wearable and elastically stretchable thermoelectric generator or other thermoelectric device can involve arranging thermoelectric pellets and printing a thermal insulation material alongside and / or around the thermoelectric pellets to form a core layer. The core layer can be cured, and a liquid metal can be selectively deposited on the thermoelectric pellets to form contact points. Printing conductive ink can form stretchable electrical interconnects that define connections among the thermoelectric pellets via the contact points to form an initial middle layer that includes the stretchable electrical interconnects. Printing a thermal interface material may form an initial outer layer positioned between the initial outer layer and an initial side of the core layer to form a layered assembly. The layered assembly may be inverted and receive additional printed layers building away from the core layer, such as an additional interconnect layer and an additional thermal interface layer.

The invention relates to a three-dimensional stacked high-power multi-channel dual-polarization airtight packaging T / R assembly, which comprises a power supply modulation layer, a multifunctional processing layer and a power amplifier low-noise amplifier layer which are sequentially stacked from bottom to top, and electrical interconnection among the three circuit layers and with the outside is realized by adopting the BGA solder balls. The three circuit layers adopt LTCC (Low Temperature Co-Fired Ceramic) or HTCC (High Temperature Coefficient Chip) to realize an integrated packaging structure with a cavity; the interior of the integrated structure is divided into a plurality of same independent cavities so as to accommodate circuits and structures of the channels; a signal transmission structure and a grounding through hole array are arranged in the cavity wall of the integrated structure, so that electrical interconnection, impedance matching and electromagnetic shielding inside and outside the package are realized; each cavity is sealed in an independent airtight mode through a metal cover plate. When necessary, a wave-absorbing material is added in the cavity to prevent self-excitation of the assembly. According to the invention, the product structure and the production process are simplified, the production efficiency, the packaging efficiency and the yield are improved, and the cost is reduced; the power capacity and the reliability of the product are improved, and the maintainability is good.

A package includes a bridging element (an OMIB), and first and second photonic paths, forming a bidirectional photonic path. The OMIB has first and second interconnect regions to connect with one or more dies. Third and fourth unidirectional photonic paths may couple between the first interconnect region and an optical interface (OI). A photonic transceiver has a first portion in the OMIB and a second portion in one of the dies. The first and the second portions may be coupled via an electrical interconnect less than 2 mm in length. The die includes compute elements around a central region, proximate to the second portion. The OMIB may include an electro-absorption modulator fabricated with germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), or a III-V material based on gallium arsenide (GaAs). The OMIB may include a temperature compensation for the modulator.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

Various embodiments include an image sensor package for a camera with sensor shift actuation. The camera may include one or more actuators (e.g., a voice coil motor (VCM) actuator) for moving the image sensor package relative to a lens group of the camera. The image sensor package may include an image sensor and a substrate. The image sensor may be electrically connected to a ledge surface of a lower portion of the substrate, via one or more wire bond electrical interconnects.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

The embodiment of the invention discloses a chip packaging system and electronic equipment. The chip packaging system comprises a PCB, a local interconnection component and a plurality of core particles, the local interconnection component is arranged on a board of the PCB, and each core particle is electrically interconnected with the PCB; the local interconnection component comprises a dielectric layer and a high-density interconnection circuit layer which are arranged in a stacked mode, and at least two core particles are electrically interconnected through the local high-density interconnection circuit. Thus, the core particles and the local interconnection parts are installed on the PCB to form a chip board-level system, and the installability, reliability and supptability of the system are effectively improved while the high-density layout requirement is met. Meanwhile, on the basis of the structural characteristic that the core particles are installed on the surface of the PCB through the local interconnection components, link loss caused by conventional packaging can be reduced, and system cost can be reduced.

A package substrate includes a first dielectric layer, a second dielectric layer and a core layer. The first dielectric layer includes first electrical interconnect. The second dielectric layer includes second electrical interconnect. The core layer is situated between the first dielectric layer and the second dielectric layer, and includes a plurality of semiconductor dies stacked one above another between the first dielectric layer and the second dielectric layer. A first semiconductor die of the semiconductor dies is a capacitor die electrically connected to the first electrical interconnect of the first dielectric layer.

The present disclosure relates to implantable medical devices having protective structures with integrated electrical interconnects. Particularly, aspects of the present disclosure are directed to a medical device that includes a first nest portion and a second nest portion mateable with the first nest portion to form a nest housing. The nest housing includes an interior surface and an exterior surface with a component cavity defined by the interior surface. An electronics module is disposed within a first region of the component cavity. A power source is disposed within a second region of the component cavity. An electrical interconnect is formed on or embedded within the first nest portion, the second nest portion, or a combination thereof. The electrical interconnect electrically connects the electronics module to the power source.

A conformable piezoelectric transducer array for performing ultrasound or the like includes a silicone elastomer substrate and a silicone elastomer superstrate. A plurality of piezoelectric transducer elements are disposed between the substrate and superstrate. A first electrical interconnect layer electrically interconnects a first surface of the transducer elements adjacent to the substrate and a second electrical interconnect layer electrically interconnecting a second surface of the transducer elements adjacent to the superstrate.

A method for testing a packaging substrate with at least one electron beam column is described, wherein the packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; directing at least one electron beam of the at least one electron beam column on at least a first portion of the packaging substrate; directing the at least one electron beam of the at least one electron beam column on at least a second portion of the packaging substrate; detecting signal electrons emitted upon impingement of the at least one electron beam for testing a first device-to-device electrical interconnect path of the packaging substrate; and illuminating at least a third portion of the packaging substrate with UV radiation.

The invention belongs to the field of microelectronic packaging, and discloses an integrated chip near-node diamond micro-channel heat dissipation packaging structure and a preparation method thereof.The integrated chip near-node diamond micro-channel heat dissipation packaging structure comprises an electrical interconnection structure, a 3D integrated chip and a heat dissipation module which are stacked in sequence, and the electrical interconnection structure is connected with the 3D integrated chip through a contact of the 3D integrated chip; the heat dissipation module comprises a heterogeneous bonding layer, a diamond substrate, a metal circuit layer and a copper-based diamond micro-channel layer which are stacked in sequence, and the heterogeneous bonding layer is in contact with one surface, close to the node side, of the 3D integrated chip; a micro-channel structure is arranged in the copper-based diamond micro-channel layer; and the micro-channel structure is filled with liquid metal. The heat dissipation module is arranged on the side, close to the node, of the 3D integrated chip, and based on the design of the high-heat-conductivity heat dissipation material and the heat dissipation structure in the heat dissipation module, the effect that the compatible heat dissipation efficiency of the 3D integrated chip is improved and the 3D integrated chip is convenient to use can be achieved by integrally manufacturing the micro-channel structure.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

The present invention relates to a TSV electrical interconnect structure having a high aspect ratio and method of manufacturing it. In the method, a backside via and a backside contact pad connected to the backside via are formed on a backside of the semiconductor base. A front-side via connected to the backside via is then formed in the front side of the semiconductor base, obtaining a TSV which electrically connects the front side and backside of the semiconductor base that has a thickness greater than or equal to 150 μm. The TSV has an aspect ratio higher than 20, which can meet the requirements of package-level matching. The TSV electrical interconnect structure having a high aspect ratio can be connected to a package substrate or a PCB board through the backside contact pad. A rewiring layer on the front side of the semiconductor base is connected to the front-side via, and the TSV electrical interconnect structure having a high aspect ratio can provide an interconnection through the rewiring layer. Moreover, one or more other semiconductor bases may be stacked on the front side.

An apparatus may include a microfluidic chip including at least one microfluidic channel and a first at least one electrical interconnect. An apparatus may include a circuit board having at least one interface interconnect and a second at least one electrical interconnect electrically coupled with the first at least one electrical interconnect of the microfluidic chip. An apparatus may include a cartridge enclosing the microfluidic chip and the circuit board, the cartridge including at least one opening allowing access to the at least one microfluidic channel on the microfluidic chip and the at least one interface interconnect.

A method for testing a packaging substrate with at least one electron beam column is described, wherein the packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; directing at least one electron beam of the at least one electron beam column on at least a first portion of the packaging substrate; directing the at least one electron beam of the at least one electron beam column on at least a second portion of the packaging substrate; detecting signal electrons emitted upon impingement of the at least one electron beam for testing a first device-to-device electrical interconnect path of the packaging substrate; and illuminating at least a third portion of the packaging substrate with UV radiation.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

Embodiments disclosed herein include an interconnect structure. In an embodiment, the interconnect structure is an apparatus that comprises a substrate with a well through a thickness of the substrate. In an embodiment, the substrate comprises a polymer foam. In an embodiment, a liquid metal is in the opening, and the liquid metal comprises voids.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

A guided vehicle that includes a body having a first end, a second end opposite to the first end, a longitudinal axis defined between the first end and the second end, and a payload disposed inside of the body between the first end and the second end. The guided vehicle also includes a guidance kit that is configured to guide the guided vehicle, an adapter that mechanically connects the payload and the guidance kit with one another, and an electrical interconnection system that electrically connects the guidance kit and the payload with one another inside of the adapter. When the payload and the guidance kit are mechanically connected with one another and electrically connected with one another, the payload and the guidance kit are angularly aligned at a same clock position measured relative to the longitudinal axis or angularly displaced at different clock positions measured relative to the longitudinal axis.

An electrical interconnect system is described having an adapter mounted in an opening in a connector interface of a faceplate of an electronic enclosure. A sealing member can be used to prevent foreign matter, such as liquid, gas, or dust particles, from entering the enclosure and into a mating region between the adapter and a mating plug connector. The sealing member can include a base and a sidewall configured to surround an outer boundary of the adapter. The sealing member can be configured to form a first sealing interface with the faceplate and a second sealing interface with the plug connector. The first and second sealing interfaces can be orthogonal to each other. The sealing member can be made of an elastomeric material.

The invention relates to the technical field of chip packaging, in particular to a packaging structure and method for multilayer wafer interconnection. Comprising a plurality of stacked wafers, the distribution of bonding pads on each wafer is the same, the bonding pads of the adjacent wafers are arranged in a staggered mode, through holes are formed in the wafers, one ends of the through holes are flush with the surface of the wafer on the outermost side, the other ends of the through holes fall on the bonding pads of the wafer on the innermost side, insulating layers are arranged in the through holes, and conductive columns are arranged in the insulating layers. And the bonding pads of the adjacent wafers are electrically connected through the conductive columns. Compared with the prior art, the bonding pads are exposed in a stepped mode through dislocation bonding, holes are uniformly filled after the insulating layers on the surfaces of the bonding pads are removed, and then electrical interconnection between wafers can be achieved. Unified via technology with efficient electrical interconnection is achieved. Therefore, the complicated steps of drilling, depositing and filling holes of multiple layers of wafers are avoided, the overall manufacturing process is simplified, and the production efficiency is remarkably improved.

An integrated device includes one or more dies and a substrate. The substrate includes on-package contacts coupled to the one or more dies and off-package contacts configured to be coupled to a printed circuit board (PCB). The integrated device also includes a first set of electrical interconnects electrically coupled to a first subset of the off-package contacts and that form a ball grid array (BGA). The integrated device also includes a second set of electrical interconnects electrically coupled to a second subset of the off-package contacts and that form a land grid array (LGA).

A laser system comprises a femtosecond laser, and a beam delivery system configured to deliver and scan a laser beam emanating from the femtosecond laser onto wood, based on a desired graphene design, wherein graphene is formed on the wood by the laser beam. A device capable of being fabricated by the laser system may include a temperature sensor which detects a temperature by measuring resistance of the graphene, a heater or a boiler which converts electrical energy to thermal energy, or electrical interconnects.

An apparatus having at least one interconnect is provided. In one aspect, an apparatus includes a first media providing a first signal channel, a second media providing a second signal channel, and an interconnect. The interconnect includes a first mating structure that includes a first electrode mounted to the first media and a thin film dielectric disposed on the first electrode. The interconnect also includes a second mating structure having a second electrode mounted to the second media. The first mating structure is connectable with the second mating structure to connect the interconnect so that, when connected, the first electrode, the thin film dielectric, and the second electrode form a thin film capacitor between the first media and the second media and connect the first signal channel and the second signal channel to form a connected signal channel.

The invention relates to the technical field of wireless communication, and provides a silicon-based constant-temperature surface acoustic wave filter and a preparation method thereof, and the preparation method comprises the following steps: carrying out monocrystalline silicon ion implantation on a silicon substrate to respectively form an n-type thermocouple pair and a p-type thermocouple pair; manufacturing a dielectric layer; a thermocouple pair interconnection layer is manufactured, so that the n-type thermocouple pair and the p-type thermocouple pair are connected to form a path; manufacturing a passivation adhesion layer on the surface, far away from the silicon substrate, of the dielectric layer; manufacturing an acoustic layer on the surface, far away from the silicon substrate, of the passivation adhesion layer; windowing the acoustic layer to form a first groove and a second groove, and exposing the n-type thermocouple pair and the p-type thermocouple pair respectively; a first electrical interconnection layer and a second electrical interconnection layer are manufactured in the first groove and the second groove respectively, an interdigital structure is manufactured on the surface, away from the silicon substrate, of the acoustic layer, and the silicon-based constant-temperature surface acoustic wave filter is obtained. According to the silicon-based constant-temperature surface acoustic wave filter, the temperature stability and the power tolerance performance can be improved.

The application relates to the fields of microelectronic packaging and novel display technology, and discloses a packaging method suitable for a hybrid device packaging structure of a MicroLED, which comprises the following steps: preparing a wide-bandgap semiconductor driving chip, a logic control chip and a light-emitting pixel chip; transferring and fixing the wide-bandgap semiconductor driving chip, the logic control chip and the light-emitting pixel chip on the surface of a carrier plate in a coplanar mode; depositing a dielectric layer on the surface of the carrier plate to expose electrode contacts; manufacturing metal wires to build an internal electrical interconnection structure and lead out a peripheral interface; coating a packaging material on the surface of the carrier plate to insulate and coat the internal electrical interconnection structure; curing and cutting to separate an independent pixel packaging body; and assembling the pixel packaging body to a display panel substrate and connecting the peripheral interface to a global power supply network. The application suppresses the hot carrier effect under high-temperature working conditions, solves the problem of thermal failure, reduces the parasitic capacitance of high-frequency driving interconnection, removes potential failure products before macroscopic mounting, and improves the assembly yield of a display panel array.