189 results about "Electrical interconnect" patented technology

An apparatus may include a microfluidic chip including at least one microfluidic channel and a first at least one electrical interconnect. An apparatus may include a circuit board having at least one interface interconnect and a second at least one electrical interconnect electrically coupled with the first at least one electrical interconnect of the microfluidic chip. An apparatus may include a cartridge enclosing the microfluidic chip and the circuit board, the cartridge including at least one opening allowing access to the at least one microfluidic channel on the microfluidic chip and the at least one interface interconnect.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

An electrical interconnect system is described having an adapter mounted in an opening in a connector interface of a faceplate of an electronic enclosure. A sealing member can be used to prevent foreign matter, such as liquid, gas, or dust particles, from entering the enclosure and into a mating region between the adapter and a mating plug connector. The sealing member can include a base and a sidewall configured to surround an outer boundary of the adapter. The sealing member can be configured to form a first sealing interface with the faceplate and a second sealing interface with the plug connector. The first and second sealing interfaces can be orthogonal to each other. The sealing member can be made of an elastomeric material.

An integrated device includes one or more dies and a substrate. The substrate includes on-package contacts coupled to the one or more dies and off-package contacts configured to be coupled to a printed circuit board (PCB). The integrated device also includes a first set of electrical interconnects electrically coupled to a first subset of the off-package contacts and that form a ball grid array (BGA). The integrated device also includes a second set of electrical interconnects electrically coupled to a second subset of the off-package contacts and that form a land grid array (LGA).

A laser system comprises a femtosecond laser, and a beam delivery system configured to deliver and scan a laser beam emanating from the femtosecond laser onto wood, based on a desired graphene design, wherein graphene is formed on the wood by the laser beam. A device capable of being fabricated by the laser system may include a temperature sensor which detects a temperature by measuring resistance of the graphene, a heater or a boiler which converts electrical energy to thermal energy, or electrical interconnects.

The application relates to the fields of microelectronic packaging and novel display technology, and discloses a packaging method suitable for a hybrid device packaging structure of a MicroLED, which comprises the following steps: preparing a wide-bandgap semiconductor driving chip, a logic control chip and a light-emitting pixel chip; transferring and fixing the wide-bandgap semiconductor driving chip, the logic control chip and the light-emitting pixel chip on the surface of a carrier plate in a coplanar mode; depositing a dielectric layer on the surface of the carrier plate to expose electrode contacts; manufacturing metal wires to build an internal electrical interconnection structure and lead out a peripheral interface; coating a packaging material on the surface of the carrier plate to insulate and coat the internal electrical interconnection structure; curing and cutting to separate an independent pixel packaging body; and assembling the pixel packaging body to a display panel substrate and connecting the peripheral interface to a global power supply network. The application suppresses the hot carrier effect under high-temperature working conditions, solves the problem of thermal failure, reduces the parasitic capacitance of high-frequency driving interconnection, removes potential failure products before macroscopic mounting, and improves the assembly yield of a display panel array.

A device, method, and hybrid computing architecture for a Symbolic Photonic Logic Gate (SPLG) system that performs data processing primarily in the optical domain. The system comprises a photonic substrate, including silicon-photonics, indium phosphide, or similar optically active materials, patterned with optical waveguides and interferometric structures configured to implement logic operations through controlled optical interference, phase modulation, or non-linear optical effects. The SPLG system is configured to execute Boolean and symbolic logic functions without requiring intermediate optical-to-electrical signal conversion. In operation, information is encoded into one or more optical parameters including phase, polarization, wavelength, or amplitude, and processed within a Symbolic Optical Core optimized for linear algebraic operations such as matrix multiplication and vector transformation. The architecture further comprises an electronic control layer configured to initialize, configure, and monitor the photonic logic elements while allowing the majority of computational operations to occur within the optical domain, thereby reducing electrical interconnect congestion and resistive heating relative to fully electronic processors.

This application discloses an inductor structure and its fabrication method, equipment, and dielectric. The inductor structure includes an inductor winding, a magnet, and a metal frame. The magnet encloses the inductor winding to form a cuboid inductor body. The metal frame covers the top and / or bottom of the cuboid inductor body and connects to the inductor winding terminals that are extended and bent to the top and / or bottom of the cuboid inductor body. By adding a metal frame to the inductor surface, an inductor structure with electrical interconnect design is achieved, which is compatible with mature molding inductor manufacturing methods and semiconductor processes. Advanced system-in-package (SIIP) requires higher dimensional accuracy than general inductor manufacturing capabilities, limiting the flexibility of package design. The electrode reconfiguration method provided by this invention can solve this accuracy mismatch and improve design flexibility.

The invention relates to the technical field of signal switching, in particular to a signal switching structure, and solves the problems that in the prior art, a signal switching and assembling structure of an AC / DC circuit board is complex in assembling process, and assembling consistency is difficult to guarantee. The AC power terminal and the DC power terminal are installed in the socket shell, the low-voltage connector is used for collecting and leading out temperature signals, a DC cavity and an AC cavity are formed in the socket shell, the side edges of the DC cavity and the side edges of the AC cavity are communicated, and a circuit board assembly is arranged in the socket shell; the circuit board assembly comprises an AC circuit board installed in the AC cavity and a DC circuit board installed in the DC cavity, and the AC circuit board and the DC circuit board are electrically interconnected and mechanically fixed through a plug-in. The integrated circuit board assembly has the advantages that the AC circuit board and the DC circuit board are connected and fixed in advance through the plug-in to form the integrated circuit board assembly, synchronous assembly of the AC circuit board and the DC circuit board is achieved through the integrated structure, the assembly process is simplified, and deviation accumulation caused by step-by-step assembly is avoided.

A semiconductor device includes a first row of doped wells formed in a semiconductor body, the first row including first conductivity type wells arranged alternatingly with second conductivity type wells in a first direction of the semiconductor body, first and second contact pads disposed over the upper surface of the semiconductor body, a primary electrical interconnect network that electrically couples semiconductor device structures formed by groups of the first conductivity type wells and the second conductivity type wells from the first row between the first and second contact pads, and a secondary electrical interconnect network that forms a node that is independent from the primary electrical interconnect network and electrically connects each of the first conductivity type wells in the first row together.

Direct-bonded optoelectronic interconnects for high-density integrated photonics are provided. A combined electrical and optical interconnect enables direct-bonding of fully-processed optoelectronic dies or wafers to wafers with optoelectronic driver circuitry. The photonic devices may be III-V semiconductor devices. Direct-bonding to silicon or silicon-on-insulator (SOI) wafers enables the integration of photonics with high-density CMOS and other microelectronics packages. Each bonding surface has an optical window to be coupled by direct-bonding. Coplanar electrical contacts lie to the outside, or may circumscribe the respective optical windows and are also direct-bonded across the interface using metal-to-metal direct-bonding, without interfering with the optical windows. Direct hybrid bonding can accomplish both optical and electrical bonding in one overall operation, to mass-produce mLED video displays. The adhesive-free dielectric-to-dielectric direct bonding and solder-free metal-to-metal direct bonding creates high-density electrical interconnects on the same bonding interface as the bonded optical interconnect. Known-good-dies may be used, which is not possible conventionally, and photolithography over their top surfaces can scale to high density.

A multi-chip package includes two electronic components bonded to each other via features on corresponding faces of the components that are directly opposite each other. The components are encapsulated in a volume of molding material that can include upper and lower sets of redistribution layers disposed on upper and lower surfaces of the volume of molding material that include electrical interconnects. The package includes one or more internal interconnects that pass through an aperture in the first electronic component to electrically couple an electrical contact on a surface of the package to the second electronic component.

The invention relates to a three-dimensional stacked microsystem for communication, navigation and electromagnetic spectrum monitoring application. The three-dimensional stacked microsystem comprises a high-density interconnection substrate; the plurality of functional core particles comprise radio frequency direct sampling core particles and digital baseband processing core particles; the at least one radio frequency channel micro module is arranged on the first side of the high-density interconnection substrate; area array vertical electrical interconnection among the radio frequency channel micro module, the functional core particles and the high-density interconnection substrate and among the functional core particles is realized through micro salient points. The internal structure of the microsystem does not comprise a lead bonding structure. According to the invention, a lead bonding process can be abandoned, a full-flip and wafer-level stacking technology is adopted, and the limitation of volume, weight and signal bandwidth is further broken through through a more optimized radio frequency direct acquisition layout and a full-silicon-based cavity structure, so that the urgent demand of a lightweight unmanned platform on a conduction, guidance and supervision integrated load is met; the system has the characteristics of high performance, miniaturization and low power consumption.

Power Electrical Circuit This description relates to a power electrical circuit (100), comprising at least: - several power supply sources (102, 103); - an electrical interconnection bus (104) coupled to the power supply sources (102, 103); - switching devices (114–120) each comprising at least one thyristor (124, 128, 132, 136) and one field-effect transistor (122, 126, 130, 134) connected in parallel with each other, and configured to connect the power supply sources (102, 103) in series or in parallel. Figure for the abbreviation: Fig. 1

The invention discloses a board-level patch type liquid metal interconnection structure, and relates to the technical field of electronic packaging interconnection. The structure comprises a PDMS (Polydimethylsiloxane) elastic accommodating body, a gallium-based liquid metal core material, a symmetrical one-way valve, a copper pin header cap, a PCB (Printed Circuit Board) with a concave bonding pad, a chip and a crimping packaging shell. A cavity for containing liquid metal is formed in the PDMS elastic containing body, and symmetrical one-way valves are integrated at the two ends to achieve filling and zero-leakage sealing of the liquid metal. One end of the copper pin header cap is crimped with the elastic accommodating body, and the other end of the copper pin header cap is crimped with the concave bonding pad of the PCB to form a conductive path. The design concept of mechanical bonding and electrical interconnection decoupling is adopted, traditional rigid welding spots are replaced with liquid metal, vibration stress is dispersed through flexible buffering of the PDMS elastomer, and the problem that reliability of the traditional welding spots is insufficient due to stress concentration in the vibration environment is solved. The structure has the advantages of being low in contact resistance, excellent in vibration resistance, compatible with an existing SMT production line and the like, and is suitable for a board-level vertical interconnection packaging scene.

A method includes: providing an active photonic component of a photonic integrated circuit (PIC); attaching two electrodes to the active photonic component of the PIC; providing a first landing pad on a front surface of the PIC, wherein, when viewed from a direction perpendicular to the front surface of the PIC, a center of the active photonic component of the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 μm; and electrically connecting the first landing pad to one of the two electrodes.

In one aspect, the present disclosure relates to an electronic device comprising: a plurality of electronic chip components; a plurality of liquid metal (LM) electrical interconnects coupled to the plurality of electronic chips; and a polyimine film encapsulating the plurality of electronic chip components and the plurality of LM electrical interconnects. In some embodiments, the polyimine film comprises the product of the polymerization reaction between terephthaldehyde, 3,3diamino-N-methyldipropylamine, and tris(2-aminoethyl)amine. In another aspect, the present disclosure relates to a method for manufacturing an electronic device, the method comprising: disposing a volume of LM on a polyimine substrate to form a plurality of electrical interconnects; disposing a plurality of electronic chip components onto the polyimine substrate and in contact with the plurality of electrical interconnects; and applying a layer of polyimine onto the polyimine substrate, the plurality of electrical interconnects, and the plurality of electronic chip components.

An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancement structure disposed on the bonding surface and including a plurality of raised spokes each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to liquefied solder material than the bonding surface. Each of the raised spokes extends radially outward from a center of the solder enhancement structure.

We provide an interactive educational kiosk system configured as a physically integrated teaching device. [Solution] The interactive educational kiosk system 100 according to the present invention is configured as an autonomous educational device that generates real-time educational output by physically converting learner operations into electrical response signals, adjusting, synchronizing, and evaluating those signals, and then routing them through electrically forced conduction paths. The interactive educational kiosk system 100 consists of a user interaction unit 104, a signal adjustment unit 106, a control processing unit 108, a reference comparison unit 110, a routing / output unit 112, a content presentation unit 114, and a learner monitoring unit 116, all housed in a kiosk enclosure 102, all of which are electrically interconnected via fixed conduction paths and power distribution rails.

The invention relates to the technical field of microelectronic devices and intelligent sensing, and discloses a neuromorphic gas sensor based on ionic gel and a memristor and a preparation method. The sensor comprises a substrate, a Mott memristor and an ionic gel capacitive gas sensing unit, wherein the Mott memristor and the ionic gel capacitive gas sensing unit are integrated on the substrate, and the Mott memristor and the ionic gel capacitive gas sensing unit are electrically interconnected through on-chip heterogeneous integration to form an oscillation circuit. The adsorption response characteristic of the ionic gel interface double-electrode layer capacitor to gas molecules is utilized to modulate the charging and discharging period of the Mott memristor, so that the gas concentration information is converted into the frequency of the output pulse signal. The gas sensing and encoding integrated function is achieved, the gas sensing and encoding integrated device has the advantages of working at the room temperature, being compact in structure, low in power consumption and compatible with the CMOS technology, and a device basis is provided for constructing an efficient gas sensing front end suitable for a brain-like intelligent sensing system.

The present disclosure is and includes at least one apparatus, system, and method for a ramped electrical interconnect for use in semiconductor manufacturing. The apparatus, system, and method include: at least one first semiconductor substrate having a first circuit including first electrical components thereon; a second semiconductor substrate at least partially covering the first circuit and having a second circuit including second electrical components thereon; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

This disclosure provides an apparatus for modulating light, the apparatus comprising a substrate having a plurality of electrical interconnects disposed on its top surface and an array of optical modulation elements disposed on the substrate. The optical modulation elements of the apparatus include an array of optical modulation elements, the array including a bottom electrode disposed on the substrate, wherein the bottom electrode is coupled to an electrical interconnect among the plurality of electrical interconnects, a bottom surface of a first dielectric layer is located above the bottom electrode, and a quantum well layer covering the top surface of the first dielectric layer. A second dielectric layer is then configured to cover the top surface of the quantum well layer, wherein each optical modulation element of the optical modulation element array is spatially separated from each of the other optical modulation elements of the array, and the top electrode is located on top of the optical modulation element array.

The electronic assembly includes a host wafer having a first circuit including passive devices for one of a tuning or matching network. Chiplets are disposed in the cavity. At least one chiplet has a second circuit including at least one transistor or switch device and a passive tuning circuit including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network. Electrical interconnects between the chiplet and the wafer electrically connect the first circuit to the second circuit.

A multi-chip package includes two electronic components bonded to each other via electrical contacts on corresponding faces of the components that are directly opposite each other. The components are encapsulated in a volume of molding material that includes a upper and lower sets of redistribution layers disposed on upper and lower surfaces of the volume of molding material that include electrical interconnects. The package includes one or more through-package interconnects that pass through the molding material. A first through-package interconnect couples an electrically conductive interconnect in a first redistribution layer to an electrically conductive interconnect in a second redistribution layer on an opposite side of the volume of molding material from the first redistribution layer, or it couples the interconnect to one of the components within the volume of molding material.

An integrated circuit comprises a plurality of child circuit modules in which each child circuit module has a base configuration that is common to each of the plurality of child circuit modules. The base configuration includes: a semiconductor logic component, one or more auxiliary circuit components, and one or more signal driver components. The integrated circuit further comprises a parent circuit module overlaying the plurality of child circuit modules. The parent circuit module includes a plurality of electrical interconnects. For each child circuit module, an electrical interconnect provides an electrical connection to the semiconductor logic component. For a first subset of the child circuit modules, an electrical interconnect provides an electrical connection to the auxiliary circuit component, and for a second subset of the child circuit modules, an electric interconnect provides an electrical connection between a signal driver component and the auxiliary circuit component of that child circuit module.

Camera systems having integrated light sources are described. The camera system may include a printed circuit board, a camera module, a bracket, a first light source, and a set of electrical interconnects. The printed circuit board has a flexible portion and a rigid portion. The camera module is mounted to the rigid portion of the printed circuit board and includes a lens barrel. The first light source is mounted to a top surface of the bracket. The set of electrical interconnects are between the rigid portion of the printed circuit board and the bracket. The bracket at least partially surrounds the lens barrel. The bracket is mounted to at least the rigid portion of the printed circuit board. The first light source is electrically connected to the printed circuit board via the set of electrical interconnects.

An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a wafer, and the chiplets have interconnections to wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The wafer has at least one wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the wafer circuit to the chiplet circuit.

The application relates to a wafer-level injection molding method of a plastic through-hole packaging substrate and the plastic through-hole packaging substrate, and relates to the technical field of integrated circuit packaging. The method comprises the following steps: coating a polyimide (PI) layer on the upper surface of a carrier plate; preparing first wiring and scribe lane copper wires on the upper surface of the PI layer; preparing at least one copper column structure on the first wiring; obtaining a cutting structure; performing injection molding treatment on the cutting structure, so that the injection molding layer is flush with the surface of the copper column structure; preparing second wiring on the upper surface of the copper column structure, wherein the second wiring is a copper circuit; thinning the carrier plate and the PI layer in the cutting structure to expose the first wiring, so as to obtain the plastic through-hole packaging substrate after injection molding. Through flexible use of a scribing process, the wafer-level injection molding of a core-free TMV substrate is realized by combining a rewiring process, a wafer-level TMV process and an injection molding process. Compared with a traditional resin film pressing method, the interlayer bonding strength of the injection molding method is greatly improved, and higher-density electrical interconnection can be realized.

An electrical interconnection architecture for electrically connecting stacked square battery modules in various combinations of parallel and series configurations distributes heat sources (e.g., heat conduction through busbars, and internal resistance heating from short circuits) to multiple battery cells, rather than a single adjacent battery cell, reducing thermal skew propagation. Examples of the interconnection architecture include various combinations of interleaved bus and bypass bus configurations. A dual parallel module configuration can have two series submodules, with battery cells connected in an interleaved interconnection pattern. A bus connection pattern can allow negative inlet and positive outlet to be on the same end of the battery module. Battery cells can be interconnected such that parallel battery cells are not adjacent battery cells. Various combinations of resistors and fuses can also be used to reduce overheating from short circuits.

This utility model relates to the field of ceramic packaging technology and discloses a ceramic packaging internal and external electrical interconnection structure, including a ceramic substrate, a metal frame, a cover plate, a metal circuit layer, a chip, a metal through-hole, a U-shaped interconnect, an external lead, and an internal lead. The metal through-hole is disposed on the ceramic substrate, and the U-shaped interconnect passes through the metal through-hole. The chip is mounted on the metal circuit layer, and the chip and the metal circuit layer are located inside the metal frame. The metal frame is used to cover the chip and the metal circuit layer and is sealed by the cover plate. In this utility model, the U-shaped interconnect passes through the metal through-hole, and then the internal lead of the metal frame connects to one end of the U-shaped interconnect and the chip, while the other end of the U-shaped interconnect is powered through the external lead. This achieves the effect of internal and external electrical interconnection through the U-shaped structure, solving the problem of traditional ceramic packaging requiring external holes for wiring and improving the integrity of the ceramic packaging.