Wafer-level chip scale package and method for fabricating and using the same

Abstract

A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e.,interface) to the printed circuit board for any small die.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a continuation-in-part of U.S. patent application Ser. No. 10 / 731,453, which is a continuation-in-part of U.S. patent application Ser. No. 10 / 618,113, which is a continuation-in-part of U.S. patent application Ser. No. 10 / 295,281, which claims priority of Korean Patent Application No. KR 01-71043, the entire disclosures of which are incorporated herein by reference.FIELD OF THE INVENTION [0002] The invention generally relates to methods for fabricating integrated circuits (ICs) and semiconductor devices and the resulting structures. Specifically, the invention relates to semiconductor packages and methods for fabricating and using such packages. More particularly, the invention relates to wafer level chip scale packages and methods for fabricating and methods for using such packages. BACKGROUND OF THE INVENTION [0003] Recent advancements in the electronics industry, especially with personal computers (PC), mobile phon...

AI Technical Summary

Benefits of technology

[0013] The invention provides a packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e.,interface) to the printed circuit board for any small die.

Problems solved by technology

The increasing complexity of the circuitry in the IC has required the conductive pads to be formed closer together.

With the bond pads narrower, the length of the wire (in the wire bonding) needs to be longer and width narrower which unfortunately induces a greater amount of inductance and thereby reduces the speed of the circuitry.

In these areas, short circuits can occur and the pattern 20 can crack and deform in these areas due to stresses.

Thus, there is a higher possibility that moisture penetrates into the solder connection 52 and decreases the reliability of the solder connection 52.

Fourth, the package 50 is completed only by carrying out many processing steps and, therefore, manufacturing costs are high.

Accordingly, the package 60 is not easy to manufacture.

Other problems exist with conventional WLSCP.

Such structures are complicated to manufacture and very expensive because of materials and equipment used.

As well, the coefficient of thermal expansion (CTE) between the various layers can induce thermal stresses into the ICs and damage the ICs during high temperature curing of these polymeric materials.

Such methods, however, suffer from a high cost and poor reliability.

The use of smaller form factors in a WL-CSP packaging with small die and large I / O, however, could result in manufacturing challenges.

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