477 results about "Page buffers" patented technology

A method of operating a semiconductor device includes performing a pre-sensing operation on selected memory cells; and performing a main sensing operation on the selected memory cells. The performing of the main sensing operation includes selectively precharging first sensing nodes of a plurality of page buffers respectively corresponding to the selected memory cells, based on a result of the pre-sensing operation.

Storage devices and methods are disclosed. In an embodiment, a storage device may include a memory device including a plurality of memory units configured to store data and a plurality of page buffers coupled to the plurality of memory units, respectively, a volatile memory configured to store write data requested by a host, a power control device configured to control power supply to the memory device and the volatile memory and a processing circuit configured to control the memory device based on a command transmitted from the host. The processing circuit backs up the write data to a first page buffer among the plurality of page buffers in response to a low power mode entry command transmitted from the host. The power control device cuts off power supply to the volatile memory after the write data is backed up in the first page buffer.

In one aspect, a page buffer includes a first latch configured to store program verification information; a second latch configured to store first bit line forced information; and a dynamic latch configured to store second bit line forced information. The first bit line forced information is different from the second bit line forced information. The dynamic latch includes a control switch coupled to the second latch. And the dynamic latch is configured to store information through a capacitor to which the control switch is coupled.

There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern.

A three-dimensional semiconductor device includes a peripheral circuit device layer that includes a page buffer area, a pass transistor area adjacent to the page buffer layer, and a logic transistor area adjacent to the pass transistor area in the first direction, and a memory cell device layer that includes a cell area and a staircase area extending from the cell area. The peripheral circuit device layer includes transistors, peripheral circuit via plugs, and peripheral circuit interconnection layers on a substrate. The memory cell device layer includes word line stack including interlayer insulating layers and word lines alternately stacked, the word line stack including end portions stacked in a staircase in the staircase area; a bit line array including bit lines arranged in the cell area; and word line pillars electrically connected to the end portions of the word lines in the staircase area, respectively.

A memory device includes a memory cell array configured to store data, a page buffer circuit configured to store data in the memory cell array or read data stored in the memory cell array, and a scan register circuit configured to receive a pass / fail result of data from the page buffer circuit and store the pass / fail result in a plurality of scan registers. The scan register circuit obtains information about the scan register where the fail result is stored through a scan operation, and uses the information about the scan register where the fail result is stored to determine the number of fail bits and / or a position index indicating the position of the fail bits according to the operation mode.

A memory device includes a memory cell array, a page buffer circuit including first to Nth page buffers, each page buffer including a sensing node, and a control logic configured to control page buffer operations, wherein the control logic is further configured to control the page buffer operations such that, in a first page buffer operation on a first page buffer included in a first group, a precharge period and a discharge period for a first sensing node of the first page buffer are performed, in a fifth page buffer operation on a fifth page buffer included in a second group, a precharge period and a discharge period for a fifth sensing node of the fifth page buffer are performed, and in a sensing period of the fifth page buffer operation, sensing operations on the first and fifth sensing nodes are performed together.

A memory device includes a memory array having memory cells, a page buffer coupled to the memory array through bit lines and including a latch, and a control logic coupled to the page buffer. The control logic is configured to perform a first read operation on the memory cells, and perform a second read operation on the memory cells by dividing the memory cells into a plurality of groups of memory cells, and performing a second read operation on the plurality of groups of memory cells based on a first set of develop times. Each of the first set of develop times is different. The control logic is also configured to perform a third read operation on the memory cells by performing a third read operation on the plurality of groups of memory cells based on a second set of develop times. Each of the second set of develop times is different. The control logic is further configured to determine a read develop time based on the third read operation.

An example page buffer circuit includes a plurality of page buffer circuits and a plurality of cache latches connected with the plurality of page buffer circuits through a combined sensing node. Each of the plurality of page buffer circuits includes a main latch connected with a corresponding sensing node. The main latch includes a first transistor connected with a corresponding sensing node and configured to be driven by a monitoring signal, a first latch circuit configured to latch data, and a second transistor connected with the first transistor and configured to be driven by a voltage level of a node latching data in the first latch circuit, and a parasitic capacitor corresponding to a parasitic capacitance caused by a junction of the first transistor and the second transistor is connected between the first transistor and the second transistor.

The invention provides a test method for a BIST system of a memory, and belongs to the field of integrated circuits. The test method comprises the following steps: a page buffer test step: a test machine sends a page buffer test command to a controller through a bus, and the controller controls a BIST circuit to test a page buffer and confirms whether the page buffer is damaged; a storage array test step: the test machine sends a storage array test command to the controller through the bus, and the controller controls the BIST circuit to test the storage array; a judgment step: judging whether the storage array is repairable or not by the BIST circuit; a temporary storage step: after the test is completed, the BIST circuit temporarily stores a test result in the page buffer; and a writing step: the controller sends the test result temporarily stored in the page buffer to a test machine through the bus, the test machine sends the test result to the controller through the bus, and the controller writes the test result into the one-time programmable memory. According to the test method, the occupied area of the chip can be reduced, and power consumption is reduced.

A memory device includes a memory cell array, a plurality of page buffer units connected to the memory cell array and connected in common to a combined sensing node, and a plurality of cache latches respectively corresponding to the plurality of page buffer units, the plurality of cache latches including a first cache latch and a second cache latch connected in common to the combined sensing node. In a first section of a data dumping operation on the first cache latch, first and second tri-state inverters included in the first cache latch are enabled to transmit data to the first cache latch, and third and fourth tri-state inverters included in the second cache latch are disabled. In a second section of the data dumping operation on the first cache latch, the third and fourth tri-state inverters are sequentially enabled to restore data previously stored in the second cache latch.

A semiconductor device may include a first memory cell array including a first source line, a first bit line, a first memory string, and first word lines; a second memory cell array including a second source line, a second bit line, a second memory string, and second word lines; a first interconnection structure including a first through via passing through the first memory cell array and commonly connected to the first bit line and the second bit line; a second interconnection structure including a second through via passing through the first memory cell array and commonly connected to the first word line and the second word line; a page buffer selectively accessing the first memory string or the second memory string through the first interconnection structure; and a row decoder commonly controlling the first word line and the second word line through the second interconnection structure.

A semiconductor device includes a first substrate structure including a first decoder circuit region, a second decoder circuit region, and a page buffer circuit region, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a first cell structure that includes first horizontally extending gate electrodes, and a second cell structure that includes second horizontally extending gate electrodes. The second cell structure is disposed below the first cell structure. A first stair structure is disposed to one side of the first and second cell structures, and a second stair structure is disposed to a second side opposite the first side. a dummy structure is disposed below the first stair structure. First contact plugs pass through the first stair structure and the first dummy structure and are respectively connected to the first gate electrodes, and second contact plugs pass through the second stair structure and are respectively connected to the second gate electrodes.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engines is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address, The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.

A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected to the plurality of memory cells via a plurality of bit lines, and a plurality of cache latches respectively corresponding to the plurality of page buffer units. Each of the plurality of page buffer units includes a pass transistor that is connected to a corresponding sensing node and is driven according to a pass control signal, and the memory device is configured such that in a data sensing period, a sensing node of a selected page buffer unit among the plurality of page buffer units is actively connected to a sensing node of an unselected page buffer unit among the plurality of page buffer units.

Examples of the present application relate to the field of semiconductors, and disclose a page buffer and an operation method thereof, a memory device and a memory system. The page buffer includes latch circuits, wherein the latch circuits includes: a latch control configuration circuit connected with a first data node and a second data node, and configure the first data node and the second data node to different logic levels respectively in response to a configuration signal, wherein a logic level of the first data node is opposite to a logic level of the second data node; and a latch transmission circuit connected with the first data node, the second data node, and a sense node, and configured to: couple the second data node with the sense node in response to a transmission signal, to transmit a configuration result of the latch control configuration circuit to the sense node.

A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected with the memory cells through a plurality of bit lines. A sensing node is connected to a bit line for each buffer circuit. The plurality of page buffer units are respectively connected with sensing nodes, each of the plurality of page buffer units includes at least one transistor. One or more auxiliary wires in the proximity of the sensing node are used to reduce coupling problems caused by a low capacitance of the sensing node.

A method, computer program product, and computing system for generating a plurality of page buffers from a log memory system of the storage system using a persistent memory organization policy. A plurality of physical layer blocks (PLBs) are generated from the log memory system using the persistent memory organization policy. A set of page buffers are allocated from the plurality of page buffers to a first mapping page of a plurality of mapping pages. A PLB is allocated from the plurality of PLBs to a second mapping page of the plurality of mapping pages. One or more IO requests are processed using one or more of the first mapping page and the second mapping page.

A method of operating a non-volatile memory device may include precharging sensing nodes of a plurality of page buffers based on a reference voltage and latching the sensing nodes to obtain first sensing data, precharging the sensing nodes of the plurality of page buffers based on a power supply voltage and latching the sensing nodes to obtain second sensing data, and comparing the first sensing data and the second sensing data to determine whether a voltage level of the power supply voltage is lower than the reference voltage.

A memory device includes a memory cell array including a first memory region storing first data, a page buffer including a first latch configured to store data dumped from the memory cell array, and a control logic circuit configured to receive parity adjustment information from an external device and control an operation of the memory cell array. The first data includes first user data and first parity data including parity bits generated based on the first user data, and the control logic circuit dumps first parity data of which a size is adjusted based on the parity adjustment information to the first latch.

The invention provides a built-in self-test system of a memory, and belongs to the field of integrated circuits. The memory of the present invention comprises: a memory array including a plurality of memory cells for storing data; the controller is electrically connected with the storage array through the multiplexer and is electrically connected with the test machine table through a bus; the built-in self-test system comprises a built-in self-test circuit which is electrically connected with the controller and is electrically connected with the storage array through the multiplexer, and the built-in self-test circuit is used for testing the storage array; the page buffer is electrically connected with the controller and the built-in self-test circuit, and is used for caching the written data when the data is written into the storage array and temporarily storing a test result when the BIST is carried out on the storage array; and the one-time programmable memory is electrically connected with the controller and is used for finally storing the test result. According to the BIST system of the memory, the occupied area of a chip can be reduced, and the power consumption is reduced.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engine is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address. The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.

A nonvolatile memory device includes a memory cell array to store an original setting data, a page buffer circuit connected to the memory cell array through a plurality of bit-lines, a secure buffer and a control circuit. The secure buffer includes an access control circuit and a plurality registers with restricted access, and the plurality registers store the original setting data that is dumped-down from the memory cell array through the page buffer circuit in an initialization sequence. The control circuit controls the page buffer circuit and the secure buffer. The plurality registers include a first register and second registers. The access control circuit, in response to the first register being accessed, accesses at least a portion of the second registers concurrently with accessing the first register.

Control logic in a memory device initiates a read operation associated with a memory block of a memory device. During the read operation, the control logic causes transmission, via a sense module, of first data from a first memory cell of a first sub-block of the set of sub-blocks to a page buffer circuit. During the read operation, the control logic causes transmission, via the sense module, of second data from a second memory cell of a second sub-block of the set of sub-blocks to the page buffer circuit.

A non-volatile memory device includes a memory cell array including a first memory cell connected to a first bit line and having a first program status, a second memory cell connected to a second bit line that is different from the first bit line and having a second program status that is a higher level status than the first program status, and a third memory cell connected to a third bit line that is different from the first and second bit lines and having a third program status that is a higher level status than the first and second program status and a page buffer configured to apply a pre-charge voltage to the first and second bit lines in a first verify operation for the second program status, and apply the pre-charge voltage to the third bit line in a second verify operation for the third program status.

A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.

A semiconductor device may include a page buffer comprising first to fifth latches, wherein the first to third latches and the fifth latch are configured to store 4-bit original data, among 5-bit original data, respectively, and the fourth latch is configured to store data identical with the data that has been stored in the second latch and a control circuit configured to determine a program inhibition pattern based on data that have been stored in two of the first to fifth latches and control the page buffer so that data that has been stored in at least one of the first to fifth latches is inverted based on the program inhibition pattern.

A memory device includes a memory array and control logic, operatively coupled to the memory array, to receive, from a memory sub-system controller, a command related to execution of a memory access operation associated with one or more memory blocks of the memory device. In response to the command, a portion of a page buffer of the memory device is reserved. The memory device causes at least a portion of non-host data received from a high-performance local memory of the memory sub-system controller to be stored in the portion of the page buffer.

Disclosed is a semiconductor device including a plurality of strings connected between a plurality of bit lines and a source line, a plurality of page buffers connected to the plurality of bit lines, respectively, and configured to adjust a voltage level of each of the plurality of bit lines, and a control circuit configured to control the plurality of page buffers to fix a voltage level of a bit line connected to a string including a memory cell on which a program operation has been completely performed and to change a voltage level of a bit line connected to a string including a memory cell on which the program operation has not been completely performed, during a de-trap operation.