43 results about "Page buffers" patented technology

The implementation of the present disclosure discloses a memory and its operation method, a memory system and an electronic device. The memory includes: a memory cell array and a page buffer, the page buffer is disposed corresponding to a bit line of the memory cell array, and the page buffer includes: a precharge and discharge circuit coupled to the bit line through a sense node of the page buffer and including a first type transistor; a plurality of latches respectively coupled to the sense node, wherein at least one of the plurality of latches includes a second type transistor, and a characteristic size of the second type transistor is smaller than that of the first type transistor.

A memory device and a memory system having the same can be provided herein. The memory system includes a memory device including a plurality of memory blocks each including a pass block and page buffer blocks respectively coupled to the pass blocks, and a memory controller configured to control the memory device to perform an operation corresponding to a command on a consolidated pass block by merging pass blocks coupled to different page buffer blocks among the pass blocks including a memory block that is a pass block by block state information indicating that each pass block is one of a pass block and a bad block, the consolidated pass block being obtained by merging the pass blocks coupled to different page buffer blocks among the pass blocks including a memory block that is a pass block among memory blocks that are both a pass block and a bad block.

A memory device includes a first cell layer, a second cell layer stacked on the first cell layer, a third cell layer stacked on the second cell layer, a fourth cell layer stacked on the third cell layer, a first page buffer connected to a first string included in the first cell layer and a third string included in the third cell layer, a second page buffer connected to a second string included in the second cell layer and a fourth string included in the fourth cell layer, and a control logic circuit configured to control the first page buffer and the second page buffer to perform a respective core operation on each of the first cell layer and the second cell layer.

A memory device including: a memory cell array including pages each page including memory cells; a page buffer circuit including page buffers corresponding to the memory cells of each page, each of the page buffers including first through N-th latches; and a control logic to control first hard decision data and first soft decision data read in a first read operation on a first page to remain in a first page buffer during a second read operation on a second page, and control an output operation such that the first hard decision data is output after the first soft decision data is output when the memory device is set to a first output mode, wherein the first hard decision data is based on a normal read level and the first soft decision data is based on an offset read level read from the first page.

A nonvolatile memory device includes a first cell region, a second cell region, and a peripheral circuit region. The first cell region includes a first normal bit line and a first redundant bit line. The second cell region is disposed above the first cell region in a vertical direction and includes a second normal bit line and a second redundant bit line. The peripheral circuit region is disposed below the first cell region in the vertical direction and includes a page buffer circuit and a page buffer decoder. The page buffer circuit includes a page buffer connected to the first normal bit line, the second normal bit line, the first redundant bit line, and the second redundant bit line. The page buffer decoder is configured to integrate a defective bit line occurring among the first normal bit line and the second normal bit line and replace the defective bit line with the first redundant bit line and the second redundant bit line.

A non-volatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a plurality of memory cell arrays arranged in a first direction. Each of the plurality of memory cell arrays includes a plurality of sub-planes arranged in the first direction and extending in a second direction intersecting the first direction. The peripheral circuit region is arranged below the memory cell region in a vertical direction and includes a plurality of page buffer circuits in association with the plurality of memory cell arrays, respectively. Each of the plurality of memory cell arrays further includes a first common source plate extending in the first direction and commonly associated with the plurality of sub-planes, and a first bit line group and a second bit line group associated with first and second sub-planes of the plurality of sub-planes, respectively.

An example memory device includes a first wafer that includes a first sub-memory block connected to first to n-th word lines, a first bit line, a first string selection line, and a first ground selection line, and a second wafer that is stacked on the first wafer in a vertical direction and includes a second sub-memory block connected to (n+1)-th to 2n-th word lines, a second bit line, a second string selection line, and a second ground selection line. The first to n-th word lines are respectively connected to the (n+1)-th to 2n-th word lines and share first to n-th word line drivers with the (n+1)-th to 2n-th word lines. The first bit line is connected to the second bit line and shares a first page buffer with the second bit line.

A nonvolatile memory device includes a memory block, a page buffer circuit and a control circuit. The page buffer circuit is connected to the cell strings through bit-lines. The control circuit controls a read operation by: latching a first sensing data and a second sensing data in the page buffer circuit by performing a first read operation on a selected word-line designated by an access address based on a read voltage set; latching a third sensing data in the page buffer circuit by performing a second read operation on an aggressor word-line adjacent to the selected word-line, based on at least one adjacent read voltage; selecting one of the first sensing data and the second sensing data as a hard decision data based on a program state of the third sensing data; and generating a soft decision data by using the first sensing data and the second sensing data.

This application provides a page buffer circuit and storage device. The page buffer includes: multiple registers and a page buffer; the multiple registers are respectively connected to peripheral interfaces to sequentially receive input data through the peripheral interfaces; the input data is sequentially converted into at least one data segment; the page buffer is connected to the multiple registers to write the current data segment stored in the multiple registers into the page buffer, thereby writing the input data into the page buffer in the manner of converting it into the at least one data segment. The write speed of the page buffer in this page buffer circuit is not limited by the write speed specified by the peripheral interface protocol of the peripheral interface, and the multiple registers can write the stored data into the page buffer as needed, which reduces the performance requirements for the write speed of the page buffer.

A non-volatile memory device enabled with memory plane circuitry, a storage device including the non-volatile memory device, and a method of operating the non-volatile memory device are provided. The non-volatile memory device includes a first page buffer circuit, a first sub-memory plane circuit directly connected to the first page buffer circuit through a first bit line, a second sub-memory plane circuit directly connected to the first page buffer circuit through a second bit line different from the first bit line, and a control logic circuit. The control logic circuit receives a command from a storage controller, determines that the command indicates first type information or second type information, enables the first sub-memory plane circuit and the second sub-memory plane circuit in response to determining that the command indicates the first type information, and enables the first sub-memory plane circuit in response to determining that the command indicates the second type information.

An example non-volatile memory device includes a control logic circuit configured to generate a program signal, a voltage generator configured generate a first program voltage, a plurality of string select transistors, including first, second, and third string select transistors, a plurality of bit lines, including first, second, and third bit lines respectively connected to the first, second, and third string select transistors, and a page buffer circuit configured to apply a first voltage or a second voltage each bit line. Here, the control logic circuit applies the first voltage to the second bit line and the third bit line, inhibits the second string select transistor by applying the second voltage to the second bit line, and controls the page buffer circuit to inhibit the third string select transistor by applying a third voltage to the third bit line by the second voltage applied to the second bit line.

The present application relates to a page buffer, a memory device including the same, and an operating method thereof. An electronic device is provided, and more particularly, a page buffer. The page buffer includes a sense node configured to sense a potential of a bit line coupled to a memory cell, a pre-charge circuit coupled to the sense node and configured to pre-charge a potential of the sense node to a first voltage during an evaluation operation on the memory cell, a discharge circuit coupled to the sense node and configured to discharge the potential of the sense node from the first voltage to a second voltage, and a latch circuit coupled to the discharge circuit and configured to store therein data sensed from the memory cell based on a comparison result of the potential of the sense node with a reference voltage after the potential of the sense node is discharged to the second voltage and a predetermined period of time elapses.

A nonvolatile memory device includes a control logic configured to generate a clock signal and a page buffer selection signal including information about a ratio of a number of page buffers on which a fail bit counting operation is performed to a total number of the plurality of page buffers, a fail bit counting circuit configured to select one or more page buffers from among the plurality of page buffers, repeat the fail bit counting operation on the selected one or more page buffers, and output a value of a number of fail bits with respect to the page buffers on which the fail bit counting operation is performed, and a predictor configured to generate a prediction value with respect to a total number of fail bits with respect to the plurality of page buffers.

The present application relates to semiconductor devices, memory devices, and methods of operating the same. A memory device includes a memory structure and a control circuit. The memory structure includes a plurality of page buffers coupled to nonvolatile memory cells. Each nonvolatile memory cell is capable of storing data. The plurality of page buffers is disposed in a predetermined direction. The control circuit is configured to separate reset sections of two page buffers from each other by a time corresponding to at least one of the reset sections. The two page buffers are disposed adjacent to each other among the plurality of page buffers.

A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharge period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line when the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to the state of the selected memory cell after the precharge period. The selection circuit outputs a control voltage that controls a switching element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharge period based on the data stored in the first storage circuit.

A nonvolatile memory device which includes a memory cell array that includes a plurality of cell strings having a plurality of memory cells classified into pages, a row decoder that is connected to the memory cell array through string selection lines, ground selection lines, and word lines, and a page buffer that is connected to the memory cell array through bit lines. In response to that a read command for a first page is received from an external device, the row decoder applies first voltages to the word lines to correspond to first capacitances of memory cells of the first page. In response to that a read command for a first partial page of the first page is received from the external device, the row decoder applies second voltages to the word lines to correspond to second capacitances of memory cells of the first partial page.

Control logic in a memory device executes a read operation of at least a portion of first data stored in a first page buffer associated with a first memory plane of a plurality of memory planes of the memory device. A write operation is executed to cause second data associated with the at least the portion of the first data to be written to a second page buffer of the memory device.

This technology includes a memory device. The memory device includes: a memory cell; a page buffer configured to store sensing data obtained from the memory cell; a current sensing circuit configured to compare a sensing voltage generated based on the sensing data with a reference voltage generated based on an allowable failure bit code, and output a pass signal or a failure signal based on the comparison result; and a failure bit manager configured to increase the number of allowable failure bits included in the allowable failure bit code until the pass signal is output from the current sensing circuit, change the allowable failure bit code according to the number of allowable failure bits, and provide the allowable failure bit code to the current sensing circuit.

A memory device includes a memory cell array, a plurality of page buffer units connected to the memory cell array and connected in common to a combined sensing node, and a plurality of cache latches respectively corresponding to the plurality of page buffer units, the plurality of cache latches including a first cache latch and a second cache latch connected in common to the combined sensing node. In a first section of a data dumping operation on the first cache latch, first and second tri-state inverters included in the first cache latch are enabled to transmit data to the first cache latch, and third and fourth tri-state inverters included in the second cache latch are disabled. In a second section of the data dumping operation on the first cache latch, the third and fourth tri-state inverters are sequentially enabled to restore data previously stored in the second cache latch.

A computing device for a personal computing device for acceleration of a large language model, according to one embodiment of the present invention, comprises: a flash memory including at least one plane including a flash memory cell array, a page buffer, and an in-memory computing unit; a main memory; a parallel processing processor for processing operations for the large language model; and a central processing device for executing a control program. The in-memory computing unit processes a matrix multiplication operation on weight data read from the flash memory cell array, and then received from the page buffer, and on input data received from the main memory, and outputs an operation result thereof to the main memory.

An example of a storage device includes a nonvolatile memory device including a plurality of planes and a plurality of page buffers respectively connected to the planes, and a storage controller configured to provide a read command for reading data stored in the planes to the nonvolatile memory device, provide a first select chip pause command for instructing data output of a first plane of the planes to the nonvolatile memory device, and provide a second select chip pause command for pausing data output of the first plane and instructing data output of a second plane of the planes to the nonvolatile memory device.

A non-volatile memory device that includes a first page buffer circuit, a first sub-memory plane circuit directly connected to the first page buffer circuit through first bit lines, a second sub-memory plane circuit directly connected to the first page buffer circuit through second bit lines different from the first bit lines, and a control logic circuit. The control logic circuit receives a command from a storage controller, determines whether the command indicates first type information or second type information, enables the first sub-memory plane circuit and the second sub-memory plane circuit in response to determining that the command indicates the first type information, and enables the first sub-memory plane circuit in response to determining that the command indicates the second type information.

A semiconductor device includes a memory cell connected to a word line and a bit line. The semiconductor device also includes a line driving circuit configured to apply a program voltage to the word line. The semiconductor device further includes a page buffer comprising a plurality of latches comprising at least one dynamic latch and at least one static latch and configured to control a voltage level of the bit line after the start of a program operation. The semiconductor device additionally includes a control circuit configured to control the page buffer to program, into the memory cell, data that have been stored in the static latch or store the data in the dynamic latch based on a temperature of the semiconductor device, when receiving a pause command during the program operation.

The disclosure relates to a memory device and an operating method thereof. The memory device according to an embodiment of the disclosure includes a plurality of memory cells, a plurality of page buffers storing or reading data in or from the plurality of memory cells, a plurality of bit lines connected between the plurality of memory cells and the plurality of page buffers, and a cyclic redundancy check unit including a collection unit collecting bit line data loaded on the plurality of bit lines and a calculation unit performing a cyclic redundancy check (CRC) on the collected bit line data.

Storage devices and methods are disclosed. In an embodiment, a storage device may include a memory device including a plurality of memory units configured to store data and a plurality of page buffers coupled to the plurality of memory units, respectively, a volatile memory configured to store write data requested by a host, a power control device configured to control power supply to the memory device and the volatile memory and a processing circuit configured to control the memory device based on a command transmitted from the host. The processing circuit backs up the write data to a first page buffer among the plurality of page buffers in response to a low power mode entry command transmitted from the host. The power control device cuts off power supply to the volatile memory after the write data is backed up in the first page buffer.

This application provides a page cache, memory device, and memory system, relating to the field of semiconductor technology, which can improve the storage capacity and access speed of the page cache while reducing the cost of the page cache and memory device. The page cache includes a first latch circuit, a second latch circuit, and a third latch circuit. The second latch circuit is coupled to the first latch circuit and configured to transfer data to the first latch circuit. The third latch circuit is coupled to the first latch circuit and configured to transfer data to the first latch circuit. The page cache is configured to output data in the first latch circuit in response to a control signal; wherein the storage capacity of the third latch circuit is greater than the storage capacity of the second latch circuit.

A nonvolatile memory device including a first semiconductor structure including a first semiconductor substrate, a memory cell area including a plurality of memory cells disposed on the first semiconductor substrate, and a first metal pad disposed on the memory cell area; a second semiconductor structure including a second semiconductor substrate, a page buffer disposed on the second semiconductor substrate, and a second metal pad bonded to the first metal pad; and a third semiconductor structure including a third semiconductor substrate, a buffer memory and peripheral circuits disposed on the third semiconductor substrate, and a third metal pad connected to the peripheral circuits, wherein the page buffer includes a plurality of vertical transistors including a source area, a channel area, and a drain area sequentially stacked in a first direction, and the first semiconductor structure to third semiconductor structure are connected in the first direction.

A non-volatile memory device and a method of operating the non-volatile memory device are provided. The non-volatile memory device includes: a memory cell array comprising multiple planes; a page buffer circuit connected to the memory cell array via multiple bit lines and including at least one cache latch; and multiple input / output pads connected to the page buffer circuit via multiple data lines and configured to send data to and receive data from the memory controller. A command set may include at least one of cache latch address information and input / output pad address information, and the non-volatile memory device is configured to perform a read operation or a write operation based on at least one of the cache latch address information and input / output pad address information included in the command set.

Embodiments of the present application provide a data transmission device, method, memory and storage system. The data transmission device comprises a post-write generator configured to generate a post-write clock signal after the end of a write operation cycle, the post-write clock signal being used to enable remaining data in to-be-written data to be loaded into a page buffer in a memory; wherein the to-be-written data is data expected to be loaded into the page buffer in the write operation cycle; and the remaining data is data in the to-be-written data that fails to be loaded into the page buffer in the write operation cycle.