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Writing control method and writing control system of semiconductor storage device, and portable electronic apparatus

a writing control and writing control technology, applied in the field of semiconductor storage devices, can solve the problems of difficult to realize the reduction in the thickness of the insulating film, difficult to reduce the thickness of the gate insulating film, etc., and achieve the effect of easy realization

Inactive Publication Date: 2005-01-06
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0008] An object of the present invention is to provide an easily-realized finer semiconductor storage device and a high-speed writing method which is suitable for that semiconductor storage device.
[0016] Thus, a speedup of writing is realized by performing one-side interleave operation using two page planes in reading and writing. Further, the memory array performs a high speed operation, further speeding up writing operation. Therefore, data processing of the memory array can be improved by using the page buffer in the memory array.

Problems solved by technology

However, such a flash memory has the following problems: it is functionally necessary that the insulating film 907 is placed to isolate the floating gate 902 from the word line 903; and it is difficult to reduce the thickness of the gate insulating film to prevent leakage of charges from the floating gate 902.
Therefore, it is difficult to realize the reduction in thickness of the insulating film 907 and the gate insulating film, interfering with the realization of a finer memory cell.

Method used

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  • Writing control method and writing control system of semiconductor storage device, and portable electronic apparatus
  • Writing control method and writing control system of semiconductor storage device, and portable electronic apparatus
  • Writing control method and writing control system of semiconductor storage device, and portable electronic apparatus

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embodiment 1

[0085] [Embodiment 1]

[0086] A semiconductor storage device of the present embodiment includes a memory element 1 as shown in FIG. 1.

[0087] The memory element1 is arranged such that a gate electrode 104 is formed via a gate insulating film 103 on a P-type well region 102 which is formed on the surface of a semiconductor substrate 101. On the upper surface and side surfaces of the gate electrode 104, arranged is a silicon nitride film 109 which is a charge holding film, holding charges at a trap level. The portions of the silicon nitride film 109 on the both side walls serve as memory functional sections 105a and 105b where charges are actually held. Here, the memory functional section indicates a section where charges are actually accumulated by rewriting operation in a memory functioning member or a charge holding film. In the P-type well region 102 on the opposite sides of the gate electrode 104, formed are N-type diffusion regions 107a and 107b which function as source region or ...

embodiment 2

[0106] [Embodiment 2]

[0107] A memory element in a semiconductor storage device of the present embodiment, as shown in FIG. 8, has substantially the same arrangement as that of the memory element 1 in FIG. 1, except for the arrangement in which each memory functioning members 261 and 262 is constituted by a region where charges are held (this region is a region where charges are accumulated and may be a film having a function of holding charges) and a region where charges are less prone to escaping (this region may be a film having a function of making charges less prone to escaping).

[0108] In terms of improvement in holding property of memory, the memory functioning members preferably include an insulating film and a charge holding film capable of holding charges. In the present embodiment, a silicon nitride film 242 having a level of trapping charges is used as a charge holding film, and silicon oxide films 241 and 243 capable of preventing the dissipation of charges accumulated i...

embodiment 3

[0120] [Embodiment 3]

[0121] As shown in FIG. 13, a memory functioning member 262 in the semiconductor storage device of the present embodiment includes a silicon nitride film 242, which is a charge holding film, with substantially uniform film thickness, having a region 281 which is arranged substantially parallel to the surface of the gate insulating film 214 and a region 282 which is arranged substantially parallel to the side surface of the gate electrode 217.

[0122] When a positive voltage is applied to a gate electrode 217, an electric flux line 283, as indicated by arrow, in a memory functioning member 262 passes through the silicon nitride film 242 twice (the region 282 and the region 281). Note that, when a negative voltage is applied to the gate electrode 217, an electric flux line reverses its direction. Here, the silicon nitride film 242 has a relative permittivity of approximately 6, and the silicon oxide films 241 and 243 have a relative permittivity of approximately 4....

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Abstract

A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane. Further, the CPU writes a second byte of data into the second plane and writes the second byte of data having been stored in the second plane while writing the first byte of data having been stored in the first plane into the memory array.

Description

[0001] This Nonprovisional application claims priority under U.S.C. § 119(a) on Patent Application No. 2003 / 142754 d in Japan on May 20, 2003, the entire contents of ch are hereby incorporated by reference.FIELD OF THE INVENTION [0002] The present invention relates to a semiconductor age device including a plurality of memory elements h having: a gate electrode provided on a semiconductor r with an intervening gate insulating film; a channel on provided beneath the gate electrode; a diffusion on provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, and particularly relates to speedup of writing operation. BACKGROUND OF THE INVENTION [0003] Conventionally, a flash memory has been used as a nonvolatile memory. [0004] In this flash memory, as shown in FIG. 31, a memory cell is constituted such that a semiconductor subst...

Claims

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Application Information

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IPC IPC(8): G11C16/24G11C16/02H01L21/8247H01L27/10H01L27/115H01L29/788H01L29/792
CPCG11C16/24
Inventor IWASE, YASUAKIYAOI, YOSHIFUMIIWATA, HIROSHISHIBATA, AKIHIDEMORIKAWA, YOSHINAONAWAKI, MASARU
Owner SHARP KK
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