142 results about "Semiconductor storage devices" patented technology

Control circuit (100) which outputs a first signal to discharge charges accumulated in a source line (SL) and a bit line (BL) according to the activation of a word line (WL) and outputs a second signal to put the source line and the bit line into a potential-free state until the start of writing or reading, with respect to a memory cell which has the source line (SL), the bit line (BL), a transistor (Tr5) which is provided between the source line (SL) and the bit line (BL) and is switched on and off by a potential of the word line (WL), and a storage element (R1) connected in series with the transistor (TR5), wherein the control circuit (100) has a first transistor (Tr3) connected to the source line (SL) and a second transistor (Tr4) connected to the bit line (BL), and the first transistor (Tr3) includes a first gate terminal and the second transistor (Tr4) includes a second gate terminal, wherein the first gate terminal is connected to a first NAND gate (69) and the second gate terminal is connected to a second NAND gate (70), and wherein both the source line (SL) and the bit line (BL) are short-circuited to a ground potential at a first time point in response to the first signal and transition from their respective first potential-free states to their respective non-potential-free states, and transition at a second time point in response to the second signal to their respective second potential-free states.

A semiconductor storage device includes a memory device including a plurality of memory cells, each of the plurality of memory cell including a transistor and configured to store data; and a controller. The controller configured to write data to the plurality of memory cells using a first range from a first voltage to a maximum threshold voltage of the plurality of memory cells, wherein the first voltage is higher than a minimum threshold voltage of the plurality of memory cells by a quarter of an operable range between the minimum threshold voltage and the maximum threshold voltage. The controller configured to heat the plurality of memory cells (i) while writing with the first range, (ii) while reading after the data has been written, or (iii) after the data has been written.

The semiconductor storage device of the present application includes: a plurality of first conductive layers; a plurality of second conductive layers; a first semiconductor layer disposed between the conductive layers; a charge storage layer including a first portion disposed between the plurality of first conductive layers and the first semiconductor layer, and a second portion disposed between the plurality of second conductive layers and the first semiconductor layer; and a first wiring electrically connected to the first semiconductor layer. The semiconductor storage device is configured to be capable of performing a readout operation and a first operation. In the readout operation, a readout voltage is supplied to an nth (n is an integer of 1 or more) first conductive layer counted from one side in a first direction, and a readout path voltage is supplied to at least a portion of the plurality of first conductive layers. In the first operation, a first voltage is supplied to the first wiring, and a second voltage smaller than the first voltage is supplied to an nth second conductive layer counted from one side in the first direction.

Embodiments provide a semiconductor storage device capable of reducing the influence of load effect at the time of manufacturing and a manufacturing method thereof. The manufacturing method of the semiconductor storage device (10) of the embodiments includes the steps of: forming a processed portion (70) by alternately laminating an insulating layer (30) and a sacrificial layer (60); forming an etching mask (300) on a surface (S11) of the processed portion (70); forming, in a first region that is a part of the etching mask (300), a plurality of through holes (310) that reach the surface (S11) of the processed portion (70) from a surface (S20) of the etching mask (300), and forming, in a second region that is adjacent to the first region in the etching mask (300), a recessed portion (320) in which a part of the surface (S20) of the etching mask (300) is recessed toward the processed portion (70).

A semiconductor storage device according to the present disclosure includes a semiconductor substrate including a first region which is a source region or a drain region and a second region which is spaced from the first region in a first direction and which is the source region or the drain region, a first contact connected to the first region, a second contact connected to the second region, a first memory cell connected to the first contact, a gate electrode formed between the first contact and the second contact, a first conductor having a height equal to a height of the gate electrode and electrically connected to the first contact, and a second conductor having a height equal to the height of the gate electrode, having at least a portion formed between the gate electrode and the second contact, and insulated from the gate electrode, the first contact, and the second contact.

A semiconductor storage device having high reliability is provided. The semiconductor storage device includes: a laminate having conductive layers and insulating layers alternately laminated in a first direction; a plurality of memory pillars extending in the first direction within the laminate; and a structure body partitioning the plurality of memory pillars and extending in the first direction within the laminate. The structure body includes: a crystalline conductor extending in the first direction within the laminate; a first insulating film provided between the laminate and the crystalline conductor; a crystalline semiconductor film provided between the crystalline conductor and the first insulating film and containing silicon; and a second insulating film provided between the crystalline semiconductor film and a side surface of the crystalline conductor and containing silicon and oxygen. The crystalline conductor includes: a first crystalline region in contact with the crystalline semiconductor film and containing germanium; and a second crystalline region provided on the first crystalline region and in contact with the second insulating film in a second direction perpendicular to the first direction.

Each of n memory cells (150 etc.) provided in a semiconductor storage device (130a) has: a first resistance element (61p) and a first switch element (71p), which is controlled by a first word line (WL), connected in series between a bit line (BL) and a first source line (SL); a second resistance element (62n) and a second switch element (72n), which is controlled by the first word line (WL), connected in series between the bit line (BL) and a second source line (SLB); a third switch element (73p), which is controlled by a second word line (WLB), connected in series with the second resistance element (62n) between the bit line (BL) and the first source line (SL); and a fourth switch element (74n), which is controlled by the second word line (WLB), connected in series with the first resistance element (61p) between the bit line (BL) and the second source line (SLB).

A semiconductor storage device includes first and second chips. The second chip has a memory region and an edge seal region, and includes a plurality of edge seals, a first wiring layer at a first layer level on a first chip side of the edge seals, and a second wiring layer at a second layer level and contains tungsten. The first wiring layer includes first wirings at positions overlapping with inner edge seals, respectively, but not with an outermost edge seal and electrically connected to the inner edge seals, respectively. The second wiring layer includes second wirings that are provided at positions overlapping with the inner edge seals, respectively, but not with the outermost edge seal, and electrically connected to the inner edge seals, respectively, and a third wiring provided on an outer side of the second wirings, and electrically separated and spaced apart from the outermost edge seal.

The present disclosure provides a semiconductor storage device and a manufacturing method thereof, and relates to the technical field of semiconductor technology. The semiconductor storage device comprises: a nitrogen layer and a storage combination unit which are alternately stacked; wherein the outer layer of the storage combination unit is a first insulator, the inner side of the first insulator is a ring-shaped floating body, the inner side of the floating body is a ring-shaped channel region, and the inner side of the channel region is provided with a gate; at least one pair of through holes respectively penetrating the storage combination unit to break the ring-shaped floating body, channel region and gate; in at least one pair of through holes, one through hole is filled with a source electrode, and the source electrode only contacts the channel regions on both sides; and the other through hole is filled with a drain electrode, and the drain electrode only contacts the channel regions on both sides. The present disclosure can improve the integration of the semiconductor storage device.

A semiconductor device includes an upper electrode, a lower electrode, an oxide semiconductor including a first portion connected to the upper electrode, a connection portion, a second portion that is connected to a lower end portion of the first portion through the connection portion, has a diameter larger than that of the lower end portion of the first portion, and connected to the lower electrode, a gate insulating film surrounding a side surface of the first portion and has an outer diameter smaller than that of the second portion, a first insulating layer through which the first portion penetrates, a gate electrode which is provided below the first insulating layer and faces the first portion via the gate insulating film, the first portion penetrating through the gate electrode, and a second insulating layer provided below the gate electrode, wherein the connection portion is surrounded by the second insulating layer.

In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Provided is a semiconductor memory device capable of increasing the speed of a write operation. The semiconductor memory device includes a memory cell array having a first block and a second block, and a control unit. The control unit applies a first voltage to a channel region of a first memory cell transistor in a first block via a bit line, and then applies a program voltage to a first word line in a state in which the channel region of the first memory cell transistor is brought into a floating state. After the channel region of the first memory cell transistor is brought into a floating state, the control unit starts a second write operation for writing data to the second memory cell transistor of the second block during a period until the application of the program voltage to the first word line ends.

A semiconductor storage device includes first and second chips. The first chip includes a first semiconductor substrate, first conductive layers arranged in a first direction and extending in a second direction, a semiconductor column extending in the first direction and facing the first conductive layers, a first charge storage film formed between the first conductive layers and the semiconductor column, a plurality of first transistors on the first semiconductor substrate, and first bonding electrodes electrically connected to a portion of the plurality of first transistors. The second chip includes a second semiconductor substrate, a plurality of second transistors on the second semiconductor substrate, and second bonding electrodes electrically connected to a portion of the plurality of second transistors, and bonded to the first bonding electrodes. A thickness of the second semiconductor substrate in the first direction is smaller than a thickness of the first semiconductor substrate in the first direction.

A semiconductor storage device of an embodiment includes a plurality of first conductive layers arranged apart from each other in a first direction; a structure including a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, a gate insulating layer provided between the first semiconductor layer and the plurality of first conductive layers, and a second semiconductor layer disposed at one end portion of the first semiconductor layer in the first direction and connected to the first semiconductor layer; a contact connected to the second semiconductor layer of the structure; an insulating portion that divides a part of the first conductive layers disposed on one end portion side of the structure in the first direction among the plurality of first conductive layers in a second direction intersecting the first direction, and that is connected to the structure and the contact from one side in the second direction; and a first insulating layer connected from the other side in the second direction of the contact. The insulating portion includes an insulating material different in kind from the first insulating layer.

Embodiments provide a semiconductor storage device capable of reducing the size and improving the reliability. The semiconductor storage device of the embodiments includes a via (35A) provided above a substrate, a conductive layer (35B) provided on the via (35A), and a via (35C) provided on the conductive layer (35B). The via (35A), the conductive layer (35B), and the via (35C) are one continuous layer.

A device comprises: a substrate having a first side and a second side; a first transistor and a second transistor formed in a first layer on the first side; a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor formed in a second layer on the first side; a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure formed on the second side, wherein the first and second interconnect structures are each configured to carry a supply voltage, and the third and fourth interconnect structures are each configured to carry a ground voltage;and a power supply structure extending vertically through the first and second levels and configured to electrically couple a source / drain terminal of the third transistor and a source / drain terminal of the fourth transistor to the third interconnect structure and the fourth interconnect structure, respectively.

A latch group includes a first latch circuit, a second latch circuit, and a third latch circuit. A clock signal of which a signal value is inverted from a clock signal of the second latch circuit is input to the first latch circuit and the third latch circuit. A control circuit is configured to operate the latch group in a normal mode, and first and second test modes. The control circuit, while operating the latch group in a first test mode, transmits a control signal to the first switch circuit to connect the electrical path between the first data output terminal and the second data input terminal, and while operating the latch group in the second test mode, transmits a control signal to the second switch circuit to connect the electrical path between the second data output terminal and the third data input terminal.

The problem is to apply a high voltage to a storage element other than a write target without making a sense amplifier module high voltage. The solution is that the semiconductor storage device of the embodiment has: a laminate in which a plurality of first insulating layers and a plurality of second insulating layers are alternately laminated; a plurality of channel layers respectively provided in the plurality of first insulating layers and extending in a first direction along the plurality of first insulating layers; a word line extending within the laminate in a laminating direction of the laminate and intersecting the plurality of channel layers; a plurality of bit lines respectively connected to the plurality of channel layers; and a plurality of boost circuits respectively provided in the plurality of first insulating layers and respectively connected to the plurality of bit lines.

Provided is a semiconductor storage device that can be appropriately manufactured, which has: a substrate having a first region and a second region arranged in a first direction; a plurality of conductive layers and a plurality of interlayer insulating layers alternately arranged in a second direction intersecting a surface of the substrate, extending in the first direction over the first region and the second region; a semiconductor layer provided in the first region, extending in the second direction, and facing the plurality of conductive layers; a charge accumulation film provided between the plurality of conductive layers and the semiconductor layer; and a first structure provided in the second region, extending in the second direction, and having an outer peripheral surface surrounded by at least a portion of the plurality of conductive layers. The first structure has: a plurality of third regions provided corresponding to at least a portion of the plurality of conductive layers; and a plurality of fourth regions provided corresponding to at least a portion of the plurality of interlayer insulating layers. A width in the first direction of the plurality of third regions is greater than a width in the first direction of the plurality of fourth regions.

A semiconductor storage device includes a plurality of memory cells aligned in first and second directions, each memory cell extends in a third direction and includes a MOS transistor and a capacitor, the MOS transistor includes a first insulating layer that extends in the third direction, a semiconductor layer that extends in the third direction to surround a side surface of the first insulating layer and is formed of a two-dimensional material, and a gate electrode that is provided outside the semiconductor layer, the capacitor includes a first electrode, a second electrode, and a capacitor material layer extending in the third direction, the first electrode surrounds a side surface of the second electrode, the capacitor material layer is provided between the first electrode and the second electrode, and the first electrode is in contact with a first end portion of the semiconductor layer in the third direction.

According to one embodiment, a cell block includes memory cells and select transistors. The memory cells correspond are connected in parallel between a local source line and a local bit line. The select transistor is connected between the local bit line and a bit line. The memory cell includes a cell transistor and a resistance change element. A gate of the cell transistor is connected to a word line. The resistance change element is connected to the cell transistor in series between the local source line and the local bit line. Each cell block is configured as a columnar structure penetrating a plurality of conductive films functioning as word lines. The select transistor and the local bit line are connected at a contact portion formed of a material different from a material of the local bit line.

A semiconductor memory device includes a memory cell array and peripheral circuitry. The memory cell array includes blocks of memory cells. The peripheral circuitry can execute a first programming verification cycle in response to a first write operation on a first word line in a word line group, thereby programming the memory cell associated with the first word line into multiple states. The word line group includes one or more word lines. The peripheral circuitry then determines a verification start cycle of multiple states based on sensing results in the first programming verification cycle, and executes a second programming verification cycle with the determined verification start cycle of multiple states in response to a second write operation on a second word line in the word line group.

A semiconductor storage device according to one embodiment comprises a first circuit board and a second circuit board. The first circuit board includes a first section, a second section that is thinner than the first section, and a plurality of first conductive sections on the second section. The second circuit board includes a plurality of second conductive sections. The plurality of second conductive sections overlaps the plurality of first conductive sections when viewed from a first direction, which is a thickness direction of the first circuit board. The plurality of second conductive sections are connected to the plurality of first conductive sections by solder in a one-to-one correspondence.

A semiconductor storage device includes one or more first memory cells connected in parallel between a first voltage supply line supplying a first voltage and a second voltage supply line supplying a second voltage different from the first voltage, and one or more second memory cells connected in parallel between the second voltage supply line and a third voltage supply line supplying the first voltage, wherein each of the first memory cells includes a first storage element having a resistance value corresponding to a first status or a second status, and a first cell transistor connected between the first storage element and the first voltage supply line, and each of the second memory cells includes a second storage element having a resistance value corresponding to a first status or a second status, and a second cell transistor connected between the second storage element and the third voltage supply line.

A semiconductor storage device according to the present invention comprises a first memory cell transistor, a second memory cell transistor, a sense amplifier, and a control unit. In a first operation mode, the control unit, via the sense amplifier, senses data stored at the first memory cell transistor. In the first operation mode, the control unit adjusts a first prescribed number of first read voltages to the first prescribed number of third read voltages that include a second prescribed number that is smaller than the first prescribed number of second read voltages that correspond to a plurality of second threshold voltage distributions, applies the first prescribed number of third read voltages to a gate of the second memory cell transistor via a word line, and, via the sense amplifier, senses data stored at the second memory cell transistor.

According to one embodiment, a semiconductor storage device includes a plurality of terminals. The plurality of terminals form at least a first row and a second row. The first row includes a plurality of terminals arranged in a first direction at intervals from each other at locations closer to a first end edge than to a second end edge. The second row includes a plurality of terminals arranged in the first direction at intervals from each other at locations closer to the second end edge than to the first end edge. An area between the first row and the second row on a first surface includes a contact area that is in contact with a heat-conducting member, which is disposed on a printed circuit board in a host device that is electrically connected to the semiconductor storage device.

A semiconductor storage device is provided which operates appropriately. The semiconductor storage device includes: a plurality of semiconductor layers and a plurality of insulating layers which are alternately stacked in a stacking direction and extend in a first direction; a plurality of conductive layers which are stacked in the stacking direction and connected to end portions of the plurality of semiconductor layers; a plurality of first via electrodes which are arranged in the first direction and face the plurality of semiconductor layers; a plurality of charge accumulation layers which are provided between the plurality of semiconductor layers and the plurality of first via electrodes; and a plurality of second via electrodes which are provided between the plurality of conductive layers and the plurality of first via electrodes, arranged in the first direction, and face the plurality of semiconductor layers. In a first cross section, a face of the second via electrode facing one of the plurality of semiconductor layers follows a first circle, and a face of the second via electrode facing an opposite side of the plurality of semiconductor layers follows a second circle. In a second cross section, an outer peripheral face of the second via electrode follows a third circle. A radius of at least one of the first circle and the second circle is different from a radius of the third circle.

A semiconductor storage device that is capable of improving reliability includes: a non-volatile memory provided with a block including a plurality of memory cell transistors connected to a word line; and a controller configured to monitor a threshold voltage distribution width of the plurality of memory cell transistors after performing at least one of an erasing operation on the block and a preliminary write operation on the plurality of memory cell transistors and to classify the plurality of memory cell transistors according to the threshold voltage distribution width of the plurality of memory cell transistors.