411 results about "Semiconductor storage devices" patented technology

In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.

A semiconductor storage device includes a first stacked region, a second stacked region, and a connection region arranged between the first and second stacked regions. In the connection region, one of a plurality of conductor layers in an upper stepped portion is connected to one of the plurality of conductor layers in the first stacked region via one of the plurality of conductor layers in a bridge portion.

According to one embodiment, in a semiconductor storage device, during an erasing operation, a voltage supplied to at least one of a first wiring and a second wiring is set as a first voltage, and a voltage supplied to a first conductive layer is set as a second voltage. The erasing operation includes a first operation period in which the first voltage is increased from a first reference voltage to a first erase voltage and the second voltage is increased from a second reference voltage to a second erase voltage. In a second operation period of the erasing operation, the first voltage is maintained at the first erase voltage and the second voltage is decreased from the second erase voltage to the second reference voltage (or a first level voltage larger than the second reference voltage) after the first operation period.

A memory system includes a semiconductor memory device; and a memory controller configured to control the semiconductor memory device. The semiconductor memory device includes a first pin configured to receive a first signal and a second signal sent from the memory controller, the second signal having a smaller amplitude than the first signal. A first receiving circuit is connected to the first pin and is configured to output a third signal and a fourth signal having a smaller amplitude than the third signal. The first receiving circuit outputs the third signal based on a comparison between the first signal and a first voltage, and outputs the fourth signal based on a comparison between the second signal and a second voltage. A first terminating circuit is connected to the first pin and is configured to be disabled if the first pin receives the first signal and enabled if the first pin receives the second signal.

To provide a semiconductor storage device which enables high-speed operation.SOLUTION: A semiconductor storage device includes a substrate, a plurality of memory blocks, and a control circuit. The control circuit is configured to be able to consecutively execute a second program operation, after subsequently executing a first precharge operation and a first program operation in a first-mode write operation. In the first precharge operation, a predetermined voltage is supplied to a first word line. In the first program operation, a first voltage is supplied to a first selection gate line, a first program voltage is supplied to the first word line, and a write path voltage smaller than the first program voltage is supplied to a second word line. In the second program operation, the first voltage is supplied to a second selection gate line, a second program voltage larger than the write path voltage is supplied to the first word line, and the write path voltage is supplied to the second word line.SELECTED DRAWING: Figure 12

A semiconductor storage device includes a memory string, a sense amplifier including first and second latch circuits, a cache memory including a third latch circuit, and a control circuit. The control circuit is configured to perform a first read operation in response to a first command set and consecutively perform a second read operation in response to a second command set received during the first read operation. During the first read operation, data read from the memory string is stored in the first latch circuit. When the second command set is received at a first timing, the control circuit transfers the data to the second latch circuit, and then to the third latch circuit. When the second command set is received at a second timing before the first timing, the control circuit directly transfers the data to the third latch circuit.

To provide a semiconductor storage device capable of suppressing the occurrence of void.SOLUTION: A semiconductor storage device comprises a first chip and a second chip bonded on the first direction side with respect to the first chip. The first chip includes a plurality of first bonding electrodes provided on a first bonding surface to which the second chip is bonded. The second chip includes a plurality of second bonding electrodes provided on a second bonding surface to which the first chip is bonded. The plurality of first bonding electrodes and the plurality of second bonding electrodes are bonded to each other to form a plurality of junction electrodes. The plurality of junction electrodes include junction electrodes arranged adjacently on one side in a third direction with respect to a second insulation layer as a first junction electrode, and junction electrodes arranged adjacently on the other side in the third direction with respect to the second insulation layer as a second junction electrode. The plurality of first junction electrodes and the plurality of second junction electrodes are arranged in a mutually zigzag manner in a second direction and the third direction.SELECTED DRAWING: Figure 7

A memory includes a first data-line and a first control-line for writing and a second data-line and a second control-line for reading. A memory cell includes a first transistor connected to the first control-line at a gate and connected to the first data-line, a second transistor connected to the second control-line at a gate and connected to the second data-line, and a third transistor connected to the first transistor at a gate and connected to the second transistor. A detector is connected to the first and second data-lines. In writing or reading, the controller activates the second control-line, the detector detects first data based on a voltage of the second data-line, and thereafter the controller activates the first control-line. After reception of a write command, the detector transmits second data from outside to the gate of the third transistor when latching the second data.

In one embodiment, a semiconductor storage device includes a string that has one end electrically connected to a bit line, and another end electrically connected to a source line, and includes a plurality of memory cells. An operation of writing data to each of a plurality of adjacent first memory cells among the plurality of memory cells is sequentially performed in a direction from a first memory cell on a side of the source line to a first memory cell on a side of the bit line. An operation of reading data from each of the plurality of adjacent first memory cells is performed to allow a current to flow through the string in a first direction from the source line to the bit line.

A semiconductor device of an embodiment includes a seed generator circuit configured to generate a seed from inputted data by using first random number sequence data generated by an XorShift circuit; and a random number generator circuit configured to receive the seed as input to generate second random number sequence data by a second XorShift circuit.

Provided is a semiconductor storage device for STT-MRAM in which the circuit area is reduced to achieve high density. A semiconductor storage device 1000 comprises a memory cell array 10 in which a plurality of memory cells 100 are arranged in rows and columns. Each memory cell 100 includes: a magnetic tunnel junction element capable of data writing by spin transfer torque due to write current; a first electrode of a topological antiferromagnetic material provided so as to supply the write current to the magnetic tunnel junction element; and a switch element SW00 for opening and closing a supply path of the write current to the magnetic tunnel junction element. The semiconductor storage device 1000 further comprises a plurality of first wires WL0, WL1 provided in the row direction of the memory cell array to control the opening / closing of the switch element SW00. The switch element SW00 is a transistor, and an active layer continuously provided in memory cells adjacent to each other in the column direction includes a channel region of each of a plurality of transistors.

A semiconductor storage device includes a memory cell array and a peripheral circuit disposed at least partially below the memory cell array. The peripheral circuit includes an RC circuit in which a resistive portion and a capacitive portion are electrically connected to each other in series. The resistive portion includes first and second lower conductors at a level that is below the memory cell array, an upper conductor at a level that is above the memory cell array, a first contact that connects the first lower conductor to the upper conductor, and a second contact that connects the upper conductor to the second lower conductor. The first lower conductor, the first contact, the upper conductor, the second contact, and the second lower conductor are electrically connected in series in this order and the first lower conductor is closest to the capacitive portion.

Control circuit (100) which outputs a first signal to discharge charges accumulated in a source line (SL) and a bit line (BL) according to the activation of a word line (WL) and outputs a second signal to put the source line and the bit line into a potential-free state until the start of writing or reading, with respect to a memory cell which has the source line (SL), the bit line (BL), a transistor (Tr5) which is provided between the source line (SL) and the bit line (BL) and is switched on and off by a potential of the word line (WL), and a storage element (R1) connected in series with the transistor (TR5), wherein the control circuit (100) has a first transistor (Tr3) connected to the source line (SL) and a second transistor (Tr4) connected to the bit line (BL), and the first transistor (Tr3) includes a first gate terminal and the second transistor (Tr4) includes a second gate terminal, wherein the first gate terminal is connected to a first NAND gate (69) and the second gate terminal is connected to a second NAND gate (70), and wherein both the source line (SL) and the bit line (BL) are short-circuited to a ground potential at a first time point in response to the first signal and transition from their respective first potential-free states to their respective non-potential-free states, and transition at a second time point in response to the second signal to their respective second potential-free states.

A semiconductor storage device according to one embodiment includes a housing having a housing space, a board disposed in the housing space and having a first surface, and a semiconductor memory provided on the first surface.

A semiconductor storage device includes a memory device including a plurality of memory cells, each of the plurality of memory cell including a transistor and configured to store data; and a controller. The controller configured to write data to the plurality of memory cells using a first range from a first voltage to a maximum threshold voltage of the plurality of memory cells, wherein the first voltage is higher than a minimum threshold voltage of the plurality of memory cells by a quarter of an operable range between the minimum threshold voltage and the maximum threshold voltage. The controller configured to heat the plurality of memory cells (i) while writing with the first range, (ii) while reading after the data has been written, or (iii) after the data has been written.

The utility model relates to the technical field of semiconductors, in particular to a semiconductor storage device which comprises a box cover connected to a storage box, a sealing heat dissipation mechanism enabling the storage box to be tightly attached to the box cover is arranged on the box cover, and a storage mechanism for storing semiconductor devices is arranged in the storage box. By arranging the storage mechanism, the semiconductor devices can be conveniently and quickly taken in the process of storing the semiconductor devices, so that the storage efficiency of the semiconductor devices is improved, the device can protect the semiconductor devices, the semiconductor devices are prevented from being damaged in the storage process, and the storage efficiency of the semiconductor devices is improved. By arranging the sealing heat dissipation mechanism, in the process of storing the semiconductor device, the box cover and the storage box can be tightly attached together, the situation that dust permeates into the storage box due to gaps is avoided, heat in the storage box can be discharged, the heat dissipation function is achieved, and the semiconductor device is further protected.

The present disclosure provides a semiconductor storage device with low contact resistance of a trench and a manufacturing method thereof. The semiconductor storage device of an embodiment includes a plurality of first wiring layers, a first pillar, a second wiring layer, a semiconductor-containing layer, and a first insulating layer. The plurality of first wiring layers are stacked in a first direction. The first pillar extends inside the plurality of first wiring layers along the first direction and includes a first semiconductor layer. The second wiring layer is disposed above an upper end of the first semiconductor layer and extends along a second direction intersecting the first direction. The semiconductor-containing layer has a first portion, a second portion, and a third portion. The first portion is disposed between the upper end of the first semiconductor layer and a bottom surface of the second wiring layer. The second portion is continuous with the first portion and is disposed along a side surface of the second wiring layer. The third portion is continuous with an upper end of the second portion and extends along a direction intersecting the first direction. The first insulating layer is disposed between the first portion and the second wiring layer and between the second portion and the second wiring layer. At least an upper surface of the third portion contains a metal.

The semiconductor storage device of the present application includes: a plurality of first conductive layers; a plurality of second conductive layers; a first semiconductor layer disposed between the conductive layers; a charge storage layer including a first portion disposed between the plurality of first conductive layers and the first semiconductor layer, and a second portion disposed between the plurality of second conductive layers and the first semiconductor layer; and a first wiring electrically connected to the first semiconductor layer. The semiconductor storage device is configured to be capable of performing a readout operation and a first operation. In the readout operation, a readout voltage is supplied to an nth (n is an integer of 1 or more) first conductive layer counted from one side in a first direction, and a readout path voltage is supplied to at least a portion of the plurality of first conductive layers. In the first operation, a first voltage is supplied to the first wiring, and a second voltage smaller than the first voltage is supplied to an nth second conductive layer counted from one side in the first direction.

Embodiments provide a semiconductor storage device capable of reducing the influence of load effect at the time of manufacturing and a manufacturing method thereof. The manufacturing method of the semiconductor storage device (10) of the embodiments includes the steps of: forming a processed portion (70) by alternately laminating an insulating layer (30) and a sacrificial layer (60); forming an etching mask (300) on a surface (S11) of the processed portion (70); forming, in a first region that is a part of the etching mask (300), a plurality of through holes (310) that reach the surface (S11) of the processed portion (70) from a surface (S20) of the etching mask (300), and forming, in a second region that is adjacent to the first region in the etching mask (300), a recessed portion (320) in which a part of the surface (S20) of the etching mask (300) is recessed toward the processed portion (70).

A semiconductor storage device includes memory cells and a sense amplifier circuit. Each of the memory cells includes p-type drive transistors, n-type load transistors, and p-type access transistors connected to a bit line pair. The sense amplifier circuit includes p-type transistors and n-type transistors.

A semiconductor storage device according to the present disclosure includes a semiconductor substrate including a first region which is a source region or a drain region and a second region which is spaced from the first region in a first direction and which is the source region or the drain region, a first contact connected to the first region, a second contact connected to the second region, a first memory cell connected to the first contact, a gate electrode formed between the first contact and the second contact, a first conductor having a height equal to a height of the gate electrode and electrically connected to the first contact, and a second conductor having a height equal to the height of the gate electrode, having at least a portion formed between the gate electrode and the second contact, and insulated from the gate electrode, the first contact, and the second contact.

To provide an optimum operation method of a memory cell, which stores data according to an amount of electricity accumulated on a floating body and satisfies current SDRAM operation specifications.SOLUTION: A clock synchronous type dynamic semiconductor storage device that uses a memory cell storing two logic values according to an amount of electricity accumulated on a floating body performs writing two logic values into the memory cell, which is performed not simultaneously but separately, triggered by different commands or at different times. The writing of one of the two logic values into the memory cell is performed, triggered by a command to release a memory cell selection state or at timing to perform the release.SELECTED DRAWING: Figure 4

A semiconductor storage device having high reliability is provided. The semiconductor storage device includes: a laminate having conductive layers and insulating layers alternately laminated in a first direction; a plurality of memory pillars extending in the first direction within the laminate; and a structure body partitioning the plurality of memory pillars and extending in the first direction within the laminate. The structure body includes: a crystalline conductor extending in the first direction within the laminate; a first insulating film provided between the laminate and the crystalline conductor; a crystalline semiconductor film provided between the crystalline conductor and the first insulating film and containing silicon; and a second insulating film provided between the crystalline semiconductor film and a side surface of the crystalline conductor and containing silicon and oxygen. The crystalline conductor includes: a first crystalline region in contact with the crystalline semiconductor film and containing germanium; and a second crystalline region provided on the first crystalline region and in contact with the second insulating film in a second direction perpendicular to the first direction.

Each of n memory cells (150 etc.) provided in a semiconductor storage device (130a) has: a first resistance element (61p) and a first switch element (71p), which is controlled by a first word line (WL), connected in series between a bit line (BL) and a first source line (SL); a second resistance element (62n) and a second switch element (72n), which is controlled by the first word line (WL), connected in series between the bit line (BL) and a second source line (SLB); a third switch element (73p), which is controlled by a second word line (WLB), connected in series with the second resistance element (62n) between the bit line (BL) and the first source line (SL); and a fourth switch element (74n), which is controlled by the second word line (WLB), connected in series with the first resistance element (61p) between the bit line (BL) and the second source line (SLB).

A semiconductor storage device includes first and second chips. The second chip has a memory region and an edge seal region, and includes a plurality of edge seals, a first wiring layer at a first layer level on a first chip side of the edge seals, and a second wiring layer at a second layer level and contains tungsten. The first wiring layer includes first wirings at positions overlapping with inner edge seals, respectively, but not with an outermost edge seal and electrically connected to the inner edge seals, respectively. The second wiring layer includes second wirings that are provided at positions overlapping with the inner edge seals, respectively, but not with the outermost edge seal, and electrically connected to the inner edge seals, respectively, and a third wiring provided on an outer side of the second wirings, and electrically separated and spaced apart from the outermost edge seal.

The present disclosure provides a semiconductor memory device and a state transition detection circuit and method for its terminal resistor. The semiconductor memory device includes 1st to Mth input and output terminals for signals to be detected, and the state transition detection circuit includes: an i-th logic detection circuit for receiving a control logic signal of the i-th signal to be detected, performing a logical operation on the control logic signal of the terminal resistor of the i-th signal to be detected to generate an i-th detection result signal; a j-th detection mode control circuit, which is connected to the j-th input and output terminal of the signal to be detected and the i-th logic detection circuit, for receiving a mode detection control signal, and when the mode detection control signal is at a first level, outputting the i-th detection result signal through the j-th input and output terminal of the signal to be detected to determine the conversion state of the terminal resistor of the i-th signal to be detected; i and j are different. The time of the state switching of the terminal resistor can be accurately determined to the clock cycle level.

The present invention discloses a semiconductor memory device and a method for manufacturing the same, which includes a substrate; a plurality of buried word lines; and a plurality of storage node plugs. The substrate includes a plurality of active regions and shallow trench isolations. The buried word lines are buried in the substrate, passing through the shallow trench isolation or the active region. The storage node plugs are arranged on the substrate and contact the active region. The storage node plugs include a plurality of first plugs, each including an insulating material and a conductive material stacked in sequence from bottom to top. At least one active region of the semiconductor memory device contacts two first plugs at the same time; alternatively, the semiconductor memory device further includes a storage node pad, which physically contacts at least two first plugs. Therefore, the present invention is conducive to forming a semiconductor memory device with better component reliability.

The present disclosure provides a semiconductor storage device and a manufacturing method thereof, and relates to the technical field of semiconductor technology. The semiconductor storage device comprises: a nitrogen layer and a storage combination unit which are alternately stacked; wherein the outer layer of the storage combination unit is a first insulator, the inner side of the first insulator is a ring-shaped floating body, the inner side of the floating body is a ring-shaped channel region, and the inner side of the channel region is provided with a gate; at least one pair of through holes respectively penetrating the storage combination unit to break the ring-shaped floating body, channel region and gate; in at least one pair of through holes, one through hole is filled with a source electrode, and the source electrode only contacts the channel regions on both sides; and the other through hole is filled with a drain electrode, and the drain electrode only contacts the channel regions on both sides. The present disclosure can improve the integration of the semiconductor storage device.

A semiconductor device includes an upper electrode, a lower electrode, an oxide semiconductor including a first portion connected to the upper electrode, a connection portion, a second portion that is connected to a lower end portion of the first portion through the connection portion, has a diameter larger than that of the lower end portion of the first portion, and connected to the lower electrode, a gate insulating film surrounding a side surface of the first portion and has an outer diameter smaller than that of the second portion, a first insulating layer through which the first portion penetrates, a gate electrode which is provided below the first insulating layer and faces the first portion via the gate insulating film, the first portion penetrating through the gate electrode, and a second insulating layer provided below the gate electrode, wherein the connection portion is surrounded by the second insulating layer.

To provide a semiconductor storage device and a detection method which are capable of reducing the loss of valid memory cells and efficiently using the memory cells.SOLUTION: A nonvolatile memory 2 includes a plurality of planes P0 to P3, a sequencer 27, and a source line CELSRC. The sequencer 27 executes erasing sequence of repeatedly performing a plurality of loops including a set of erasing operation of erasing each data of a memory cell included in one erasing target block selected in each of the planes P0 to P3 and erasing verification operation of confirming whether or not data has been erased. Moreover, the sequencer 27, for each erasing target block, detects the presence or absence of current leakage from the source line CELSRC, determines based on results of the detection whether or not the erasing sequence is valid, and cancels the execution of the erasing sequence for the erasing target block determined not to be valid.SELECTED DRAWING: Figure 2