976 results about "Sense amplifier" patented technology

Technology is disclosed for reading memory cells having threshold switching selectors. A sense amplifier may have a set of capacitors that may be used to exchange charge with a sense node connected to the selected word line. A capacitor may be used to pull excess charge from the sense node or to provide charge to the sense node. A control circuit drives a current to the selected word line to charge up the selected word line to switch on the threshold switching selector of the selected memory cell. A capacitor may be connected to the selected word line when, or soon after, the threshold switching selector switches on. The capacitor may draw away excess charge to prevent a snapback current from flowing through the memory cell thereby preventing mis-reads. The capacitor may reduce read latency by speeding the rate of voltage change on a word line.

In an implementation, a device includes: a first inverter; a first sense amplifier connected to the first inverter; a first match line connected to the first sense amplifier; a first analog content addressable memory cell including: a first pull-down transistor; a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node; a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.

A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

A memory device includes a peripheral circuit structure and a cell array structure, in which the cell array structure overlaps the peripheral circuit structure in a first direction, in which the cell array structure includes a merged sub array in which at least four sub array regions are merged, in which the merged sub array comprises a memory cell region including: a plurality of first bit lines and a plurality of second bit lines; and a plurality of first word lines and a plurality of second word lines, in which the peripheral circuit structure comprises a merged bank in which at least four banks are merged, and in the merged bank comprises: a first bit line sense amplifier (BLSA), a second BLSA, a first sub word line driver (SWD), a second SWD, and in which a spare space is defined between the first bit lines and the second bit lines.

A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a plate line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the plate line of the memory cell connected to an unselected page.

In a matrix of SOT-MRAM cells, a first row is selected for writing and a second row is selected for reading. A first SOT-MRAM cell of the first row and a second SOT-MRAM of the second row are in a first column, while a third SOT-MRAM cell of the first row and a fourth SOT-MRAM of the second row are in a second column. The currents for writing the first SOT-MRAM cell and the third SOT-MRAM cell are in opposite direction. A first sense amplifier is configured to detect a voltage change on the first read bit line which is charged with a first read current in the second SOT-MRAM cell. A second sense amplifier is configured to detect a voltage change on the second read bit line which is discharged with a second read current in a fourth SOT-MRAM cell.

Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

The embodiment of the invention relates to the field of memories, and provides a sense amplifier which at least comprises a first transistor electrically connected between a first power supply node and a complementary read bit line, and the control end of the first transistor is connected to the control end of a third transistor; the second transistor is electrically connected between the second power supply node and the reading bit line, and the control end of the second transistor is connected to the control end of the fourth transistor; a third transistor electrically connected between the complementary read bit line and a third power supply node; a fourth transistor electrically connected between the read bit line and a fourth power supply node; the first calibration tube is connected between the complementary reading bit line and the control end of the third transistor; wherein the first power supply node is connected to a first power supply voltage through the first switching element; the second power supply node is connected to the first power supply voltage through the second switching element; the third power supply node is connected to a second power supply voltage through a third switching element; the fourth power supply node is connected to the second power supply voltage through a fourth switching element.

A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.

Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

Single (1 T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.

The present application relates to the field of semiconductor circuit design, and relates to a sense amplifier circuit and a data readout method, comprising: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; a first control MOS transistor for providing a bias voltage to the first PMOS transistor according to a control signal; a second control MOS transistor for providing a bias voltage to the second PMOS transistor according to a control signal; a first offset cancellation MOS transistor for electrically connecting an initial bit line to a first complementary readout bit line according to the offset cancellation signal; and a second offset cancellation MOS transistor for electrically connecting the initial complementary bit line to the first readout bit line according to the offset cancellation signal. Stable gate voltages are provided to the first and second PMOS transistors respectively via the first and second control MOS transistors, thereby stably eliminating offset noise in the sense amplifier circuit and avoiding voltage fluctuations on the bit lines and complementary bit lines.

Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

A memory device includes a first semiconductor layer and a second semiconductor layer arranged relative to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bit line and a complementary bit line coupled with the memory cell array, a first vertical conductive line coupled with the bit line, and a second vertical conductive line coupled with the complementary bit line. The second semiconductor layer includes a peripheral circuit, a bit line sense amplifier, first and second control lines coupled with the bit line sense amplifier, a third vertical conductive line coupled with the bit line sense amplifier, and a fourth vertical conductive line coupled with the bit line sense amplifier. The bit line sense amplifier includes at least one first transistor pair shared by at least one of the first control line and the second control line.

A semiconductor memory device may include a first chip including a first array matrix and a second array matrix adjacent to each other and including memory cells, and a second chip below the first chip, and including sense amplifiers configured to drive the memory cells, where first cell bit lines are in the first array matrix, and second cell bit lines are in the second array matrix, where first bit lines and first complementary bit lines are below the first array matrix, and second bit lines and second complementary bit lines are below the second array matrix, where the first bit lines and the second bit lines are connected to the first cell bit lines and the second cell bit lines, respectively, and where the first complementary bit lines and the second complementary bit lines are connected to the second cell bit lines and first cell bit lines, respectively.

A voltage generator including an LDO (low dropout) regulator that supplies a current to an internal voltage node of a sense amplification circuit as feedback control based on a voltage level of the internal voltage node; and a power switch circuit including a plurality of power switches each having one end connected to an external voltage and an opposite end connected to the internal voltage node, and that supplies the current to the internal voltage node as feed-forward control based on a known number of sense amplifiers to be activated. The voltage generator may efficiently supply current according to an operation mode of the sense amplification circuit.

A microelectronic device includes a control circuitry structure and a memory array structure bonded to the control circuitry structure. The control circuitry structure includes a control circuitry region including two sense amplifier (SA) sub-regions including SA circuitry, and two sub-word line driver (SWD) sub-regions including SWD circuitry. The two SA sub-regions horizontally extend between opposing boundaries of the control circuitry region in a first direction. The two SWD sub-regions are interposed between the two SA sub-regions in a second direction and individually include a central region adjacent a respective one of the opposing horizontal boundaries of the control circuitry region, and two arm regions at opposing ends of the central region in the second direction and respectively horizontally protruding, in the first direction, from the central region. The memory array structure includes an array region horizontally overlapping the control circuitry region of the control circuitry structure and including memory cells.

A memory device includes a first semiconductor layer and a second semiconductor layer disposed with respect to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bitline and a complementary bitline coupled with the memory cell array, a first vertical wire coupled with the bitline, and a second vertical wire coupled with the complementary bitline. The second semiconductor layer includes a peripheral circuit, a bitline sense amplifier, first and second control lines coupled with the bitline sense amplifier, a third vertical wire coupled with the bitline sense amplifier, and a fourth vertical wire coupled with the bitline sense amplifier. The bitline sense amplifier includes at least one first transistor pair that is shared by at least one of the first and second control lines.

A memory circuit includes a first memory cell operatively accessible through a first access line and a second access line; a first read pass-gate transistor and a second read pass-gate transistor coupled to the first access line and second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on a clock signal; and a second read enable control circuit configured to generate a second read enable signal. The first read enable signal selectively transitions to a different logic state based on a first sense enable signal. The second read enable signal is configured to activate or deactivate both the first and second read pass-gate transistors, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.

A semiconductor device may include: a cell area in which a plurality of memory cells arranged in a first direction, a second direction and a third direction are disposed, the first direction and the second direction being parallel to an upper surface of a substrate and intersecting, and the third direction being perpendicular to the upper surface of the substrate; and a peripheral circuit area in which a word line driver connected to the plurality of memory cells through a plurality of word lines, a sense amplifier circuit connected to the plurality of memory cells through a plurality of bit lines, and a source line driver connected to the plurality of memory cells through a plurality of source lines, are disposed.

The invention discloses a numerical comparator which comprises a storage unit array, storage units of the storage unit array are connected through word lines and bit lines to form an array, and first numbers participating in comparison are sequentially stored in the storage units of different word lines on the same bit line according to a bit sequence. The different word lines on the same bit line form a first word line group, and a second number participating in comparison is sequentially stored in a memory unit of a word line, which is different from any word line in the first word line group, on the same complementary bit line corresponding to the bit line according to a bit sequence. The word lines different from any word line in the first word line group form a second word line group, and the bit lines and the complementary bit lines are connected to the input ends of the sensing amplifiers corresponding to the bit lines. And the memory unit is a DRAM (Dynamic Random Access Memory) unit storage unit. The first number and the second number are binary numbers.

A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction in plan view on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, and in a page read operation, a first refresh operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a second refresh operation of decreasing the number of positive holes in the semiconductor body of a memory cell for which page writing has not been performed are performed and a third refresh operation for a memory cell, in a page, in which the logical “1” data is stored is performed by using latch data in a sense amplifier circuit.

A memory includes a local control circuitry that manages refresh transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts refresh transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides refresh transactions into phases and periods based on whether the refresh transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt refresh transactions with access transactions in a manner that minimizes access interference.

A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.

A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit including sub peripheral circuits respectively disposed under the sub cell arrays. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. The wordlines extend in a row direction and are arranged in a column direction. The bitlines extend in the column direction and are arranged in the row direction. Each sub peripheral circuit is divided into first and second column edge regions and a central region. The central region is between the first column edge region and the second column edge region. A sense amplifier region including a plurality of bitline sense amplifiers are in at least one of the first column edge region and the second column edge region. A wordline driver region including a plurality of sub wordline drivers is disposed in the central region.

A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) circuit design, in particular to a sense amplifier based on flip point and current mirror compensation, a reading circuit and a chip. The invention designs a sensitive amplifier based on flip point and current mirror compensation. The sensitive amplifier comprises 11 NMOS (N-channel Metal Oxide Semiconductor) tubes M1-M11 and two PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P2. Corresponding control logic is provided in cooperation with the provided sensitive amplifier, so that a pre-charging stage, an offset elimination stage, an offset compensation stage, a charge sharing and reference voltage amplification stage and an induction amplification stage are designed when the sensitive amplifier reads the DRAM storage unit. The sensitive amplifier provided by the invention has the advantages that the number of elements is small, the circuit area is not greatly increased, the high sensing yield is ensured, the offset voltage index is greatly reduced, and the reading speed is increased.

Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

This application provides a ferroelectric random access memory and a terminal, and relates to the field of storage technologies, to improve strength of a read signal and read efficiency in a read phase, and reduce an area of the ferroelectric random access memory. The ferroelectric random access memory includes bit lines, an ith plate line, a multiplexer, a sense amplifier, and a plurality of ferroelectric memory cells. Each ferroelectric memory array of the plurality of ferroelectric memory cells includes m columns of ferroelectric memory cells arranged in array, and the ferroelectric memory cell includes one ferroelectric capacitor and one first transistor. In any row, a ferroelectric capacitor of the (m*n+i)th column of ferroelectric memory cells is electrically connected to the ith plate line; and in the read phase, each plate line in the ith plate line inputs a high level to the ferroelectric memory cell in a time division manner, where m is an integer greater than or equal to 2, n is an integer greater than or equal to 0, and i is a positive integer less than or equal to m. Each column of ferroelectric memory cells are electrically connected to one of the bit lines, and every m bit lines are electrically connected to a same multiplexer. Each sense amplifier is electrically connected to one multiplexer.