91 results about "Sense amplifier" patented technology

A sense amplifier and a memory device including the sense amplifier are provided. The sense amplifier includes: a first PMOS transistor and a first NMOS transistor connected in series between a power supply voltage and an input node; a second NMOS transistor connected between the input node and ground; a second PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor connected in series between the power supply voltage and ground; a first switch connected between a first node and a second node, the first node being between the first PMOS transistor and the first NMOS transistor, and the second node being between the second PMOS transistor and the third NMOS transistor; and a second switch connected between the second node and an output node.

Systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. An apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. A first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. A second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. Control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.

A system and technique for buffering data locally within a memory device to allow access to data associated with a plurality of different rows within the memory device. The memory device includes a storage bank circuit having memory cells and a sense amplifier circuit coupled to the storage bank circuit. The memory device also includes a buffer circuit coupled to an output of the sense amplifier circuit. In addition, the memory device includes a selection circuit. The selection circuit receives a first data signal from the sense amplifier circuit and a second data signal from the buffer circuit and outputs a selected one of the first data signal and the second data signal.

A system to generate true random numbers includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array. The hash generator receives a null-read result from the null-read operation and outputs a partial true random number based on the null-read result.

A memory device includes a memory cell coupled to a word line and a bit line, a row driver to drive the word line to a pre-charge level, a column driver to drive the bit line to a first target level, a sense amplifier to sense a first sense level of the word line after the first target level is applied to the memory cell, and a read control circuit to control the column driver to selectively apply a second target level different from the first target level to the memory cell based on the first sense level sensed by the sense amplifier.

A semiconductor memory device includes: a memory cell array located in a first layer and including a word line, a cell bit line, and a memory cell located in a region where the word line and the cell bit line are crossed; and a bit line sense amplifier located in a second layer, different from the first layer. The bit line sense amplifier is connected to a bit line that is connected to the cell bit line and to a complementary bit line corresponding to the bit line. The bit line sense amplifier detects data stored in the at least one memory cell. Each of the at least one cell bit line is segmented into two or more portions, and the two or more portions are respectively connected to the bit line and the complementary bit line connected to the bit line sense amplifier.

The application discloses a reading method and reading circuit of FRAM, which comprises the following steps: the voltage signals on the bit lines of the storage unit and the reference unit in the FRAM array are converted into corresponding voltage sizes by the respective differential circuits, and then are input into a sensing amplifier, and the voltage difference is read out by the sensing amplifier. The reading circuit using the method comprises two differential circuit modules and a sensing amplifier; the differential circuit module is used for differentiating the voltage signals on the bit lines with respect to time, so as to obtain the change speed of the voltage signals on the bit lines with respect to time; and the sensing amplifier is used for amplifying the signal difference after the processing of the differential circuit module, and finally converting the information stored in the storage unit into '0' and '1'; the method has the advantages of new feasibility, fast reading time, low power consumption and the like.

A memory and its access method, and an electronic device, are disclosed. The memory includes at least one memory array, multiple bit lines extending along a third direction perpendicular to a substrate, and multiple common bit lines extending along a second direction parallel to the substrate. The memory array includes multiple memory cells arrayed along the first and second directions parallel to the substrate, and multiple word lines extending along the first direction. Bit lines in the same column distributed along the second direction are connected to the same common bit line, bit lines in different columns are connected to different common bit lines, and each bit line is connected to the common bit line through a first gating sub-circuit. The first gating sub-circuit is also connected to a first gating control line, and the first gating sub-circuit is configured to connect or disconnect the bit lines and the common bit lines according to the control of the first gating control line. The solution provided in this embodiment, where multiple bit lines are connected to a single common bit line, can reduce the number of sense amplifiers used in the memory.

The problem is to apply a high voltage to a storage element other than a write target without making a sense amplifier module high voltage. The solution is that the semiconductor storage device of the embodiment has: a laminate in which a plurality of first insulating layers and a plurality of second insulating layers are alternately laminated; a plurality of channel layers respectively provided in the plurality of first insulating layers and extending in a first direction along the plurality of first insulating layers; a word line extending within the laminate in a laminating direction of the laminate and intersecting the plurality of channel layers; a plurality of bit lines respectively connected to the plurality of channel layers; and a plurality of boost circuits respectively provided in the plurality of first insulating layers and respectively connected to the plurality of bit lines.

Embodiments of the present application relate to a memory device that provides multiple bias voltages using a dynamic latch. The memory device includes a sense amplifier (SA) latch coupled to a sense node. A dynamic latch (DL) is connected to the SA latch and coupled to the sense node. A sense line includes the sense node and is selectively connected to the SA latch, the DL, and a bit line coupled to a string of memory cells. Control logic is coupled to the SA latch and the DL and causes a preprogrammed verify voltage to boost the sense node; and in response to detecting a high bit value stored in the SA latch, causes a voltage to turn on a DL set transistor so that either a first bias voltage or a second bias voltage is stored at a latch transistor. The first bias voltage can be used for slow programming of a selected memory cell and the second bias voltage can be used for fast programming of the selected memory cell.

The application provides a data reading circuit of an MRAM chip, comprising: a to-be-tested storage unit, a first gating transistor connected in series with the to-be-tested storage unit, a reference unit, a second gating transistor connected in series with the reference unit, and a readout amplifier, wherein the reference unit has three optional reference resistance branches, including a working mode branch, a first test mode branch and a second test mode branch, the working mode branch is used for reading data of the to-be-tested storage unit, the first test mode branch is used for screening out fixed failure units and high-resistance state out-of-range failure units with an open-circuit failure type, and the second test mode branch is used for screening out fixed failure units and low-resistance state out-of-range failure units with a short-circuit failure type.

A sense amplifier circuit includes first, second inputs coupled to first, second memory sensing nodes, respectively. A sensing circuit operates to sense a differential signal between the first, second inputs. A first boosting capacitor has a first terminal coupled to the first input and a second terminal coupled to a switchable node. A second boosting capacitor has a first terminal coupled to the second input and a second terminal coupled to the switchable node. Control circuitry operates, responsive to a bitline boost activation signal having a first value, to couple the first terminals of the first, second boosting capacitors to a regulated supply voltage and drive the switchable node to ground. Responsive to the bitline boost activation signal having a second value, the first terminals of the first, second boosting capacitors are decoupled from the regulated supply voltage and the switchable node is driven to the regulated supply voltage.

A memory die is bonded to a logic die on a wafer by die-to-wafer bonding. The logic die may include surface metal pads having first planar horizontal surfaces located within a horizontal plane including a bonding interface and located within an area not overlapping with an area of the memory die. Alternatively or additionally, electrically conductive paths may be present between sense amplifiers in the logic die and first bit lines in the memory die. The electrically conductive paths may include second bit lines located in the logic die and laterally extending from within an area overlapping with the area of the memory die to an area not overlapping with the area of the memory die in a plan view. One or more memory die can be attached to the logic die.

Various aspects include a circuit having single-rail static operating global data lines for a synchronous random access memory (SRAM). The circuit can include one or more auto tri-state drivers coupled to the single-rail static operating global data lines of the SRAM. The circuit can include one or more sense amplifiers coupled to the one or more auto tri-state drivers. The circuit can include latches coupled to the single-rail static operating global data lines. Some embodiments can include a method for operating global data lines of a multi-array SRAM. The method can include connecting single-rail static operating global data lines of the SRAM to one or more auto tri-state drivers of the SRAM, and operating the one or more auto tri-state drivers without a strobe signal. The method can include operating the single-rail global data lines of the SRAM with a static signal.

In some examples, a method for reducing offset in a sense amplifier of multiple sense amplifiers comprises identifying, from the multiple sense amplifiers, a sense amplifier associated with an offset characteristic, selecting, from multiple bit lines, at least one bit line pair associated with the identified sense amplifier for de-offsetting, and applying a pulsed signal to the word line to initiate a discharge that adjusts a voltage on the selected bit line, whereby to reduce the offset in the sense amplifier.

An amplifier circuit for writing to or reading from a memory cell with reduced power consumption is provided. The amplifier circuit includes a first to a sixth switch and a sense amplifier. The sense amplifier is latching type and includes a first input / output terminal and a second input / output terminal. The first terminal of the first switch is electrically connected to the first terminal of the second switch, and the second terminal of the second switch is electrically connected to the first terminal of the third switch and the first input / output terminal of the sense amplifier. The first terminal of the fourth switch is electrically connected to the first terminal of the fifth switch, and the second terminal of the fifth switch is electrically connected to the first terminal of the sixth switch and the second input / output terminal of the sense amplifier. The control terminals of the first and fifth switches are respectively electrically connected to a first wiring, and the control terminals of the third and sixth switches are respectively electrically connected to a second wiring.

The present application relates to the technical field of DRAM circuit design, and particularly relates to a DRAM sensitive amplifier based on IO active compensation, a reading circuit and a module. The present application adds four transistors N6, N7, N8 and N9 in the traditional BLSA, the source of N6 and N7 is connected to SAN, the gate of N6 is connected to BLT, the drain of N6 is connected to the drain of N8, the gate of N7 is connected to BLB, the drain of N7 is connected to the drain of N9, the gate of N8 and N9 is connected to pre-column selection signal PCSL, and the source of N8 is connected to transmission line IOB; the source of N9 is connected to transmission line IOT. Before data transmission, the voltage of one of IOB or IOT transmitting 0 data is pulled down, so that the voltage difference between BLT and BLB is lower than the offset voltage of the sensitive amplifier, and data flipping and transmission of error data are avoided.

A semiconductor device includes a first layer including memory cells connected to bit lines and word lines, wherein each memory cell includes a cell transistor and a cell capacitor; a second layer on the first layer and including a row decoder connected to the word lines, a sense amplifier circuit connected to the bit lines, and a column decoder configured to determine a selected bit line among the bit lines; and a third layer on the second layer, the third layer including a logic circuit configured to control the row decoder, the sense amplifier circuit, and the column decoder, and an input / output interface configured to transmit and receive a signal to and from an external device, wherein the second layer includes a computing circuit configured to perform at least one computation, the at least one computation based on at least one of input data received by the input / output interface and read data read from the memory cells.

A request to perform a program operation to program a set of memory cells on a memory device comprising a sense amplifier circuit is received. A defect indicator associated with the set of memory cells is determined to satisfy a defect condition. A modified sensing time period, exceeding a default sensing time period, is determined based on the defect indicator. The program operation is performed using the modified sensing time period during a program verify phase of the program operation.

A semiconductor memory device includes bit lines, memory cells that are respectively connected to the bit lines, sense amplifier units that are respectively connected to the bit lines, and each of which includes m latch circuits, and a logic control circuit configured to input data to the m latch circuits and control a write operation on each of the memory cells using the data input to the m latch circuits. The logic control circuit executes an operation to write n bits to each of the memory cells, where n is 2 or more and greater than m, by executing a plurality of write operations, including a first write operation executed on the memory cells by inputting first m bits of data to the m latch circuits, and a second write operation executed on the memory cells by inputting second m bits of data to the m latch circuits.

A memory is provided that is includes a sense amplifier for sensing a bit during a write operation. The memory further includes a selective negative bit line boost enable circuit that uses the sense amplifier during a write operation to compare a charged bit line to a reference voltage. Depending upon the comparison, the sense amplifier either asserts or de-asserts a negative bit line boost enable signal.

A memory includes a local control circuitry that manages scrub transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts scrub transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides scrub transactions into phases and periods based on whether the scrub transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt scrub transactions with access transactions in a manner that minimizes access interference.

The present invention relates to a read sense amplifier circuit and system that enables read operations over a wide power range by using a low reference resistor and securing gain through a two-stage operational amplifier circuit, and can also detect low fuse resistance to secure a sensing resistance margin and improve yield, and a memory cell read method using the same. The above read sense amplifier circuit comprises a current mirror circuit stage that receives a reference current from an external bias circuit and mirrors the reference current through a plurality of paths, a reference resistor stage including a reference resistor and an NMOS transistor that activates the reference resistor, a precharge circuit stage that receives a precharge signal and precharges a reference bit line connected to the reference resistor based on the precharge signal, an amplifier circuit stage that senses cell data for a cell corresponding to the selected fuse using the voltage difference between the resistance of the selected fuse corresponding to the selected cell and the reference resistor, and a buffer circuit stage that outputs the sensed data, wherein the amplifier circuit stage includes a plurality of PMOS transistors, and at least one input stage of the plurality of PMOS transistors of the amplifier circuit stage may be electrically connected to a connection resistor.

The present invention relates to low leakage sensing circuits, memory circuits including low leakage sensing circuits, and methods. A sensing circuit for a memory circuit includes sensing amplifiers that detect a difference in voltage levels on complementary bit lines during a read operation. Unlike sensing amplifiers with built-in tail devices that cause significant leakage, the sensing circuit includes a common tail device for all of the sensing amplifiers. To ensure that the tail device has sufficient drive strength for each sensing amplifier to perform voltage difference detection, the sensing circuit also includes a sensing signal generation and boost circuit (SSG&B circuit) that generates a sensing mode control signal (SEN) that controls the on / off state of the tail device and further boosts the SEN to increase drive current when appropriate. The use of a common tail device and the SSG&B circuit reduces leakage from the sensing circuit during a precharge mode of operation without sacrificing performance during a read mode of operation. Related method embodiments are also disclosed herein.

A semiconductor device may include: a cell area in which a plurality of memory cells arranged in a first direction, a second direction and a third direction are disposed, the first direction and the second direction being parallel to an upper surface of a substrate and intersecting, and the third direction being perpendicular to the upper surface of the substrate; and a peripheral circuit area in which a word line driver connected to the plurality of memory cells through a plurality of word lines, a sense amplifier circuit connected to the plurality of memory cells through a plurality of bit lines, and a source line driver connected to the plurality of memory cells through a plurality of source lines, are disposed.

The application discloses a memory and a data migration method, and relates to the storage field, which can shorten the time for realizing data migration between adjacent storage unit subarrays in DRAM in-memory computing, thereby reducing the power consumption of the memory and improving the efficiency. The memory comprises a row of interval distributed sense amplifiers and switch units between adjacent storage unit subarrays; between the adjacent storage unit subarrays, in every two adjacent columns of bit lines, a sense amplifier is arranged on one column of bit lines, and a switch unit is connected in series on the other column of bit lines; wherein, on the same column of bit lines, the sense amplifiers and the switch units are alternately arranged between the storage unit subarrays.

A system includes a memory device and a memory replica. The memory device includes a plurality of memory cell, an input-output multiplexer, an input-output sense amplifier, and a storage element. The input-output multiplexer selects one of the memory cells in response to a select signal. The input-output sense amplifier generates a data output signal representing a bit stored in the selected one of the memory cells. The storage element latches the data output signal in response to a data latch signal and outputs a bit that corresponds to the data output signal. The memory device replica mimics the behavior of the memory device and generates the data latch signal.

This invention provides a sensing circuit, a memory device, and a method for operating the memory. It replaces the sensing amplifier in existing technologies with a multi-value sensing amplifier. During sensing, there is no need to switch word line voltages. The multi-value sensing amplifier can receive the sensing current, reference recovery current, and reference read current, and compare the sensing current with these two currents. This provides two comparison results in a single sensing operation. Based on these results, it can be verified whether the memory cell is a problematic cell. The problematic cell can then be programmed to restore it to normal operation. This significantly reduces the recovery operation time and greatly improves its efficiency. The method is simple, effective, and easy to implement. It can be implemented in both memory recovery and read operations without requiring additional power-on time and solves the coverage problem of existing methods.

A memory die is bonded to a logic die on a wafer by die-to-wafer bonding. The logic die may include surface metal pads having first planar horizontal surfaces located within a horizontal plane including a bonding interface and located within an area not overlapping with an area of the memory die. Alternatively or additionally, electrically conductive paths may be present between sense amplifiers in the logic die and first bit lines in the memory die. The electrically conductive paths may include second bit lines located in the logic die and laterally extending from within an area overlapping with the area of the memory die to an area not overlapping with the area of the memory die in a plan view. One or more memory die can be attached to the logic die.

This application discloses a memory circuit. Each row of cells includes M+1 bit cells. First to Mth bit cells normally store M-bit data; an (M+1)th bit cell stores opposite data of an ith bit cell; each row of sense amplifiers includes M sense amplifiers; one positive input end of an ith sense amplifier is connected with an output end of the ith bit cell; one negative input end of the ith sense amplifier is connected with an output end of the (M+1)th bit cell; two positive input ends of a jth sense amplifier are connected with an output end of a jth bit cell; two negative input ends of the jth sense amplifier are respectively connected with an output end of the (M+1)th bit cell and an output end of the ith bit cell. The memory circuit can improve data retention and increase the utilization rate of the cells.