728 results about "Sense amplifier" patented technology

In an implementation, a device includes: a first inverter; a first sense amplifier connected to the first inverter; a first match line connected to the first sense amplifier; a first analog content addressable memory cell including: a first pull-down transistor; a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node; a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.

The embodiment of the invention relates to the field of memories, and provides a sense amplifier which at least comprises a first transistor electrically connected between a first power supply node and a complementary read bit line, and the control end of the first transistor is connected to the control end of a third transistor; the second transistor is electrically connected between the second power supply node and the reading bit line, and the control end of the second transistor is connected to the control end of the fourth transistor; a third transistor electrically connected between the complementary read bit line and a third power supply node; a fourth transistor electrically connected between the read bit line and a fourth power supply node; the first calibration tube is connected between the complementary reading bit line and the control end of the third transistor; wherein the first power supply node is connected to a first power supply voltage through the first switching element; the second power supply node is connected to the first power supply voltage through the second switching element; the third power supply node is connected to a second power supply voltage through a third switching element; the fourth power supply node is connected to the second power supply voltage through a fourth switching element.

A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.

The present application relates to the field of semiconductor circuit design, and relates to a sense amplifier circuit and a data readout method, comprising: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; a first control MOS transistor for providing a bias voltage to the first PMOS transistor according to a control signal; a second control MOS transistor for providing a bias voltage to the second PMOS transistor according to a control signal; a first offset cancellation MOS transistor for electrically connecting an initial bit line to a first complementary readout bit line according to the offset cancellation signal; and a second offset cancellation MOS transistor for electrically connecting the initial complementary bit line to the first readout bit line according to the offset cancellation signal. Stable gate voltages are provided to the first and second PMOS transistors respectively via the first and second control MOS transistors, thereby stably eliminating offset noise in the sense amplifier circuit and avoiding voltage fluctuations on the bit lines and complementary bit lines.

A voltage generator including an LDO (low dropout) regulator that supplies a current to an internal voltage node of a sense amplification circuit as feedback control based on a voltage level of the internal voltage node; and a power switch circuit including a plurality of power switches each having one end connected to an external voltage and an opposite end connected to the internal voltage node, and that supplies the current to the internal voltage node as feed-forward control based on a known number of sense amplifiers to be activated. The voltage generator may efficiently supply current according to an operation mode of the sense amplification circuit.

A microelectronic device includes a control circuitry structure and a memory array structure bonded to the control circuitry structure. The control circuitry structure includes a control circuitry region including two sense amplifier (SA) sub-regions including SA circuitry, and two sub-word line driver (SWD) sub-regions including SWD circuitry. The two SA sub-regions horizontally extend between opposing boundaries of the control circuitry region in a first direction. The two SWD sub-regions are interposed between the two SA sub-regions in a second direction and individually include a central region adjacent a respective one of the opposing horizontal boundaries of the control circuitry region, and two arm regions at opposing ends of the central region in the second direction and respectively horizontally protruding, in the first direction, from the central region. The memory array structure includes an array region horizontally overlapping the control circuitry region of the control circuitry structure and including memory cells.

A semiconductor device may include: a cell area in which a plurality of memory cells arranged in a first direction, a second direction and a third direction are disposed, the first direction and the second direction being parallel to an upper surface of a substrate and intersecting, and the third direction being perpendicular to the upper surface of the substrate; and a peripheral circuit area in which a word line driver connected to the plurality of memory cells through a plurality of word lines, a sense amplifier circuit connected to the plurality of memory cells through a plurality of bit lines, and a source line driver connected to the plurality of memory cells through a plurality of source lines, are disposed.

The invention discloses a numerical comparator which comprises a storage unit array, storage units of the storage unit array are connected through word lines and bit lines to form an array, and first numbers participating in comparison are sequentially stored in the storage units of different word lines on the same bit line according to a bit sequence. The different word lines on the same bit line form a first word line group, and a second number participating in comparison is sequentially stored in a memory unit of a word line, which is different from any word line in the first word line group, on the same complementary bit line corresponding to the bit line according to a bit sequence. The word lines different from any word line in the first word line group form a second word line group, and the bit lines and the complementary bit lines are connected to the input ends of the sensing amplifiers corresponding to the bit lines. And the memory unit is a DRAM (Dynamic Random Access Memory) unit storage unit. The first number and the second number are binary numbers.

A memory includes a local control circuitry that manages refresh transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts refresh transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides refresh transactions into phases and periods based on whether the refresh transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt refresh transactions with access transactions in a manner that minimizes access interference.

A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) circuit design, in particular to a sense amplifier based on flip point and current mirror compensation, a reading circuit and a chip. The invention designs a sensitive amplifier based on flip point and current mirror compensation. The sensitive amplifier comprises 11 NMOS (N-channel Metal Oxide Semiconductor) tubes M1-M11 and two PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P2. Corresponding control logic is provided in cooperation with the provided sensitive amplifier, so that a pre-charging stage, an offset elimination stage, an offset compensation stage, a charge sharing and reference voltage amplification stage and an induction amplification stage are designed when the sensitive amplifier reads the DRAM storage unit. The sensitive amplifier provided by the invention has the advantages that the number of elements is small, the circuit area is not greatly increased, the high sensing yield is ensured, the offset voltage index is greatly reduced, and the reading speed is increased.

Semiconductor devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device comprises a memory array structure and a peripheral circuit structure connected with the memory array structure. The memory array structure comprises a transistor layer comprising a plurality of arrays of vertical transistors, a storage layer comprising a plurality of arrays of capacitors coupled with the vertical transistors, a plurality of bit lines coupled with the vertical transistors, and a first interconnection layer comprising a first interconnection structure connected with the plurality of bit lines, and a second interconnection structure disconnected with the plurality of bit lines and connected to a common electrical node. The peripheral circuit structure comprises a second interconnection layer comprising a third interconnection structure connected with the first interconnection structure, and a sense amplifier circuit connected with the third interconnection structure.

A memory circuit includes a memory cell, a bit line, a bit line bar, a pass-gate transistor coupled to the memory cell and the bit line, a sense amplifier coupled to the bit line, the bit line bar and the pass-gate transistor, and a pre-charge circuit coupled to the first node, and configured to pre-charge the first node to a pre-charge voltage in response to a pre-charge control signal. The sense amplifier includes a first path between the bit line and the bit line bar. The first path includes a first isolation transistor configured to receive an isolation control signal, and being coupled between the bit line and a first node, and a first inverter configured to receive a sense amplifier enable signal, and being coupled between a second node and a third node.

Systems and methods implementing an improved DVCS amplifier are described. The integrated circuit can include a controller. The integrated circuit can further include an amplifier configured to measure a common mode voltage across a capacitor of a switching converter. The integrated circuit can include a circuit configured to receive a differential input being provided to the amplifier. Based on the differential input, the circuit can further be configured to maintain the common mode voltage to regulate the amplifier within an operating range of the amplifier.

To provide a semiconductor storage device for storing data by accumulating majority carriers in an electrically floating body of a MOSFET.SOLUTION: In a memory device using a semiconductor device, plate lines PLL0, PLR0 capacitively coupled to floating bodies of memory cells MCL, MCR are wired in parallel with word lines WLL0, WLR0 separately for each word line, and an erase operation of majority carriers is executed simultaneously along the word lines by applying a voltage to the plate lines. In the refresh operation, after the data along the selected word line is read and latched by the sense amplifier S / A, the bit lines BLL and BLR are separated from the sense amplifier to once erase the majority carriers all together from the floating bodies of the cells on the selected word line, and the majority carriers are injected into the cells in which a large number of majority carriers are originally stored depending on the state of the sense amplifier. In addition, the write operation includes an operation of simultaneously extracting majority carriers from the selected cell and simultaneously writing data to the sense amplifier from the outside.SELECTED DRAWING: Figure 4

Some embodiments include an integrated assembly having a memory array over a substrate. The memory array includes a three-dimensional arrangement of memory cells. A sense amplifier is associated with the substrate and directly below the memory array. A vertically extending digit line passes through the arrangement of memory cells and is coupled with the sense amplifier. Some embodiments include an integrated assembly having a memory bank containing 64 memory data blocks arranged in a 16x4 configuration. Some embodiments include an integrated assembly having a memory bank containing 512 megabytes divided among 64 memory data blocks, each memory data block having 8 megabytes. The 64 memory data blocks are arranged in a configuration having a plurality of rows, each row containing two or more of the memory data blocks.

A sense amplifier and a memory device including the sense amplifier are provided. The sense amplifier includes: a first PMOS transistor and a first NMOS transistor connected in series between a power supply voltage and an input node; a second NMOS transistor connected between the input node and ground; a second PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor connected in series between the power supply voltage and ground; a first switch connected between a first node and a second node, the first node being between the first PMOS transistor and the first NMOS transistor, and the second node being between the second PMOS transistor and the third NMOS transistor; and a second switch connected between the second node and an output node.

A compare circuitry that can be implemented in a memory circuit includes: selection logic coupled to a sense amplifier of the memory circuit, the selection logic structured to receive a sense amplifier enable signal, a column output from the sense amplifier, and a column output bar from the sense amplifier, wherein the selection logic is structured to pass through the column output and the column output bar when the sense amplifier enable signal is active and hold the column output and the column output bar at a same value when the sense amplifier enable signal is inactive; and an XNOR gate structured to receive the column output and the column output bar passed through the selection logic, a data input, and a data input bar and output a bit compare output.

Disclosed are devices including threshold-voltage compensated sense amplifiers and methods of compensation thereof. Example threshold-voltage compensated sense amplifiers according to the present disclosure include circuitry for providing threshold-voltage compensation, such as an isolation transistor and at least one pre-charge transistor.

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and / or constant data from the host. The memory controller is configured to write the resolved instructions and / or constant data in parallel to a plurality of locations the memory device.

Systems and methods for sense amplifier power reduction are disclosed including controlling a supply voltage to a sense amplifier through different periods of operation, including providing a first supply voltage to the sense amplifier during an activation period and a second supply voltage to the sense amplifier lower than the first supply voltage during a precharge period to reduce power consumption of the sense amplifier. A voltage supply to a memory cell can be limited to the second supply during the precharge period to reduce a potential voltage stored at the memory cell, increasing memory cell retention.

Methods, systems, and devices for a counter-based sense amplifier method for memory cells are described. The described techniques provide for a memory system to store, in a counter associated with an array of memory cells, a value indicating a quantity of memory cells in the array having a predetermined logic value. The memory system may perform a read operation to read the data stored in the array of memory cells by applying a ramping bias voltage and may count the quantity of memory cells having the predetermined logic value during the read operation. The memory system may stop the read operation when the memory system identifies a quantity of memory cells having the predetermined logic value that is equal to the value stored to the counter.

A ferroelectric memory device includes: a ferroelectric memory cell connected between a bit line and a plate line and controlled by a word line; a row decoder configured to activate the word line; a board line voltage generator configured to provide a ground voltage to the board line during a pre-charge period and provide a first voltage to the board line in response to activation of the word line; and a sense amplifier configured to amplify a voltage of the bit line to a second voltage higher than the first voltage during a sensing operation.

The invention relates to a memory including a sense amplifier and a method of operating the memory. The operating method of the memory may include: receiving a first activation command and a first row address; initiating a first mismatch compensation operation in a sense amplifier array for a normal cell array corresponding to the first row address and in a redundant sense amplifier array for a redundant cell array corresponding to the normal cell array; determining whether to access the normal cell array based on the first row address and the repair information; in response to a determination to access the normal cell array, deactivating the redundant sense amplifier array for the redundant cell array; activating a word line of the normal cell array corresponding to the first row address; and sensing and amplifying data of a memory cell corresponding to the activated word line by a sense amplifier array for the normal cell array.

A resistive memory device performs a selective write operation. Included in the resistive memory device are at least one memory cell, a reference resistance circuit whose resistance value is adjusted, a sense amplifier configured to read data stored in the at least one memory cell by comparing a resistance value of the at least one memory cell with a resistance value of the reference resistance circuit, a write driver configured to program write requested data into the at least one memory cell, and a selective write controller. The selective write controller performs a read-before-write operation by adjusting the resistance value of the reference resistor circuit according to the write data during the selective write operation.

Systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. An apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. A first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. A second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. Control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.

A semiconductor storage device includes memory cells and a sense amplifier circuit. Each of the memory cells includes p-type drive transistors, n-type load transistors, and p-type access transistors connected to a bit line pair. The sense amplifier circuit includes p-type transistors and n-type transistors.

Systems, devices, methods, and circuits for managing failures of in-memory computing (IMC) devices. An example memory device includes: a plurality of memory units and a circuitry configured for execution of a computing instruction in one or more memory units. A memory unit includes: a memory cell array and a peripheral circuit including a plurality of subcircuits coupled to the memory cell array. Each subcircuit includes: one or more internal sense amplifiers, one or more latches, and one or more multipliers. The circuitry is configured to: determine whether a subcircuit is defective by determining whether at least one of an internal sense amplifier, a latch, or a multiplier in the subcircuit is defective using an external sense amplifier external to the memory unit, and in response to determining that the subcircuit is defective, perform one or more corresponding actions including replacing the subcircuit with a redundant subcircuit in the peripheral circuit.

The present invention efficiently routes bit lines. In a semiconductor memory device according to an embodiment, a second bit line includes: a second inter-cell-module wiring electrically connected to a second memory cell and extending in a first direction from a position overlapping the second memory cell in a vertical direction toward a sense amplifier module; and a second in-module wiring that is parallel to the first in-module wiring in the first direction and extends in the second direction at a position close to the first in-module wiring, and that electrically connects the second inter-cell-module wiring and the second sense amplifier cell.

An in-memory computing (IMC) accelerator using a high-density operation circuit and a low-power sense amplifier as a peripheral circuit includes a plurality of dynamic random-access memory (DRAM) banks each including a pair of cell arrays, a data supply logic, a memory, and a controller for IMC, a global SRAM, and a top-level controller, wherein the cell array includes a plurality of subarrays, each of the subarrays includes a DRAM array including a big array and a little array, and an arithmetic circuit configured to perform an operation, and the arithmetic circuit includes a sense amplifier configured to amplify a bit line voltage difference, and a compact multiply-accumulate (MAC)-single instruction multiple data (SIMD) unit (CMSU) for an MAC operation and an SIMD operation, so that functionality of an in-memory operation is diversified.