1258 results about "Sense amplifier" patented technology

Technology is disclosed for reading memory cells having threshold switching selectors. A sense amplifier may have a set of capacitors that may be used to exchange charge with a sense node connected to the selected word line. A capacitor may be used to pull excess charge from the sense node or to provide charge to the sense node. A control circuit drives a current to the selected word line to charge up the selected word line to switch on the threshold switching selector of the selected memory cell. A capacitor may be connected to the selected word line when, or soon after, the threshold switching selector switches on. The capacitor may draw away excess charge to prevent a snapback current from flowing through the memory cell thereby preventing mis-reads. The capacitor may reduce read latency by speeding the rate of voltage change on a word line.

In an implementation, a device includes: a first inverter; a first sense amplifier connected to the first inverter; a first match line connected to the first sense amplifier; a first analog content addressable memory cell including: a first pull-down transistor; a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node; a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.

A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

A memory device that operates at high speed is provided.The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

A memory device includes a peripheral circuit structure and a cell array structure, in which the cell array structure overlaps the peripheral circuit structure in a first direction, in which the cell array structure includes a merged sub array in which at least four sub array regions are merged, in which the merged sub array comprises a memory cell region including: a plurality of first bit lines and a plurality of second bit lines; and a plurality of first word lines and a plurality of second word lines, in which the peripheral circuit structure comprises a merged bank in which at least four banks are merged, and in the merged bank comprises: a first bit line sense amplifier (BLSA), a second BLSA, a first sub word line driver (SWD), a second SWD, and in which a spare space is defined between the first bit lines and the second bit lines.

A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a plate line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the plate line of the memory cell connected to an unselected page.

There is provided a memory device including a processing-in-memory (PIM) dynamic random access memory (DRAM) die(s) and PIM-high bandwidth memory (HBM) devices. The memory device includes a core peripheral circuit structure including a bank core circuit including a row decoder and a sense amplifier of each of a plurality of banks, and a cell array structure disposed on the core peripheral circuit structure. The bank core circuit includes a plurality of sub core circuits correspondingly connected to the plurality of sub cell blocks, respectively. Each of the plurality of sub core circuits includes a sense amplifier segmented to be connected to a corresponding sub cell block, and a processing element connected to the segmented sense amplifier and configured to perform a logical operation on an operand that is data loaded into the segmented sense amplifier.

In a matrix of SOT-MRAM cells, a first row is selected for writing and a second row is selected for reading. A first SOT-MRAM cell of the first row and a second SOT-MRAM of the second row are in a first column, while a third SOT-MRAM cell of the first row and a fourth SOT-MRAM of the second row are in a second column. The currents for writing the first SOT-MRAM cell and the third SOT-MRAM cell are in opposite direction. A first sense amplifier is configured to detect a voltage change on the first read bit line which is charged with a first read current in the second SOT-MRAM cell. A second sense amplifier is configured to detect a voltage change on the second read bit line which is discharged with a second read current in a fourth SOT-MRAM cell.

Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

A memory system includes a plurality of memory cells at intersections between a plurality of word lines and a plurality of bit lines, and a plurality of bit line sense amplifiers connected to the plurality of bit lines, the plurality of bit line sense amplifiers configured to write data to or read data from the plurality of memory cells through the plurality of bit lines, a redundancy bit line sense amplifier among the plurality of bit line sense amplifiers configured to generate a physically unclonable function (PUF) key including a unique random digital value.

A memory apparatus includes pages each including a plurality of memory cells arranged in a column on a substrate. A voltage applied to each of a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each page is controlled to perform a page write operation for retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel semiconductor layer, or a voltage applied to each of the first gate conductor layer, the second gate conductor layer, a third gate conductor layer, a fourth gate conductor layer, the first impurity layer, and the second impurity layer is controlled to perform a page erase operation for removing the holes from the channel semiconductor layer. The first impurity layer in the memory cell connects to a source line. The second impurity layer connects to a bit line. One of the first gate conductor layer and the second gate conductor layer connects to a word line, and the other connects to a first drive control line. The bit line connects to a sense amplifier circuit via a switch circuit. During a page read operation, page data in a group of memory cells selected by the word line is read by the sense amplifier circuit. During each of the page write operation, the page erase operation, and the page read operation, an identical fixed voltage is applied to the first drive control line.

The embodiment of the invention relates to the field of memories, and provides a sense amplifier which at least comprises a first transistor electrically connected between a first power supply node and a complementary read bit line, and the control end of the first transistor is connected to the control end of a third transistor; the second transistor is electrically connected between the second power supply node and the reading bit line, and the control end of the second transistor is connected to the control end of the fourth transistor; a third transistor electrically connected between the complementary read bit line and a third power supply node; a fourth transistor electrically connected between the read bit line and a fourth power supply node; the first calibration tube is connected between the complementary reading bit line and the control end of the third transistor; wherein the first power supply node is connected to a first power supply voltage through the first switching element; the second power supply node is connected to the first power supply voltage through the second switching element; the third power supply node is connected to a second power supply voltage through a third switching element; the fourth power supply node is connected to the second power supply voltage through a fourth switching element.

A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.

A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input / output (I / O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I / O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

A semiconductor device and a method for preparing the semiconductor device, the semiconductor device comprises a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bit line connection line and a second bit line connection line, the first semiconductor structure comprises a sensing amplifier circuit, the second semiconductor structure is connected to the first semiconductor structure by bonding and comprises a first storage unit, the third semiconductor structure is connected to the second semiconductor structure by bonding and comprises a second storage unit, the first bit line connection line is associated with the first storage unit, the second bit line connection line is associated with the second storage unit, the first bit line connection line and the second bit line connection line are comparatively coupled to each other by the sensing amplifier circuit, and the length difference between the first bit line connection line and the second bit line connection line is less than or equal to 2 microns. The coupling capacitance of adjacent bit lines can be reduced, the anti-crosstalk capability can be improved, and the difference in signal transmission time delay can be reduced, thereby improving the stability and reliability of the device.

Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

Single (1 T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

A 3D semiconductor device including: a first level with first-transistors, a single crystal layer overlaid by at least one first metal-layer which includes interconnects between the first-transistors forming first control circuits with a sense amplifiers; the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second-transistors with a metal gate, overlaid by a third level which includes second memory cells which include third-transistors and are partially disposed atop the control circuits, which control the data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third-transistor gate locations are aligned to second-transistor gate locations within greater than 0.2 nm error, the average thickness of second metal-layer is at least twice the average thickness of the third metal-layer; the second metal-layer includes a global power distribution grid.

A memory circuit includes a set of memory cells configured to store data, and a local input output (LIO) circuit coupled to a global bit line and the set of memory cells. The LIO circuit includes a sense amplifier, a driver circuit and a booster circuit. The sense amplifier is configured to sense a first signal in response to at least a sense amplifier signal. The first signal corresponds to a value of the data stored in the set of memory cells. The driver circuit is configured to generate a global bit line signal in response to at least the first signal or an inverted first signal. The booster circuit is coupled to the driver circuit and the global bit line, and configured to adjust the global bit line signal in response to a delayed global bit line signal.

A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.

The present application relates to the field of semiconductor circuit design, and relates to a sense amplifier circuit and a data readout method, comprising: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; a first control MOS transistor for providing a bias voltage to the first PMOS transistor according to a control signal; a second control MOS transistor for providing a bias voltage to the second PMOS transistor according to a control signal; a first offset cancellation MOS transistor for electrically connecting an initial bit line to a first complementary readout bit line according to the offset cancellation signal; and a second offset cancellation MOS transistor for electrically connecting the initial complementary bit line to the first readout bit line according to the offset cancellation signal. Stable gate voltages are provided to the first and second PMOS transistors respectively via the first and second control MOS transistors, thereby stably eliminating offset noise in the sense amplifier circuit and avoiding voltage fluctuations on the bit lines and complementary bit lines.

Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

A leakage-based physical unclonable function (L-PUF) device, a L-PUF array and applications thereof are provided. The L-PUF device includes a precharge circuit, two leaky devices and a sense amplifier. The two leaky devices are electrically connected to the precharge circuit respectively. Each leaky device includes a transistor having a control end electrically connected to ground, a first end electrically connected to the precharge circuit and a second end electrically connected to ground. The sense amplifier is electrically connected to the first end of each of the two leaky devices, and may generate a first output signal and a second output signal. The sense amplifier may switch between a first state and a second state based on a voltage difference between the first leaky device and the second leaky device, which is determined by a leakage current of the first leaky device and a leakage current of the second leaky device.

A memory device includes a first semiconductor layer and a second semiconductor layer arranged relative to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bit line and a complementary bit line coupled with the memory cell array, a first vertical conductive line coupled with the bit line, and a second vertical conductive line coupled with the complementary bit line. The second semiconductor layer includes a peripheral circuit, a bit line sense amplifier, first and second control lines coupled with the bit line sense amplifier, a third vertical conductive line coupled with the bit line sense amplifier, and a fourth vertical conductive line coupled with the bit line sense amplifier. The bit line sense amplifier includes at least one first transistor pair shared by at least one of the first control line and the second control line.

A semiconductor memory device may include a first chip including a first array matrix and a second array matrix adjacent to each other and including memory cells, and a second chip below the first chip, and including sense amplifiers configured to drive the memory cells, where first cell bit lines are in the first array matrix, and second cell bit lines are in the second array matrix, where first bit lines and first complementary bit lines are below the first array matrix, and second bit lines and second complementary bit lines are below the second array matrix, where the first bit lines and the second bit lines are connected to the first cell bit lines and the second cell bit lines, respectively, and where the first complementary bit lines and the second complementary bit lines are connected to the second cell bit lines and first cell bit lines, respectively.

A voltage generator including an LDO (low dropout) regulator that supplies a current to an internal voltage node of a sense amplification circuit as feedback control based on a voltage level of the internal voltage node; and a power switch circuit including a plurality of power switches each having one end connected to an external voltage and an opposite end connected to the internal voltage node, and that supplies the current to the internal voltage node as feed-forward control based on a known number of sense amplifiers to be activated. The voltage generator may efficiently supply current according to an operation mode of the sense amplification circuit.

A microelectronic device includes a control circuitry structure and a memory array structure bonded to the control circuitry structure. The control circuitry structure includes a control circuitry region including two sense amplifier (SA) sub-regions including SA circuitry, and two sub-word line driver (SWD) sub-regions including SWD circuitry. The two SA sub-regions horizontally extend between opposing boundaries of the control circuitry region in a first direction. The two SWD sub-regions are interposed between the two SA sub-regions in a second direction and individually include a central region adjacent a respective one of the opposing horizontal boundaries of the control circuitry region, and two arm regions at opposing ends of the central region in the second direction and respectively horizontally protruding, in the first direction, from the central region. The memory array structure includes an array region horizontally overlapping the control circuitry region of the control circuitry structure and including memory cells.

A memory device includes a first semiconductor layer and a second semiconductor layer disposed with respect to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bitline and a complementary bitline coupled with the memory cell array, a first vertical wire coupled with the bitline, and a second vertical wire coupled with the complementary bitline. The second semiconductor layer includes a peripheral circuit, a bitline sense amplifier, first and second control lines coupled with the bitline sense amplifier, a third vertical wire coupled with the bitline sense amplifier, and a fourth vertical wire coupled with the bitline sense amplifier. The bitline sense amplifier includes at least one first transistor pair that is shared by at least one of the first and second control lines.

A memory circuit includes a first memory cell operatively accessible through a first access line and a second access line; a first read pass-gate transistor and a second read pass-gate transistor coupled to the first access line and second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on a clock signal; and a second read enable control circuit configured to generate a second read enable signal. The first read enable signal selectively transitions to a different logic state based on a first sense enable signal. The second read enable signal is configured to activate or deactivate both the first and second read pass-gate transistors, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.

A semiconductor device may include: a cell area in which a plurality of memory cells arranged in a first direction, a second direction and a third direction are disposed, the first direction and the second direction being parallel to an upper surface of a substrate and intersecting, and the third direction being perpendicular to the upper surface of the substrate; and a peripheral circuit area in which a word line driver connected to the plurality of memory cells through a plurality of word lines, a sense amplifier circuit connected to the plurality of memory cells through a plurality of bit lines, and a source line driver connected to the plurality of memory cells through a plurality of source lines, are disposed.