519 results about "Sense amplifier" patented technology

The embodiment of the invention relates to the field of memories, and provides a sense amplifier which at least comprises a first transistor electrically connected between a first power supply node and a complementary read bit line, and the control end of the first transistor is connected to the control end of a third transistor; the second transistor is electrically connected between the second power supply node and the reading bit line, and the control end of the second transistor is connected to the control end of the fourth transistor; a third transistor electrically connected between the complementary read bit line and a third power supply node; a fourth transistor electrically connected between the read bit line and a fourth power supply node; the first calibration tube is connected between the complementary reading bit line and the control end of the third transistor; wherein the first power supply node is connected to a first power supply voltage through the first switching element; the second power supply node is connected to the first power supply voltage through the second switching element; the third power supply node is connected to a second power supply voltage through a third switching element; the fourth power supply node is connected to the second power supply voltage through a fourth switching element.

A voltage generator including an LDO (low dropout) regulator that supplies a current to an internal voltage node of a sense amplification circuit as feedback control based on a voltage level of the internal voltage node; and a power switch circuit including a plurality of power switches each having one end connected to an external voltage and an opposite end connected to the internal voltage node, and that supplies the current to the internal voltage node as feed-forward control based on a known number of sense amplifiers to be activated. The voltage generator may efficiently supply current according to an operation mode of the sense amplification circuit.

A memory includes a local control circuitry that manages refresh transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts refresh transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides refresh transactions into phases and periods based on whether the refresh transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt refresh transactions with access transactions in a manner that minimizes access interference.

A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.

A memory circuit includes a memory cell, a bit line, a bit line bar, a pass-gate transistor coupled to the memory cell and the bit line, a sense amplifier coupled to the bit line, the bit line bar and the pass-gate transistor, and a pre-charge circuit coupled to the first node, and configured to pre-charge the first node to a pre-charge voltage in response to a pre-charge control signal. The sense amplifier includes a first path between the bit line and the bit line bar. The first path includes a first isolation transistor configured to receive an isolation control signal, and being coupled between the bit line and a first node, and a first inverter configured to receive a sense amplifier enable signal, and being coupled between a second node and a third node.

Systems and methods implementing an improved DVCS amplifier are described. The integrated circuit can include a controller. The integrated circuit can further include an amplifier configured to measure a common mode voltage across a capacitor of a switching converter. The integrated circuit can include a circuit configured to receive a differential input being provided to the amplifier. Based on the differential input, the circuit can further be configured to maintain the common mode voltage to regulate the amplifier within an operating range of the amplifier.

To provide a semiconductor storage device for storing data by accumulating majority carriers in an electrically floating body of a MOSFET.SOLUTION: In a memory device using a semiconductor device, plate lines PLL0, PLR0 capacitively coupled to floating bodies of memory cells MCL, MCR are wired in parallel with word lines WLL0, WLR0 separately for each word line, and an erase operation of majority carriers is executed simultaneously along the word lines by applying a voltage to the plate lines. In the refresh operation, after the data along the selected word line is read and latched by the sense amplifier S / A, the bit lines BLL and BLR are separated from the sense amplifier to once erase the majority carriers all together from the floating bodies of the cells on the selected word line, and the majority carriers are injected into the cells in which a large number of majority carriers are originally stored depending on the state of the sense amplifier. In addition, the write operation includes an operation of simultaneously extracting majority carriers from the selected cell and simultaneously writing data to the sense amplifier from the outside.SELECTED DRAWING: Figure 4

Some embodiments include an integrated assembly having a memory array over a substrate. The memory array includes a three-dimensional arrangement of memory cells. A sense amplifier is associated with the substrate and directly below the memory array. A vertically extending digit line passes through the arrangement of memory cells and is coupled with the sense amplifier. Some embodiments include an integrated assembly having a memory bank containing 64 memory data blocks arranged in a 16x4 configuration. Some embodiments include an integrated assembly having a memory bank containing 512 megabytes divided among 64 memory data blocks, each memory data block having 8 megabytes. The 64 memory data blocks are arranged in a configuration having a plurality of rows, each row containing two or more of the memory data blocks.

A sense amplifier and a memory device including the sense amplifier are provided. The sense amplifier includes: a first PMOS transistor and a first NMOS transistor connected in series between a power supply voltage and an input node; a second NMOS transistor connected between the input node and ground; a second PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor connected in series between the power supply voltage and ground; a first switch connected between a first node and a second node, the first node being between the first PMOS transistor and the first NMOS transistor, and the second node being between the second PMOS transistor and the third NMOS transistor; and a second switch connected between the second node and an output node.

A compare circuitry that can be implemented in a memory circuit includes: selection logic coupled to a sense amplifier of the memory circuit, the selection logic structured to receive a sense amplifier enable signal, a column output from the sense amplifier, and a column output bar from the sense amplifier, wherein the selection logic is structured to pass through the column output and the column output bar when the sense amplifier enable signal is active and hold the column output and the column output bar at a same value when the sense amplifier enable signal is inactive; and an XNOR gate structured to receive the column output and the column output bar passed through the selection logic, a data input, and a data input bar and output a bit compare output.

Disclosed are devices including threshold-voltage compensated sense amplifiers and methods of compensation thereof. Example threshold-voltage compensated sense amplifiers according to the present disclosure include circuitry for providing threshold-voltage compensation, such as an isolation transistor and at least one pre-charge transistor.

Systems and methods for sense amplifier power reduction are disclosed including controlling a supply voltage to a sense amplifier through different periods of operation, including providing a first supply voltage to the sense amplifier during an activation period and a second supply voltage to the sense amplifier lower than the first supply voltage during a precharge period to reduce power consumption of the sense amplifier. A voltage supply to a memory cell can be limited to the second supply during the precharge period to reduce a potential voltage stored at the memory cell, increasing memory cell retention.

Methods, systems, and devices for a counter-based sense amplifier method for memory cells are described. The described techniques provide for a memory system to store, in a counter associated with an array of memory cells, a value indicating a quantity of memory cells in the array having a predetermined logic value. The memory system may perform a read operation to read the data stored in the array of memory cells by applying a ramping bias voltage and may count the quantity of memory cells having the predetermined logic value during the read operation. The memory system may stop the read operation when the memory system identifies a quantity of memory cells having the predetermined logic value that is equal to the value stored to the counter.

A ferroelectric memory device includes: a ferroelectric memory cell connected between a bit line and a plate line and controlled by a word line; a row decoder configured to activate the word line; a board line voltage generator configured to provide a ground voltage to the board line during a pre-charge period and provide a first voltage to the board line in response to activation of the word line; and a sense amplifier configured to amplify a voltage of the bit line to a second voltage higher than the first voltage during a sensing operation.

Systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. An apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. A first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. A second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. Control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.

A semiconductor storage device includes memory cells and a sense amplifier circuit. Each of the memory cells includes p-type drive transistors, n-type load transistors, and p-type access transistors connected to a bit line pair. The sense amplifier circuit includes p-type transistors and n-type transistors.

Systems, devices, methods, and circuits for managing failures of in-memory computing (IMC) devices. An example memory device includes: a plurality of memory units and a circuitry configured for execution of a computing instruction in one or more memory units. A memory unit includes: a memory cell array and a peripheral circuit including a plurality of subcircuits coupled to the memory cell array. Each subcircuit includes: one or more internal sense amplifiers, one or more latches, and one or more multipliers. The circuitry is configured to: determine whether a subcircuit is defective by determining whether at least one of an internal sense amplifier, a latch, or a multiplier in the subcircuit is defective using an external sense amplifier external to the memory unit, and in response to determining that the subcircuit is defective, perform one or more corresponding actions including replacing the subcircuit with a redundant subcircuit in the peripheral circuit.

The present invention efficiently routes bit lines. In a semiconductor memory device according to an embodiment, a second bit line includes: a second inter-cell-module wiring electrically connected to a second memory cell and extending in a first direction from a position overlapping the second memory cell in a vertical direction toward a sense amplifier module; and a second in-module wiring that is parallel to the first in-module wiring in the first direction and extends in the second direction at a position close to the first in-module wiring, and that electrically connects the second inter-cell-module wiring and the second sense amplifier cell.

An in-memory computing (IMC) accelerator using a high-density operation circuit and a low-power sense amplifier as a peripheral circuit includes a plurality of dynamic random-access memory (DRAM) banks each including a pair of cell arrays, a data supply logic, a memory, and a controller for IMC, a global SRAM, and a top-level controller, wherein the cell array includes a plurality of subarrays, each of the subarrays includes a DRAM array including a big array and a little array, and an arithmetic circuit configured to perform an operation, and the arithmetic circuit includes a sense amplifier configured to amplify a bit line voltage difference, and a compact multiply-accumulate (MAC)-single instruction multiple data (SIMD) unit (CMSU) for an MAC operation and an SIMD operation, so that functionality of an in-memory operation is diversified.

A system and technique for buffering data locally within a memory device to allow access to data associated with a plurality of different rows within the memory device. The memory device includes a storage bank circuit having memory cells and a sense amplifier circuit coupled to the storage bank circuit. The memory device also includes a buffer circuit coupled to an output of the sense amplifier circuit. In addition, the memory device includes a selection circuit. The selection circuit receives a first data signal from the sense amplifier circuit and a second data signal from the buffer circuit and outputs a selected one of the first data signal and the second data signal.

A system to generate true random numbers includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array. The hash generator receives a null-read result from the null-read operation and outputs a partial true random number based on the null-read result.

The application discloses a reconfigurable strong PUF circuit and method with strong nonlinear response, an STT-MRAM storage unit array is used for storing data information "0" or "1", an odd array access transistor is used for accessing the STT-MRAM storage unit of an odd bit, and an even array access transistor is used for accessing the STT-MRAM storage unit of an even bit; an odd array excitation selection transistor is used for controlling the write signal of the STT-MRAM storage unit of the odd bit, and an even array excitation selection transistor is used for controlling the write signal of the STT-MRAM storage unit of the even bit; an array selection circuit ASC selects an odd row STT-MRAM storage unit and an even row STT-MRAM storage unit from the STT-MRAM storage unit array, inputs the resistance comparison into a sensing amplifier circuit SA, and outputs a comparison result. The application makes the PUF response have strong nonlinearity, thereby significantly improving the security, and improving the performance of the PUF in speed, power consumption, area and the like.

A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RTj to convert a resistance value of a memory cell MCij to be read to a data voltage, a reference circuit and RTR to generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RTj and a first input terminal of the sense amplifier or between the reference circuit and RTR and a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.

A data readout method, corresponding circuit, and memory device are provided. In an example, plural memory banks in a memory device share a common data readout bus via respective sense amplifiers. Data are read from the memory banks in a sequence of readout operations wherein, during each readout operation, the sense amplifier of one of the memory banks takes control over the common data readout bus and data are read from that one memory bank via the sense amplifier taking control over the common data readout bus, while the sense amplifiers of the other memory banks are set to a high impedance state.

A semiconductor device capable of increasing readout margin in a nonvolatile resistive random access memory is provided. A clamping circuit applies fixed potential to each of a memory element and a reference resistive element. A pre-charge circuit pre-charges first and second nodes to power-source potential. A sense amplifier amplifies the potential difference between the potential of the first node and the potential of the second node generated after a discharge period based on cell current and reference current after pre-charging made by the pre-charge circuit. A third node is coupled to the first and second nodes through a capacitor. An electric-charge supply circuit is connected to the third node, and supplies electric charge to the third node in the discharge period.

A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input / output (I / O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I / O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

A memory device includes a memory cell coupled to a word line and a bit line, a row driver to drive the word line to a pre-charge level, a column driver to drive the bit line to a first target level, a sense amplifier to sense a first sense level of the word line after the first target level is applied to the memory cell, and a read control circuit to control the column driver to selectively apply a second target level different from the first target level to the memory cell based on the first sense level sensed by the sense amplifier.

A semiconductor memory device includes: a memory cell array located in a first layer and including a word line, a cell bit line, and a memory cell located in a region where the word line and the cell bit line are crossed; and a bit line sense amplifier located in a second layer, different from the first layer. The bit line sense amplifier is connected to a bit line that is connected to the cell bit line and to a complementary bit line corresponding to the bit line. The bit line sense amplifier detects data stored in the at least one memory cell. Each of the at least one cell bit line is segmented into two or more portions, and the two or more portions are respectively connected to the bit line and the complementary bit line connected to the bit line sense amplifier.

Methods, systems, and devices for threshold voltage compensation for a memory system sense amplifier are described. A sense amplifier may include a first transistor comprising: a gate terminal coupled with a second digit line, a drain terminal coupled with a first digit line through a first switching component, and a source terminal coupled with a node. The sense amplifier may include a second transistor comprising a source terminal coupled with the node. The sense amplifier may include a first voltage supply configured to be coupled with the node using a third transistor during an amplification phase of a sense operation for the memory cell; and a second voltage supply configured to be coupled with the node through a fourth transistor during a compensation phase of the sense operation.

Embodiments provide a storage device that can improve characteristics of the storage device. According to one embodiment, a device includes a sense amplifier that senses a first signal based on first data in a cell and a second signal based on second data in the cell. The sense amplifier includes a current mirror that causes a first current to flow into a first node connected to the cell and causes a second current to flow into a second node based on a potential of the first node, a first switch connected to the second node and a third node, a transistor including a terminal connected to the second node and a gate connected to the third node, a second switch connected to the second node and a fourth node, and a circuit connected to the second node and the third node and causing a third current to flow into the second node based on a potential of the third node.