3 results about "Datapath circuits" patented technology

A transceiver circuit is disclosed. The transceiver circuit includes a transmitter driver circuit configured to drive a transmit antenna. The transceiver circuit also includes a receiver circuit configured to generate digital signals based on received signals. The transceiver circuit also includes a loopback data path circuit electrically connected to the transmitter driver circuit and to the receiver circuit, where the loopback data path circuit is configured to conditionally provide signals from the transmitter driver circuit to the receiver circuit according to one or more control signals. The transceiver circuit also includes a controller configured to generate the control signals.

A computing system includes a communication system comprising a glitch filter circuitry disposed in an integrated circuit (IC) device configured to receive an input signal and provide a glitch filter output signal based on the input signal. The glitch filter circuitry includes a control path circuitry configured to receive the input signal and generate a control signal based on detecting a glitch within the input signal, the control path circuitry including a configurable resistor capacitor (RC) filter circuitry configured to deliver a configurable RC filter circuitry output signal based on one or more selection signals. The control signal is based on the configurable RC filter circuitry output signal, and a data path circuitry configured to receive the control signal and mitigate glitches within the input signal based on the control signal.

A memory device includes core circuitry having memory cells and write data path circuitry coupled to the core circuitry. The write data path circuitry determines a second parity bit based on a second signal and a poison bit. The second signal and the poison bit are determined by processing a first data signal. Furthermore, the write data path circuitry detects a first error within the second signal based on a comparison between the first parity bit and the second parity bit, and outputs a first error signal including the first error.