4 results about "NOR logic" patented technology

The application discloses a double-gate reconfigurable field effect transistor process design kit construction method, and belongs to the field of integrated circuit process design kit expansion, reconfigurable device modeling and physical verification. In view of the fact that existing open source PDK mainly faces traditional CMOS devices and is difficult to support circuit design, layout drawing and post-layout verification of double-gate RFET, the application provides a process design kit construction method for double-gate RFET. The method comprises the following steps: constructing a four-terminal RFET compact model and packaging the four-terminal RFET compact model into a SPICE subcircuit; establishing a schematic symbol, a layout unit and parameter configuration; extending LVS device identification rules to identify four-port RFET devices containing a source, a drain, a control gate and a polarity gate; constructing a parasitic parameter extraction file and integrating the parasitic parameter extraction file into a layout verification process; and finally, performing post-layout simulation verification on an RFET inverter and reconfigurable NAND and NOR logic. The application realizes a complete design closed loop of double-gate RFET from a model, a schematic, a layout, DRC / LVS, PEX and reverse label simulation.

The application provides an approximate circuit automatic pruning method based on a global optimization algorithm, which obtains an automatic pruning result of the circuit by decomposing an original circuit structure and with the help of a global optimization algorithm. The application changes the deleted minimum unit into a basic NAND logic, improving the precision of deletion. At the same time, the decomposed NAND logic is converted into a C language model, so that the whole iteration is separated from the synthesis tool and the simulation tool, and the simulation is replaced by the C language, saving a large amount of time. Finally, the global optimization algorithm is added, and the optimal solution of each iteration is no longer searched for in the selection of the deleted node, but the whole is considered, and a suitable node set is searched for deletion, so that the effect of the deleted node is optimal. In the approximate processing of 16 8-bit additions, the highest area reduction of 18.47% and the power consumption reduction of 38.91% are obtained under the mse limit of 100.

The invention discloses an exclusive-OR circuit based on an RRAM mirror device and application of the exclusive-OR circuit in image encryption, and belongs to the field of integrated circuit design. The XOR circuit comprises a left array, an RMD unit located on the right side and two STI units located between the left array and the right RMD unit. The left-side array comprises two RMD units, the two RMD units in the left-side array receive signals A and B respectively, and then the left-side array generates two logic signals through OR and NAND operations respectively; the two logic signals are subjected to level conversion through the two STI units and then jointly applied to the RMD unit on the right side, and final XOR output is generated through NOR logic operation. According to the circuit, the number of devices and the circuit structure are remarkably simplified while the functional integrity is maintained; and the XOR logic function and the image encryption application are realized, and the method has obvious advantages in the aspects of performance, integration and manufacturing cost.

The application relates to a repeatable trigger type monostable circuit based on multi-channel signal control, comprising a data selector, a plurality of tri-state gate buffers, the enable ends of the tri-state gate buffers being connected with the output ends of the data selector respectively, the input ends of the tri-state gate buffers being used for connecting external sensors, a NAND logic gate, one input end of the NAND logic gate being connected with the output ends of the tri-state gate buffers through an input coupling bias unit, an NOR logic gate, one input end of the NOR logic gate being connected with the output end of the NAND logic gate through a delay unit, the other input end of the NOR logic gate being grounded, and the output end of the NOR logic gate being connected with the other input end of the NAND logic gate, and the enable state of each tri-state gate buffer is controlled, and the input trigger signal of the tri-state gate buffer being enabled is continuously responded within the delay time defined by the delay unit. Compared with the prior art, the application has the advantages of simplicity, selectivity based on different trigger sources, and the like.