8 results about "NOR logic" patented technology

A non-overlapping clock generator based on exclusive-NOR gates. The non-overlapping clock generator generates a non-overlapping in-phase output clock signal and an inverting output clock signal from an input clock signal. The non-overlapping clock generator includes first and second exclusive-NOR gates, first and second load transistors cross-coupled to each other, and first and second delay circuits coupled between the in-phase output clock signal and the control terminal of the first load transistor and between the inverting output clock signal and the control terminal of the second load transistor, respectively. Each exclusive-NOR gate includes at least one pass transistor logic to implement exclusive-NOR logic, the at least one pass transistor logic being coupled to the first control voltage. A non-overlapping period between the in-phase output clock signal and the inverting output clock signal is determined based on the first control voltage and / or the delay periods of the first and second delay circuits.

The application discloses a double-gate reconfigurable field effect transistor process design kit construction method, and belongs to the field of integrated circuit process design kit expansion, reconfigurable device modeling and physical verification. In view of the fact that existing open source PDK mainly faces traditional CMOS devices and is difficult to support circuit design, layout drawing and post-layout verification of double-gate RFET, the application provides a process design kit construction method for double-gate RFET. The method comprises the following steps: constructing a four-terminal RFET compact model and packaging the four-terminal RFET compact model into a SPICE subcircuit; establishing a schematic symbol, a layout unit and parameter configuration; extending LVS device identification rules to identify four-port RFET devices containing a source, a drain, a control gate and a polarity gate; constructing a parasitic parameter extraction file and integrating the parasitic parameter extraction file into a layout verification process; and finally, performing post-layout simulation verification on an RFET inverter and reconfigurable NAND and NOR logic. The application realizes a complete design closed loop of double-gate RFET from a model, a schematic, a layout, DRC / LVS, PEX and reverse label simulation.

The application provides an approximate circuit automatic pruning method based on a global optimization algorithm, which obtains an automatic pruning result of the circuit by decomposing an original circuit structure and with the help of a global optimization algorithm. The application changes the deleted minimum unit into a basic NAND logic, improving the precision of deletion. At the same time, the decomposed NAND logic is converted into a C language model, so that the whole iteration is separated from the synthesis tool and the simulation tool, and the simulation is replaced by the C language, saving a large amount of time. Finally, the global optimization algorithm is added, and the optimal solution of each iteration is no longer searched for in the selection of the deleted node, but the whole is considered, and a suitable node set is searched for deletion, so that the effect of the deleted node is optimal. In the approximate processing of 16 8-bit additions, the highest area reduction of 18.47% and the power consumption reduction of 38.91% are obtained under the mse limit of 100.

The invention discloses an exclusive-OR circuit based on an RRAM mirror device and application of the exclusive-OR circuit in image encryption, and belongs to the field of integrated circuit design. The XOR circuit comprises a left array, an RMD unit located on the right side and two STI units located between the left array and the right RMD unit. The left-side array comprises two RMD units, the two RMD units in the left-side array receive signals A and B respectively, and then the left-side array generates two logic signals through OR and NAND operations respectively; the two logic signals are subjected to level conversion through the two STI units and then jointly applied to the RMD unit on the right side, and final XOR output is generated through NOR logic operation. According to the circuit, the number of devices and the circuit structure are remarkably simplified while the functional integrity is maintained; and the XOR logic function and the image encryption application are realized, and the method has obvious advantages in the aspects of performance, integration and manufacturing cost.

The application discloses a kind of based on multi-region grid single channel microcavity transistor, photoelectric full logic gate device, control method and circuit, the full logic gate device includes the substrate, first bottom gate electrode and second bottom gate electrode, bottom gate dielectric layer, channel layer, source electrode and drain electrode, top gate dielectric layer, top gate electrode of stacked arrangement, it further includes first laser and second laser.First bottom gate electrode and second bottom gate electrode, bottom gate dielectric layer, channel layer, source electrode and drain electrode constitute NOR logic gate;Second bottom gate electrode, bottom gate dielectric layer, channel layer, source electrode and drain electrode, top gate dielectric layer, top gate electrode constitute NAND logic gate;Substrate, channel layer, source electrode and drain electrode and first laser and second laser constitute XOR logic gate;The application can realize linear NAND and NOR and nonlinear XOR three kinds of logic functions in single transistor device, reduce transistor consumption and circuit area.

This disclosure provides a miniature LED pixel driving circuit, which includes a logic operation module and a pixel driving module. The logic operation module receives an N-bit image data signal, where N is a positive integer. The logic operation module includes a conversion unit, an AND logic unit connected to the conversion unit, and a NOR logic unit connected to the AND logic unit. The conversion unit is used to convert the N-bit image data signal in a first format to a second format. The AND logic unit is used to convert the N-bit image data signal in the second format and a timing control signal to a third format. The NOR logic unit is used to convert the N-bit image data signal in the third format to a fourth format to control the on / off state of the pixel driving module.

A flip-flop includes a first input circuit, a first NOR logic gate, a first stacked gate circuit and a first NAND logic gate. The first input circuit is coupled to a first node, and configured to generate a first signal responsive to at least a first data signal, a first clock signal, or a second clock signal. The first NOR logic gate is coupled between the first node and a second node, and configured to generate a second signal responsive to the first signal or a first reset signal. The first stacked gate circuit is coupled between the first node and a third node, and configured to generate a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and fourth node, and is configured to generate a fourth signal responsive to the third signal or a second reset signal.

The application relates to a repeatable trigger type monostable circuit based on multi-channel signal control, comprising a data selector, a plurality of tri-state gate buffers, the enable ends of the tri-state gate buffers being connected with the output ends of the data selector respectively, the input ends of the tri-state gate buffers being used for connecting external sensors, a NAND logic gate, one input end of the NAND logic gate being connected with the output ends of the tri-state gate buffers through an input coupling bias unit, an NOR logic gate, one input end of the NOR logic gate being connected with the output end of the NAND logic gate through a delay unit, the other input end of the NOR logic gate being grounded, and the output end of the NOR logic gate being connected with the other input end of the NAND logic gate, and the enable state of each tri-state gate buffer is controlled, and the input trigger signal of the tri-state gate buffer being enabled is continuously responded within the delay time defined by the delay unit. Compared with the prior art, the application has the advantages of simplicity, selectivity based on different trigger sources, and the like.