Sensitivity amplifying sequential control signal generating circuit based on self-timing

Abstract

The invention, belonging to the technical field of integrated circuit memory cell, particularly relates to a sensitivity amplifying sequential control signal generating circuit based on self-timing. The circuit comprises two configurable memory cell pseudo arrays, and a double-input NOR-logic and a delay unit, wherein the bit lines of the pseudo memory array is pre-charged to a high level, while working, when word line signals (WL signals) of the pseudo array are changed from low level to high level, the bit lines (BL) of the two configurable memory cell pseudo arrays start to discharge, the bit line voltage is reduced so that the NOR gate is overturned to complete the sequential control function. According to the invention, the function failure problem of the memory caused by process variation in the manufacturing process can be effectively reduced, the yield of the memory is raised, and the reading speed of the memory is raised.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit storage units, and in particular relates to a self-timing-based sensitive amplifying timing control signal generation circuit for Static Random Access Memory (SRAM) or Register File. Background technique [0002] Integrated circuit technology manufacturing has entered the deep submicron manufacturing stage, 65nm and 45nm CMOS technology has become the mainstream technology of integrated circuit manufacturing, industry-leading companies such as Intel and IBM have successively manufactured 22nm and 18nm CMOS technology circuits. However, with the continuous improvement of the process and the continuous decrease of the minimum channel size, the impact of process manufacturing deviations on CMOS devices is becoming more and more significant. Especially for storage devices with high data storage rate, such as static random access memory (Static Random Access Memory, SRAM) or register file (R...

AI Technical Summary

Problems solved by technology

This causes the discharge speed and discharge time of each column to be different, resulting in poor time follow-up of the pseudo-array memory cells, or even failure, and the entire memory cannot work.

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