Ultra high-speed nor-type lsdl/domino combined address decoder

Abstract

An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address hits are converted into N logic true address bits and N complementary address bits. A partial address decoder generates two bit groups using selected of the N logic true address bits and N complementary address bits in NOR logic structures such only two cascaded NFETS are used in a logic tree. The bit groups are partitioned to optimize the layout of the parallel bit lines in the address decoder.

Description

TECHNICAL FIELD[0001]The present invention relates to ultra high speed address decoders using dynamic logic circuits, and in particular, to address decoders employing partial decoders and word-line drivers for addressing a group of registers.BACKGROUND INFORMATION[0002]Modern data processing systems may perform Boolean operations on a set of signals using dynamic logic circuits. Dynamic logic circuits are clocked. During the precharge phase of the clock, the circuit is preconditioned, typically, by precharging an internal node (dynamic node) of the circuit by coupling to a power supply rail. During an evaluate phase of the clock, the Boolean function being implemented by the logic circuit is evaluated in response to the set of input signal values appearing on the inputs during the evaluate phase. (For the purposes herein, it suffices to assume that the input signals have settled to their “steady-state” values for the current clock cycle, recognizing that the input value may change f...

AI Technical Summary

Benefits of technology

[0010]The invention offers a scheme to make an ultra high-speed Address Decoder generating 2N address lines from N address bits by combining both NOR-type Limited Dynamic Switch Logic (LSDL) and NOR-type Domino Logic to implement a Partial Decoder (PD) portion of the Address Decoder. The PD circuitry is partitioned into a first and second circuit group. The first circuit group receives M of the N address bits and generates P=2M bits and is implemented in NOR-type LSDL logic gates. The second group receives (N−M) of the N address bits and generates K=2N−M bits and is implemented in NOR-type Domino logic. Since LSDL has lower power dissipation than Domino, the partition is chosen such that P is greater than K. This enables the speed of dynamic logic to be realized without the power of a total Domino implementation.

[0011]The word-line (WL) Drivers are configured as K groups of P drivers wherein each of the P drivers has an input receiving one of the P bits from the first circuit group and has a common node gated by a same one of the bits from the K bits generated by the second circuit group. This generates the P times K=2N word-lines. Since the K groups of P drivers are each gated by a Domino driven bit line, each word-lines is thus gated by the Domino circuit clock and is only active for one-half clock cycle and OFF for the second-half clock cycle. Only one clock phase is needed for the Address Decoder and having P drivers gated by a common bit line reduces layout area and increases WL driver speed. Having no more that two cascaded NFETS in the logic gates, using a single clock phase, and implementing the logic using a combination of LSDL and Domino dynamic logic gates enables an ultra high speed Address Decoder.

Problems solved by technology

However, the switching of the output node with the toggling of the phase of the clock each cycle may consume power even when the logical value of the output is otherwise unchanged.

Computer systems employing dynamic logic may find that it is difficult to implement selection circuits for single and multilevel selection from many inputs because of the limitations of required precharge and evaluation times as well as the fact that outputs are not held during the precharge cycle.

Output data driving consumes an additional clock cycle.

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