5 results about "NAND logic" patented technology

The application provides an approximate circuit automatic pruning method based on a global optimization algorithm, which obtains an automatic pruning result of the circuit by decomposing an original circuit structure and with the help of a global optimization algorithm. The application changes the deleted minimum unit into a basic NAND logic, improving the precision of deletion. At the same time, the decomposed NAND logic is converted into a C language model, so that the whole iteration is separated from the synthesis tool and the simulation tool, and the simulation is replaced by the C language, saving a large amount of time. Finally, the global optimization algorithm is added, and the optimal solution of each iteration is no longer searched for in the selection of the deleted node, but the whole is considered, and a suitable node set is searched for deletion, so that the effect of the deleted node is optimal. In the approximate processing of 16 8-bit additions, the highest area reduction of 18.47% and the power consumption reduction of 38.91% are obtained under the mse limit of 100.

The invention provides an in-memory computing acceleration system based on UFS NAND and electronic equipment. Large model parameters, parameter sparsity indexes and large model computing intermediate data are stored in a partition mode through a UFS NAND storage array module; when a request for initiating a large model task is received through a logic chip integration module, a task computing power demand and parameter sparseness are evaluated, attention acceleration calculation is performed by using a large model based on an evaluation result to obtain an output calculation result, or the calculation result is migrated to an external chip for calculation. The method is highly adaptive to the core characteristics of a large model, supports parameter sparse access and a hardware acceleration attention mechanism, and can meet the calculation requirements of the large model; moreover, the computing power of a UFS NAND logic chip is enhanced, a UFS protocol and an existing architecture are compatible, end-side equipment can be directly replaced, hardware modification is not needed, and the cost is reduced; and task scheduling can be optimized, local calculation and external migration are intelligently switched according to task types and parameter sparseness, and efficiency and performance are considered.

The invention discloses a customizable NAND logic gate biosensing system based on an engineered methylated CRISPR / Cas12a consensus sequence and an application of the customizable NAND logic gate biosensing system. According to the system, an engineered methylated CRISPR / Cas12a consensus sequence (MCCS, 5 '-TTTGATC-3') is combined with a hybridization chain reaction triggered by a primer, so that efficient conversion between a methylation state and Cas12a activation is realized. Dam methyltransferase, S-adenosylmethionine (SAM) and DpnI are used as three input signals, and when the three input signals all exist, methylation catalyzed by the Dam methyltransferase promotes DpnI cutting, destroys the continuity of a PAM-original spacer region and enables Cas12a to be inactivated (in a closed state), and a low-fluorescence signal is generated; under any other input combination, the Cas12a-crRNA keeps the activity and outputs a high-fluorescence'turn-on 'signal, so that the ultra-sensitive detection on the activity of the Dam methyltransferase is realized. The system shows high recovery rate and low variability in simulating a real biological sample, and provides a universal molecular calculation driven sensing platform for enzyme activity analysis and inhibitor screening in a complex biological environment.

A flip-flop includes a first input circuit, a first NOR logic gate, a first stacked gate circuit and a first NAND logic gate. The first input circuit is coupled to a first node, and configured to generate a first signal responsive to at least a first data signal, a first clock signal, or a second clock signal. The first NOR logic gate is coupled between the first node and a second node, and configured to generate a second signal responsive to the first signal or a first reset signal. The first stacked gate circuit is coupled between the first node and a third node, and configured to generate a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and fourth node, and is configured to generate a fourth signal responsive to the third signal or a second reset signal.

The application relates to a repeatable trigger type monostable circuit based on multi-channel signal control, comprising a data selector, a plurality of tri-state gate buffers, the enable ends of the tri-state gate buffers being connected with the output ends of the data selector respectively, the input ends of the tri-state gate buffers being used for connecting external sensors, a NAND logic gate, one input end of the NAND logic gate being connected with the output ends of the tri-state gate buffers through an input coupling bias unit, an NOR logic gate, one input end of the NOR logic gate being connected with the output end of the NAND logic gate through a delay unit, the other input end of the NOR logic gate being grounded, and the output end of the NOR logic gate being connected with the other input end of the NAND logic gate, and the enable state of each tri-state gate buffer is controlled, and the input trigger signal of the tri-state gate buffer being enabled is continuously responded within the delay time defined by the delay unit. Compared with the prior art, the application has the advantages of simplicity, selectivity based on different trigger sources, and the like.