13 results about "NAND logic" patented technology

The invention discloses an asynchronous counter, a ramp generator, an analog-to-digital converter and an image sensor, and relates to the field of integrated circuits. The asynchronous counter comprises a plurality of cascaded D triggers; the clock input end and the inverted output end of each odd-level trigger are respectively connected to the first input end and the second input end of the OR logic gate, and the output end of the OR logic gate is connected to the clock input end of the next even-level trigger; the forward output end of each even-level trigger and the forward output end of the last odd-level trigger are connected to the first input end and the second input end of the NAND logic gate respectively, and the clock input end of the last odd-level trigger is connected to the third input end of the NAND logic gate through the phase inverter. And the output end of the NAND logic gate is connected to the clock input end of the next odd-level trigger. Therefore, by optimizing the generation logic of the clock input signal in the odd-level trigger, the delay time of the output signal under different bits is reduced.

According to the image transmission system used for monitoring, the image transmission system adopts the NAND gate logic circuit to replace traditional complex digital camera interface logic, the interface logic is simplified, and the requirements for interface resources and processing burden of a single-chip microcomputer are greatly reduced. And the physical size of the single-chip microcomputer and the occupied space of the system are obviously reduced. Through a double-buffer ping-pong operation mechanism and a threshold value control strategy, a high-speed and continuous data flow generated by the image acquisition module can be coped with only by utilizing a limited buffer memory in the single chip microcomputer. The requirement for a storage device in the data camera interface is avoided, and the cost of the storage device is saved. The compact, low-cost and efficient image transmission system makes it possible to realize reliable fly and insect image acquisition and storage by the insect situation monitoring control unit of the embedded equipment deinsectization device. And a high-quality data basis is provided for subsequent intelligent functions such as insect condition recognition and statistics based on image analysis.

The application provides an approximate circuit automatic pruning method based on a global optimization algorithm, which obtains an automatic pruning result of the circuit by decomposing an original circuit structure and with the help of a global optimization algorithm. The application changes the deleted minimum unit into a basic NAND logic, improving the precision of deletion. At the same time, the decomposed NAND logic is converted into a C language model, so that the whole iteration is separated from the synthesis tool and the simulation tool, and the simulation is replaced by the C language, saving a large amount of time. Finally, the global optimization algorithm is added, and the optimal solution of each iteration is no longer searched for in the selection of the deleted node, but the whole is considered, and a suitable node set is searched for deletion, so that the effect of the deleted node is optimal. In the approximate processing of 16 8-bit additions, the highest area reduction of 18.47% and the power consumption reduction of 38.91% are obtained under the mse limit of 100.

Herein, based on Boolean operators, DNA logic gate complexes are constructed to obtain True (fluorescence signal recovery) or False (fluorescence signal quenching) value using a molecular beacon acting as output. A DNA logic gate complex is composed of a DNA board and at least two modular logic units of YES and / or NOT gate. First, the DNA board is designed to accommodate individual YES and / or NOT modular logic units. An OR logic gate is composed of the DNA board and at least two YES modular logic units, and when there are multiple YES modular logic units, they are arranged in a parallel manner. A NAND logic gate is composed of a DNA board and at least two NOT modular logic units, and when there are multiple NOT modular logic units, they are arranged in a parallel manner. An IMPLY logic gate comprises at least one YES modular logic unit and at least one NOT modular logic unit as well as the DNA board. The designed DNA logic gate complexes were tested with biomarker miRNAs of hepatocellular carcinoma and successfully computed True / False fluorescence outcomes, exhibiting great potential for applications in the field of diseases diagnosis.

The application discloses a kind of based on multi-region grid single channel microcavity transistor, photoelectric full logic gate device, control method and circuit, the full logic gate device includes the substrate, first bottom gate electrode and second bottom gate electrode, bottom gate dielectric layer, channel layer, source electrode and drain electrode, top gate dielectric layer, top gate electrode of stacked arrangement, it further includes first laser and second laser.First bottom gate electrode and second bottom gate electrode, bottom gate dielectric layer, channel layer, source electrode and drain electrode constitute NOR logic gate;Second bottom gate electrode, bottom gate dielectric layer, channel layer, source electrode and drain electrode, top gate dielectric layer, top gate electrode constitute NAND logic gate;Substrate, channel layer, source electrode and drain electrode and first laser and second laser constitute XOR logic gate;The application can realize linear NAND and NOR and nonlinear XOR three kinds of logic functions in single transistor device, reduce transistor consumption and circuit area.

The utility model relates to a signal selection circuit and a fan adsorption system, the signal selection circuit comprises a signal selection operation module and a selection output module, the signal selection operation module comprises an AND gate logic circuit unit and an NAND gate logic circuit unit, the AND gate logic circuit unit is used for outputting a first selection signal when receiving a first signal, and the NAND gate logic circuit unit is used for outputting a second selection signal when receiving a second signal; or a first selection signal is output when the first signal and the second signal are received. And the NAND gate logic circuit unit is used for outputting a feedback signal to the AND gate logic circuit unit when receiving the second signal, so that the AND gate logic circuit unit outputs a second selection signal according to the second signal and the feedback signal. The selection output module is used for outputting a first analog signal when the control end receives the first selection signal and outputting a second analog signal when the control end receives the second selection signal. Through cooperation of the signal selection operation module and the selection output module, directional selection output of two paths of analog signals can be realized, a programming chip does not need to be arranged, and the circuit cost is effectively reduced.

The present disclosure relates to a memory circuit and an operating method thereof. A memory circuit includes: a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter, and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal and generate a first signal. The first N-type transistor is coupled to the NAND logic gate and is configured to receive a first precharge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage source and is configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate and is configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate and is configured to latch the first signal in response to at least the first clock signal or the first precharge signal.

The invention provides an in-memory computing acceleration system based on UFS NAND and electronic equipment. Large model parameters, parameter sparsity indexes and large model computing intermediate data are stored in a partition mode through a UFS NAND storage array module; when a request for initiating a large model task is received through a logic chip integration module, a task computing power demand and parameter sparseness are evaluated, attention acceleration calculation is performed by using a large model based on an evaluation result to obtain an output calculation result, or the calculation result is migrated to an external chip for calculation. The method is highly adaptive to the core characteristics of a large model, supports parameter sparse access and a hardware acceleration attention mechanism, and can meet the calculation requirements of the large model; moreover, the computing power of a UFS NAND logic chip is enhanced, a UFS protocol and an existing architecture are compatible, end-side equipment can be directly replaced, hardware modification is not needed, and the cost is reduced; and task scheduling can be optimized, local calculation and external migration are intelligently switched according to task types and parameter sparseness, and efficiency and performance are considered.

The invention discloses a counter based on a T trigger, a ramp generator, a converter and a sensor, and relates to the field of integrated circuits. The counter comprises a plurality of cascaded T triggers; the signal input end in each T trigger is connected with a first control signal and is used for adjusting the working state of the counter; the clock pulse input end and the inverted output end of each odd-level trigger are connected to the clock pulse input end of the next even-level trigger through an OR logic gate; the positive output end of each even-level trigger, the positive output end of the previous odd-level trigger and the clock pulse input end of the previous odd-level trigger are connected to the clock pulse input end of the next odd-level trigger through NAND logic gates; and a phase inverter is arranged between the clock pulse input end of the last odd-level trigger and the NAND logic gate. Therefore, by adjusting the trigger type and optimizing the generation logic process of the clock input signal, the delay time of the output signal in the counter is reduced.

The present invention provides a fast restart system for a hardware emulation accelerator and a control method thereof. The system includes a control module, a threshold monitoring module, a NAND logic circuit, a first MOS transistor, a discharge circuit, and a target discharge voltage module. The control module outputs an enable signal to the target discharge voltage module. The control module and the threshold monitoring module respectively output a startup signal and a voltage monitoring signal to two signal input terminals of the NAND logic circuit. The signal output terminal of the NAND logic circuit is connected to the gate of the first MOS transistor. The target discharge voltage module is connected to the source of the first MOS transistor. The discharge circuit is connected between the drain of the first MOS transistor and ground. The technical solution of the present invention can achieve a fast restart of the hardware emulation accelerator.

The invention discloses a customizable NAND logic gate biosensing system based on an engineered methylated CRISPR / Cas12a consensus sequence and an application of the customizable NAND logic gate biosensing system. According to the system, an engineered methylated CRISPR / Cas12a consensus sequence (MCCS, 5 '-TTTGATC-3') is combined with a hybridization chain reaction triggered by a primer, so that efficient conversion between a methylation state and Cas12a activation is realized. Dam methyltransferase, S-adenosylmethionine (SAM) and DpnI are used as three input signals, and when the three input signals all exist, methylation catalyzed by the Dam methyltransferase promotes DpnI cutting, destroys the continuity of a PAM-original spacer region and enables Cas12a to be inactivated (in a closed state), and a low-fluorescence signal is generated; under any other input combination, the Cas12a-crRNA keeps the activity and outputs a high-fluorescence'turn-on 'signal, so that the ultra-sensitive detection on the activity of the Dam methyltransferase is realized. The system shows high recovery rate and low variability in simulating a real biological sample, and provides a universal molecular calculation driven sensing platform for enzyme activity analysis and inhibitor screening in a complex biological environment.

A flip-flop includes a first input circuit, a first NOR logic gate, a first stacked gate circuit and a first NAND logic gate. The first input circuit is coupled to a first node, and configured to generate a first signal responsive to at least a first data signal, a first clock signal, or a second clock signal. The first NOR logic gate is coupled between the first node and a second node, and configured to generate a second signal responsive to the first signal or a first reset signal. The first stacked gate circuit is coupled between the first node and a third node, and configured to generate a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and fourth node, and is configured to generate a fourth signal responsive to the third signal or a second reset signal.

The application relates to a repeatable trigger type monostable circuit based on multi-channel signal control, comprising a data selector, a plurality of tri-state gate buffers, the enable ends of the tri-state gate buffers being connected with the output ends of the data selector respectively, the input ends of the tri-state gate buffers being used for connecting external sensors, a NAND logic gate, one input end of the NAND logic gate being connected with the output ends of the tri-state gate buffers through an input coupling bias unit, an NOR logic gate, one input end of the NOR logic gate being connected with the output end of the NAND logic gate through a delay unit, the other input end of the NOR logic gate being grounded, and the output end of the NOR logic gate being connected with the other input end of the NAND logic gate, and the enable state of each tri-state gate buffer is controlled, and the input trigger signal of the tri-state gate buffer being enabled is continuously responded within the delay time defined by the delay unit. Compared with the prior art, the application has the advantages of simplicity, selectivity based on different trigger sources, and the like.