32results about How to "Realize the logic function" patented technology

The invention relates to a rail traffic vehicle-mounted BTM automatic test system and method. The system comprises a simulation driving platform used for simulating electrical buttons on a real bridgeto realize the interaction with a vehicle simulator; the vehicle simulator used for simulating the running speed and location of a vehicle; a computer interlocking used for simulating a trackside device and sending the state of the trackside device to a trackside electronic unit; the trackside electronic unit used for calculating an ID of a transponder message and controlling the opportunity of sending the corresponding ID of the transponder message to a reference signal generator; the reference signal generator used for sending corresponding transponder message information stored in advanceto a reference loop; a BTM used for querying and obtaining the transponder message information stored in the reference loop; and an automatic train protection system used for sending a message query request to the BTM. By adoption of the rail traffic vehicle-mounted BTM automatic test system and method, the message collection action of a vehicle-mounted BTM through a series of transponders on theline can be simulated, which is convenient for the reliability test of the vehicle-mounted BTM.

The invention belongs to the technical field of flow measurement, and relates to a CPLD-based vortex shedding flowmeter. The vortex shedding flowmeter comprises a supply voltage conversion circuit, a piezoelectric sensor used for generated vortex shedding signals, a front end signal processing circuit, a standard pulse shaping circuit, the CPLD and a peripheral circuit thereof as well as a crystal oscillator circuit for providing a clock for the CPLD and a precision voltage flow conversion circuit, wherein, the piezoelectric sensor, the front end signal processing circuit and the standard pulse shaping circuit are sequentially connected, and PWM signals output from the standard pulse shaping circuit are sent to the CPLD; the CPLD stores a lookup table which reflects the corresponding relation between the vortex shedding frequencies before and after correction, and the CPLD counts the vortex shedding signals according to the input PWM signals, and corrects a count value by the lookup table to output a frequency signal reflecting the flow rate. The invention also provides a correction method of the flowmeter. The vortex shedding flowmeter and the correction method have the advantages of low power consumption, reliable performance and good real-time property.

The invention discloses a method for realizing linkage of query conditions in a self-defined report. For the query conditions in the self-defined report, interface components meeting input conditions are arranged and defined by a user, and linkage logic among the components is defined by the user at the same time, so that two kinds of variable logic exist, namely, component arrangement and definition logic and component linkage logic. According to the method, script design and analysis are performed, and the two kinds of the variable logic are expressed through flexible combination of script functions; logical functions of two kinds of dynamic logic are realized through analysis of a script by a script analysis engine; and business logic functions needed in the report query conditions are realized through script writing by the user in the self-defined report.

The invention discloses an expansion magnetic tunnel junction, a spinning majority gate device and a logic circuit. The spinning majority gate device comprises three input magnetic tunnel junctions (MTJs) and an output MTJ, wherein free layers of the three input MTJs are connected with a free layer of the output MTJ, magnetization directions of the free layers of the three input MTJs are determined by a direction and a size of an injection current, a magnetization direction of the free layer of the output MTJ is affected jointly by the magnetization directions of the free layers of the other three MTJs, and the resistance states of the output MTJs are determined jointly by the magnetization directions of the free layers of the output MTJs and magnetization of fixed layers. The magnetization directions of the fixed layers are changed by injecting a current, parallel to a membrane surface, into a heavy metal layer, so that the resistance states of the output MTJs are changed; and a freelayer of the previous spinning majority gate device and a free layer of a next spinning majority gate device are in bridge connection, a transfer current is injected into the output MTJs of the previous spinning majority gate device, and thus, information interconnection of the two spinning majority gate devices is achieved.

The invention discloses an intelligent power distribution monitoring system which is applicable to a power distribution looped network, wherein the power distribution looped network comprises a power supply station and a plurality of power distribution substations; the power distribution substations are connected with the power supply station; each power distribution substation is provided with a fault diagnosis and control unit; the power supply station is used for sending starting signal protection instructions to the fault diagnosis and control units in real time; the fault diagnosis and control units are used for receiving the starting signal protection instructions, synchronously collecting status information of the power distribution substations to which the fault diagnosis and control units belong, and the other power distribution substations to which the fault diagnosis and control units do not belong after the starting signal protection instructions are received, and processing the status information; if the status information is fault-free, the power distribution substations are instructed to reclose; if the status information is faulted, faults are detected, and removed to form a processing result; and then the processing result is fed back to the power supply station. The invention further discloses an intelligent power distribution monitoring method.

The invention discloses a system and method for implementing speed control of a diesel engine on the basis of multiple CAN communication protocols. A device comprises a bus interface unit, a CAN protocol analysis unit and a CAN communication unit, wherein the CAN protocol analysis unit comprises a plurality of protocol modules corresponding to a plurality of CAN communication protocols; the CAN communication unit is used for executing communication based on the CAN communication protocols; one end of the CAN protocol analysis unit is connected with an engine master control system through the bus interface unit; the other end of the CAN protocol analysis unit is connected with an electronic injection control system of the diesel engine through the CAN communication unit; and the CAN protocol analysis unit calls the protocol modules to analyze communication data between the engine master control system and the electronic injection control system of the diesel engine so as to execute CAN communication in required types. The method is used for implementing speed control of the diesel engine by controlling the system for implementing speed control of the diesel engine. The system and method for implementing speed control of the diesel engine on the basis of the multiple CAN communication protocols have the advantages of simple structure, low required cost, capability of implementing speed control of the diesel engine on the basis of the multiple CAN communication protocols and high control efficiency.

The invention discloses a rectifying control system with redundant current feedback, and the rectifying control system is applied to large rectification systems. The rectifying control system comprises an alternating-current transformer, a direct-current sensor, a main controller, a rectifier unit driving controller and an alarm device, the rectifier unit driving controller comprises a rectifier unit angle side drive controller and a rectifier unit star side drive controller, and the main controller comprises a logic control module, an adjuster and an output control module. The rectifying control system is applied to large same parallelly-connected rectification systems, output current fluctuation caused by feedback signal anomalies is effectively avoided without increasing the number of the sensor, a rectifying device and a load are protected under abnormal working conditions, system safety is improved, basic control tasks can be finished by the aid of fewer sensors, operating cost is reduced, and stable running reliability of the device is improved.

The invention relates to the technical field of integrated circuits, in particular to a reconfigurable threshold logic unit based on an SET (Single Electron Transistor)/MOS (Metal Oxide Semiconductor) composite structure and composed of nano devices. The reconfigurable threshold logic unit comprises a four-input SET/MOS composite circuit, a first phase inverter and a second phase inverter, wherein the output ends of the first phase inverter and the second phase inverter are respectively connected with an input end of the SET/MOS composite circuit; the input end is offset, but the device parameters of the circuit are not changed, thus, the logic unit can realize OR, NOR, AND and NAND logic functions. The reconfigurable threshold logic unit is simple in structure, low in power consumption, high in integration level, higher in reconfigurability and capable of effectively realizing different logic functions of the same unit. Due to the existence of the characteristics, the reconfigurable threshold logic unit can be applied to super-large-scale integrated circuits such as an FPGA (Field Programmable Gate Array), an artificial neural network and the like with low power consumption and high integration level.

The invention discloses a pflash type programmable logic device based on cluster circuits, and relates to the field of programmable logic devices, the programmable logic device comprises a kernel power management circuit, a word line circuit, a bit line circuit, a substrate potential circuit and a plurality of cluster circuits; each cluster circuit comprises a programmable wiring switch matrix, a logic unit circuit and a pull-down network circuit; the pull-down network circuit is connected with the signal input end of each switch unit; the kernel power supply management circuit obtains programming signals and is connected with the logic unit circuits in all the cluster circuits to provide kernel power supply; according to the programmable logic device, the circuits are matched to work to carry out operations such as erasing and programming, the connection relation between signals and the logic unit circuit is changed, so that the logic function needed by a user is achieved, the cluster circuit is achieved through the non-volatile pflash, then the whole programmable logic device is formed, and the programmable logic device has the advantages that power failure information is not lost, power-on quick start and single particle immunity are achieved. The application in a space environment and a ground radiation environment is met.

The invention provides a logic operation circuit, a differential amplification circuit and an electronic equipment. The logic operation circuit comprises at least one differential logic operation circuit, the differential logic operation circuit comprising: a logic network module comprising a first logic network unit and a second logic network unit with complementary logical functions, the input signals of the first logic network unit and the second logic network unit form differential signals, and the first logic network unit and the second logic network unit are used for realizing a preset logic function according to the input signals and outputting an operation result; the differential amplification module comprises a first input end, a second input end, a first output end and a second output end, the first input end and the second input end are respectively connected with the output ends of the first logic network unit and the second logic network unit, and the first output end and the second output end form a differential output end; and the amplifier is used for amplifying the operation result and outputting a logic operation result. Side channel attacks can be prevented, the data safety is improved, and the circuit power consumption is reduced.

Provided is a two-dimensional photonic crystal logic equivalence gate based on an auto-collimation interference effect. The two-dimensional photonic crystal logic equivalence gate comprises a tetragonal lattice photonic crystal which has the auto-collimation interference effect; three line defects serving as three beam splitters S1, S2 and S3 are made inside the photonic crystal and arranged in the auto-collimation beam propagation direction; the distance between the beam splitter S1 and the beam splitter S2 is delta l1=12a, and the distance between the beam splitter S2 and the beam splitter S3 is delta l2=25a, wherein a is a lattice constant of the photonic crystal; the photonic crystal is internally provided with three incident ports and one output port, and the three incident ports are two input beam ports and one reference light port. The phase difference between two input beams is adjusted by adjusting the defect column radius and the light path difference between the two input beams, and the two input beams achieve the logical function through destructive interference or destructive interference. The logic equivalence gate is not limited by physical boundaries in traditional waveguide and has better adaptability.

The invention discloses a CD40192 control circuit for teaching. The control circuit comprises an addition and subtraction preset number circuit, a zero clear circuit, a decoding display circuit, a power supply circuit and a start/stop circuit, wherein the power supply circuit is used for providing power for the addition and subtraction preset number circuit, the decoding display circuit and the start/stop circuit; the addition and subtraction preset number circuit is used for controlling the decoding display circuit to output numbers in a one-by-one addition or one-by-one subtraction manner; when the number is added to 9 or subtracted to 0, a number before start is preset automatically by the decoding display circuit; the start/stop circuit is used for controlling output pause or continuity of the decoding display circuit; the zeroing circuit is used for controlling the addition and subtraction preset number circuit to carry out zero clear on output of the decoding display circuit. Byadopting the control circuit, automatic addition and subtraction display of unit digits can be simply and conveniently achieved, the practicability is good, teaching contents can be enriched, and theteaching quality can be improved.

The embodiment of the invention discloses a lazy loading implementation method and device, electronic equipment and a storage medium. The lazy loading implementation method comprises the steps that a lazy loading class defined as an abstract class is determined to achieve a lazy loading logic function, a target abstract method is defined in the lazy loading class to achieve target logic, and at least two target service classes inherit the lazy loading logic function by inheriting the lazy loading class; in a page implementation process, a target function provided by a rewriting system is used for realizing a logic function of the target function when the target function is called back; and transmitting a duplicated target function into the target abstraction method to realize the realization of the same target logic in the at least two target business classes. According to the embodiment of the invention, lazy loading is realized through definition of the abstract class and the abstract method and is prevented from being limited by a system version, and the application scene of lazy loading realization is improved.

The invention discloses a magnetic skyrmion-based JK trigger with an annular magnetic track structure. The magnetic skyrmion is placed in the annular magnetic racing track; a voltage driving mode is adopted to enable the skyrmion to circularly move in the magnetic racing track, and the state of the skyrmion in the magnetic racing track is read through the magnetic tunnel junction, so that the logic function of the JK trigger is realized, and the stability of the JK trigger based on the skyrmion in use is ensured.

The invention provides a three-input three-output DNA algorithm self-assembly hexagon structure model. A three-input three-output hexagon structure subelement is composed of a DNA single chain, different coding sequences are used in six edges of the hexagon single chain, and a three-input three-output algorithm can be executed in three directions. Exclusive OR logic is executed through base complementary pairing based on the DNA hexagon model to form an exclusive-OR gate compound Sierpinski triangle for proving the reliability of self-assembly logic of the model. The model can effectively solve the problem that a tradition algorithm is high in self-assembly mispairing rate, and the self-assembly reliability is improved. Due to the fact that a hexagon structure has three input-output directions, the single hexagon structure model can achieve three-input three-output logic functions at most, and a plurality of cascaded hexagon structures can achieve more complex multi-input multi-output operation, which is a breakthrough in the field of DNA calculation.