402 results about "Line defects" patented technology

The invention discloses a power line defect diagnosis method based on a visible light image. The power line defect diagnosis method includes: a defect data gallery of a power line defect is established; an image from the defect data gallery is segmented, image features are extracted from the segmented image, a defect feature gallery is established based on the extracted image features, and the defect feature gallery serves as a reference benchmark of establishing recognition and classification of the power line defect; the visible light image is applied to capture an actual power line so as to obtain a captured image of the actual power line, and the image features of the captured image is extracted; the obtained image features of the actual power line image and the image features in the established defect feature gallery carry out matching; if a matched dot pair is greater than or equal to a preset threshold, the obtained image features of the actual power line image and the image features in the established defect feature gallery are matched, namely the actual power line has defects; and if the matched dot pair is smaller than the preset threshold, the obtained image features of the actual power line image and the image features in the established defect feature gallery are not matched, namely the actual power line is normal. The diagnosis method is efficient, and can automatically detect defects of the power line.

There is provided an optical control device including a plurality of line-defect waveguides provided in a photonic crystal; each line-defect waveguide including a multiplicity of dielectric pillars with a finite height arranged at lattice points of a two-dimensional Bravais lattice. The optical control device comprises: a first line-defect waveguide; a second line-defect waveguide provided with the dielectric pillars having a thickness different from that of the dielectric pillars of the first line-defect waveguide; and a third line-defect waveguide arranged between the first and second line-defect waveguides and provided with the dielectric pillars whose thicknesses are gradually varied from those of the dielectric pillars of the first line-defect waveguide to those of the dielectric pillars of the second line-defect waveguide along a wave guiding direction.

High-speed interconnect systems for connecting two or more electrical elements are provided. Interconnect system has the means, which could reduce the microwave loss induced due to the dielectrics. Reducing the effective loss tangent of the dielectrics reduces the microwave loss. With optimize design of the interconnects, the speed of the electrical signal can be made to closer to the speed of the light. The interconnect systems consists of the electrical signal line, inhomogeneous dielectric systems and the ground line, wherein inhomogeneous dielectric system consisting of the opened-trenches into the dielectric substrate or comb-shaped dielectrics to reduce the microwave loss. Alternatively dielectric structure can have the structure based on the fully electronic or electromagnetic crystal or quasi crystal with the line defect. Alternatively, dielectric structure can be made to comb-shaped structure with teethes having thickness and space making the air pocket to reduce the microwave loss. The interconnect system, can be made in rigid or flex board for off-chip interconnects for IC packages, connectors and cables, where conventional manufacturing technology can be used and yet to increase the bandwidth of the interconnects.

A TFT array substrate for use in an LCD device includes at least one repair line to repair line defects. The repair line(s) is formed when forming the pixel electrode so that additional process steps are not required. Accordingly, productivity can be increased. Moreover, either a short-circuit or an open-circuit can be repaired due to the repair line(s). Thus, in the present invention, a TFT array substrate, including: a substrate; a gate line formed on the substrate, arranged in a transverse direction and having a gate electrode; a data line insulated against the gate line by a first insulation layer, arranged in a longitudinal direction perpendicular to the gate line, having a source electrode near the cross point of the gate and data lines, and having first and second data lines which are defined by a cross point of the gate and data lines; a drain electrode space apart from the source electrode over the gate electrode; a pixel electrode connecting to the drain electrode; and a repair line(s) insulated against the data and gate lines by insulation layers and overlapping the gate and data lines, one repair line overlapping a free end of the other repair line and the gate line.