9 results about "XNOR gate" patented technology

The invention relates to the technical field of memristors, and provides a chitosan-based memristor which comprises a substrate, a buffer layer, a composite dielectric layer and a top electrode which are sequentially stacked from bottom to top, the buffer layer is formed by spin-coating a PEDOT: PSS aqueous solution on the substrate and then carrying out heat treatment; the composite dielectric layer is formed by spin-coating the buffer layer with an ultrasonic composite solution formed by a graphene oxide aqueous dispersion and a chitosan acetic acid solution and then carrying out heat treatment. By adopting a collaborative architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT: PSS buffer layer, the prepared bio-based memristor has the effects of relatively high switching ratio, relatively low operating voltage and good performance stability. Meanwhile, based on stable high and low resistance states of the device, all seven basic logic operations including a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate and an XNOR gate are completely realized on a single bio-based platform, the function accuracy can reach 100%, and an unexpected effect is achieved.

A compare circuitry that can be implemented in a memory circuit includes: selection logic coupled to a sense amplifier of the memory circuit, the selection logic structured to receive a sense amplifier enable signal, a column output from the sense amplifier, and a column output bar from the sense amplifier, wherein the selection logic is structured to pass through the column output and the column output bar when the sense amplifier enable signal is active and hold the column output and the column output bar at a same value when the sense amplifier enable signal is inactive; and an XNOR gate structured to receive the column output and the column output bar passed through the selection logic, a data input, and a data input bar and output a bit compare output.

A system for scanning and marking the same data before data transmission, comprising: D flip-flop, XOR gate, AND gate, CPU, storage, data bus; D flip-flop is connected in series to form a first group of shift registers and a second group of shift registers; XOR gate, AND gate, the first group of shift registers, the second group of shift registers form a scanning device; CPU, storage, scanning device are connected through data bus; The relatively static data stream and the flowing data stream are sent to the first group of shift registers and the second group of shift registers respectively; Scan the same data, and mark the same data stored in the storage as the basis of compressed data.

The application relates to the technical field of memristor, and provides a chitosan-based memristor, which comprises, from bottom to top, a substrate, a buffer layer, a composite dielectric layer and a top electrode; the buffer layer is formed by heat treatment after PEDOT:PSS aqueous solution is spin-coated on the substrate; and the composite dielectric layer is formed by heat treatment after an ultrasonic composite solution formed by graphene oxide aqueous dispersion and chitosan acetic acid solution is spin-coated on the buffer layer. Through the synergistic architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT:PSS buffer layer, the prepared bio-based memristor has the effects of high switching, low operating voltage and good performance stability. Meanwhile, based on the stable high and low resistance states of the device, all seven basic logic operations including the non-gate, the and gate, the or gate, the not-and gate, the not-or gate, the exclusive or gate and the same or gate are completely realized on a single bio-based platform, the function correctness rate can reach 100%, and unexpected effects are achieved.

The application discloses an FM0 decoding circuit and method for ETC, which comprises an edge detection unit, a narrowband filter unit, a rounding unit, a half frequency division unit, a non-gate processing unit, a shift delay unit, an exclusive or gate processing unit and a with gate processing unit. The application takes full advantage of the feature that FM0 coding is self-brought bit synchronization information, adopts a bit synchronization extraction mode, directly recovers a bit synchronization clock from an original coding sequence, avoids the synchronization problem of a transmission source clock and a local clock, has a simple and stable circuit structure, is low in cost, can adapt to various processors, and reduces the difficulty of processor selection and system design.

This invention relates to a restriction authorization module for setting limits on computing chips. This authorization module is configured as a main module for restricting computational operations on the computing chip. The authorization module authorizes the operation of the actual design in the computing device (such as a CPU, GPU, AI-based neural network model, or any basic logic gate such as AND, OR, NOT, XOR, XNOR, NAND, NOR, NOR, etc.) via an enable signal. Encryption enable logic can be set for non-on-chip systems. Replaceable and / or reconfigurable measurement units are configured to measure one or more parameters, wherein the measurement unit is adapted to be reconfigured for on-chip systems if the restriction authorization is used for repeated operations. Different types of security mode settings are implemented, which trigger a reset in the case of reconfigurable measurement units. The restriction authorization design logic is operable when the measurement unit does not reach the measurement limit. The measurement unit provides enable logic triggering, which further enables the actual design to operate; however, if the measurement unit reaches the measurement limit, the measurement unit triggers enable logic, rendering the actual design inoperable.

The utility model relates to a multipath FV converter comprising a circuit assembly. The circuit assembly comprises resistors R1-R5, a capacitor C1, an operational amplifier U4, triodes Q1 and Q2, an XNOR gate circuit U1B, XNOR gate circuits U2A and U2B, a D trigger U3A and an operational amplifier U4; the XNOR gate circuits U2A and U2B are connected to output signals of an external rotor position sensor, the input end of the XNOR gate circuit U1B is connected to the output end of the XNOR gate circuit U2B, and the other input end of the XNOR gate circuit U1B is connected to the data input end 5 of the D trigger U3A and is connected with the complementary output end 2 of the D trigger U3A; the output end of the XNOR gate circuit U1B is connected with the clock input end 3 of the D trigger U3A and connected with the base electrode of the triode Q1 through the resistor R1. The device is reasonable in design, compact in structure and convenient to use.

The application belongs to the technical field of integrated circuits, and particularly relates to a storage operation circuit, an SRAM in-memory computing circuit with TCAM and logic operation functions and a chip. Each basic storage operation circuit comprises two storage units T1 and T2 for storing data and two operation logic units ALU1 and ALU2. The operation logic units ALU1 and ALU2 each comprise a control end, a first input end, a second input end and an output end. The operation logic unit ALU1 is an AND gate when the control end is connected to VSS and is an XNOR gate when the control end is connected to VDD. The operation logic unit ALU2 is an XOR gate when the control end is connected to VSS and is an OR gate when the control end is connected to VDD. The input end of the operation logic unit ALU1 is connected to an external input IN and the storage unit T1. The input end of the operation logic unit ALU2 is connected to the output of the operation logic unit ALU1 and the storage unit T2. The application solves the problem that a conventional SRAM storage operation circuit is difficult to implement a composite Boolean logic operation in a single cycle, and improves the operation performance and stability of the storage operation circuit.

The invention discloses a silicon-based reconfigurable optical logic gate structure based on a uniformly distributed phase change material, which is characterized in that a 6 [mu] m * 6 [mu] m waveguide region is designed on a silicon-based substrate, and the silicon-based reconfigurable optical logic gate structure comprises two bent input waveguides, a bias input waveguide and two output ports. The middle design area is etched into a 7 * 7 nanopore array, the pores are filled with phase change materials, and the materials can be switched between a crystalline state and an amorphous state so as to change the refractive index. The phase state of the phase change material is changed through an external electric heating control, so that the device is equivalent to different logic gate structures in different refractive index states, and the functions of an AND gate, an OR gate, an XOR gate and an XNOR gate can be reconfigured on the same chip. According to the invention, a binary particle swarm optimization algorithm is also adopted to optimize hole array arrangement so as to maximize the logic function output contrast. The device is excellent in output contrast ratio under the wavelength of 1550 nm, and expected logic function switching can be achieved. The reconfigurable optical logic gate is compact in structure, non-volatile and flexible in function, and a potential scheme is provided for integrated optical calculation.