3 results about "XNOR gate" patented technology

The application relates to the technical field of memristor, and provides a chitosan-based memristor, which comprises, from bottom to top, a substrate, a buffer layer, a composite dielectric layer and a top electrode; the buffer layer is formed by heat treatment after PEDOT:PSS aqueous solution is spin-coated on the substrate; and the composite dielectric layer is formed by heat treatment after an ultrasonic composite solution formed by graphene oxide aqueous dispersion and chitosan acetic acid solution is spin-coated on the buffer layer. Through the synergistic architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT:PSS buffer layer, the prepared bio-based memristor has the effects of high switching, low operating voltage and good performance stability. Meanwhile, based on the stable high and low resistance states of the device, all seven basic logic operations including the non-gate, the and gate, the or gate, the not-and gate, the not-or gate, the exclusive or gate and the same or gate are completely realized on a single bio-based platform, the function correctness rate can reach 100%, and unexpected effects are achieved.

The application discloses an FM0 decoding circuit and method for ETC, which comprises an edge detection unit, a narrowband filter unit, a rounding unit, a half frequency division unit, a non-gate processing unit, a shift delay unit, an exclusive or gate processing unit and a with gate processing unit. The application takes full advantage of the feature that FM0 coding is self-brought bit synchronization information, adopts a bit synchronization extraction mode, directly recovers a bit synchronization clock from an original coding sequence, avoids the synchronization problem of a transmission source clock and a local clock, has a simple and stable circuit structure, is low in cost, can adapt to various processors, and reduces the difficulty of processor selection and system design.

This invention relates to a restriction authorization module for setting limits on computing chips. This authorization module is configured as a main module for restricting computational operations on the computing chip. The authorization module authorizes the operation of the actual design in the computing device (such as a CPU, GPU, AI-based neural network model, or any basic logic gate such as AND, OR, NOT, XOR, XNOR, NAND, NOR, NOR, etc.) via an enable signal. Encryption enable logic can be set for non-on-chip systems. Replaceable and / or reconfigurable measurement units are configured to measure one or more parameters, wherein the measurement unit is adapted to be reconfigured for on-chip systems if the restriction authorization is used for repeated operations. Different types of security mode settings are implemented, which trigger a reset in the case of reconfigurable measurement units. The restriction authorization design logic is operable when the measurement unit does not reach the measurement limit. The measurement unit provides enable logic triggering, which further enables the actual design to operate; however, if the measurement unit reaches the measurement limit, the measurement unit triggers enable logic, rendering the actual design inoperable.