22 results about "XNOR gate" patented technology

The invention relates to the technical field of memristors, and provides a chitosan-based memristor which comprises a substrate, a buffer layer, a composite dielectric layer and a top electrode which are sequentially stacked from bottom to top, the buffer layer is formed by spin-coating a PEDOT: PSS aqueous solution on the substrate and then carrying out heat treatment; the composite dielectric layer is formed by spin-coating the buffer layer with an ultrasonic composite solution formed by a graphene oxide aqueous dispersion and a chitosan acetic acid solution and then carrying out heat treatment. By adopting a collaborative architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT: PSS buffer layer, the prepared bio-based memristor has the effects of relatively high switching ratio, relatively low operating voltage and good performance stability. Meanwhile, based on stable high and low resistance states of the device, all seven basic logic operations including a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate and an XNOR gate are completely realized on a single bio-based platform, the function accuracy can reach 100%, and an unexpected effect is achieved.

A compare circuitry that can be implemented in a memory circuit includes: selection logic coupled to a sense amplifier of the memory circuit, the selection logic structured to receive a sense amplifier enable signal, a column output from the sense amplifier, and a column output bar from the sense amplifier, wherein the selection logic is structured to pass through the column output and the column output bar when the sense amplifier enable signal is active and hold the column output and the column output bar at a same value when the sense amplifier enable signal is inactive; and an XNOR gate structured to receive the column output and the column output bar passed through the selection logic, a data input, and a data input bar and output a bit compare output.

This invention provides a three-state XOR / XNOR gate based on probabilistic devices and its modulation method, relating to the field of semiconductor device technology. The three-state XOR / XNOR gate comprises multiple probabilistic devices connected in series. The resistive state of each probabilistic device exhibits either a high-resistance state or a low-resistance state depending on the input pulse current density. By inputting multiple pulse currents of different current densities, the total voltage across the series connection of the multiple probabilistic devices reaches different voltage ranges, corresponding to logic values ​​1, 1 / 2, and 0, respectively, thus realizing a three-state XOR and XNOR gate. The application of this three-state XOR / XNOR gate is expected to overcome the performance bottleneck of traditional binary circuits and become a key component in AI acceleration, fault-tolerant computing, and novel computing architectures.

The invention discloses a PTL-based processor calculation unit design method, which comprises the following steps: multiplexing a processor dual-port register, and obtaining the input of a PTL basic gate circuit from the output of the dual-port register, so as to form a PTL gate circuit as the design basis of a processor calculation unit. The PTL basic gate circuit comprises a NOT gate, an AND gate, an OR gate, an NAND gate, a NOR gate, an XOR gate, an XNOR gate or a transmission gate. And the processor calculation unit comprises an adder, a multiplier or a logical operation unit. And the dual-port register outputs complementary signal pair input of the PTL basic gate circuit.

A system for scanning and marking the same data before data transmission, comprising: D flip-flop, XOR gate, AND gate, CPU, storage, data bus; D flip-flop is connected in series to form a first group of shift registers and a second group of shift registers; XOR gate, AND gate, the first group of shift registers, the second group of shift registers form a scanning device; CPU, storage, scanning device are connected through data bus; The relatively static data stream and the flowing data stream are sent to the first group of shift registers and the second group of shift registers respectively; Scan the same data, and mark the same data stored in the storage as the basis of compressed data.

The invention discloses a radiation hardening foreground calibration circuit and equipment, the foreground calibration circuit comprises a comparator, a first trigger, a counter, an accumulator, a digital-to-analog converter and a radiation hardening unit, the radiation hardening unit comprises a delay module, a second trigger, an XNOR gate and an AND gate, and the delay module and the second trigger delay and synchronize the result signal output by the comparator to obtain a second path of result signal, perform XNOR operation with the original result signal obtained by the first trigger, and then perform AND operation with the clock signal to serve as a response signal of the counter and the accumulator. The invention aims to solve the problem that a space task fails due to the fact that a traditional foreground calibration circuit is easily influenced by a single particle when running in a radiation environment and a single particle function is interrupted, improve the radiation hardening capability of the foreground calibration circuit running in the radiation environment, and realize the radiation hardening optimization design of the foreground calibration circuit.

The present invention relates to provide limited granting module for computing chips A Granting module is provided as a main module for limiting the computational operations of the computing chips. The Granting module through enable signal grants the operations of an actual design in a computing device, such as CPU, GPU, Artificial Intelligence based Neural Network models, any primitive logic gates such as AND, OR, NOT, XOR, XNOR, NAND, NOR and the like. An encrypted enable logic may be provided for non-System on Chip. A replaceable and / or reconfigurable measuring unit is provided to measure one or more parameters, wherein the measuring unit is adapted to reconfigure for a System on Chip if the Limited grantor is meant for repetitive operations. Different kind of the secured mode settings are implemented which triggers to reset in case of re-configurable measuring unit. Limited grantor Design logic is operative when measuring unit is not reached to measuring limit. The measuring unit provides enable logic triggering that further provide the actual design to operate, whereas if the measuring unit reaches to a measuring limit, the measuring unit triggers enable logic which makes the actual design non operative.

The invention provides a three-state XOR XNOR gate based on a probabilistic device and a modulation method of the three-state XOR XNOR gate, and relates to the technical field of semiconductor devices. The three-state XOR-XNOR gate comprises a plurality of probability devices which are connected in series, and the resistance states of the probability devices are high resistance states or low resistance states according to different input pulse current densities; by inputting pulse current with different current densities for multiple times, the total series voltage of a plurality of probabilistic devices reaches different voltage ranges and corresponds to logic values 1, 1 / 2 and 0 respectively, so that a three-state exclusive-OR gate and a three-state XNOR gate are realized. The application of the three-state XOR XNOR gate is expected to break through the performance bottleneck of a traditional binary circuit, and the three-state XOR XNOR gate becomes a key component in AI acceleration, fault-tolerant calculation and novel calculation architecture.

The application relates to the technical field of memristor, and provides a chitosan-based memristor, which comprises, from bottom to top, a substrate, a buffer layer, a composite dielectric layer and a top electrode; the buffer layer is formed by heat treatment after PEDOT:PSS aqueous solution is spin-coated on the substrate; and the composite dielectric layer is formed by heat treatment after an ultrasonic composite solution formed by graphene oxide aqueous dispersion and chitosan acetic acid solution is spin-coated on the buffer layer. Through the synergistic architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT:PSS buffer layer, the prepared bio-based memristor has the effects of high switching, low operating voltage and good performance stability. Meanwhile, based on the stable high and low resistance states of the device, all seven basic logic operations including the non-gate, the and gate, the or gate, the not-and gate, the not-or gate, the exclusive or gate and the same or gate are completely realized on a single bio-based platform, the function correctness rate can reach 100%, and unexpected effects are achieved.

The application discloses an FM0 decoding circuit and method for ETC, which comprises an edge detection unit, a narrowband filter unit, a rounding unit, a half frequency division unit, a non-gate processing unit, a shift delay unit, an exclusive or gate processing unit and a with gate processing unit. The application takes full advantage of the feature that FM0 coding is self-brought bit synchronization information, adopts a bit synchronization extraction mode, directly recovers a bit synchronization clock from an original coding sequence, avoids the synchronization problem of a transmission source clock and a local clock, has a simple and stable circuit structure, is low in cost, can adapt to various processors, and reduces the difficulty of processor selection and system design.

The present invention relates to a in-memory computing circuit. The sign bit of the input data is input to the first input terminal of the XNOR gate in the circuit. The second terminal of the XNOR gate is connected to the Q of the last SRAM cell in the memory array, and the sign bit of the weight is input to the second terminal of the XNOR gate. The output terminal of the XNOR gate is connected to the gate of transistor PM1. The sources of transistor PM1 and transistor PM2 are connected to one end of capacitor C1. The drains of transistor PM1 and transistor PM2 are connected to the output terminal of transmission gate T1. The other end of capacitor C1 is connected to VDD. The gate of transistor PM2 is connected to the gate of transistor PM3. The sources of transistor PM3 and transistor PM4 are connected to one end of capacitor C2. The other end of capacitor C2 is connected to VDD. The drains of transistor PM3 and transistor PM4 are connected to the output terminal of transmission gate T1. The input terminal of transmission gate T1 is connected to the complementary bit line. The gate of transistor PM4 inputs the opposite of the output result of the XNOR gate. The present invention can improve the concurrency and computing speed of array computing.

The invention discloses an XNOR gate and an XOR gate circuit realized based on three-valued memristors. The XNOR gate and the XOR gate circuit comprise three memristors, three voltage sources, four voltage control type switches and an auxiliary resistor, wherein the three memristors are two input memristors and one output memristor respectively. The XNOR gate controls the conduction of the voltage control type switches S1 and S3 by using the parallel partial voltage Vab input into the memristor, controls the conduction of the voltage control type switches S2 and S4 by using the partial voltage Vbc of the auxiliary resistor R, and determines the threshold voltages VS1, VS2, VS3 and VS4 of the voltage control type switches S1, S2, S3 and S4 according to the partial voltages Vab and Vbc, thereby realizing XNOR logic operation. According to the invention, the limitation of the traditional binary circuit on the information bearing capability is overcome, the operational capability of the circuit is enhanced, and the circuit structure is simpler.

This invention relates to a restriction authorization module for setting limits on computing chips. This authorization module is configured as a main module for restricting computational operations on the computing chip. The authorization module authorizes the operation of the actual design in the computing device (such as a CPU, GPU, AI-based neural network model, or any basic logic gate such as AND, OR, NOT, XOR, XNOR, NAND, NOR, NOR, etc.) via an enable signal. Encryption enable logic can be set for non-on-chip systems. Replaceable and / or reconfigurable measurement units are configured to measure one or more parameters, wherein the measurement unit is adapted to be reconfigured for on-chip systems if the restriction authorization is used for repeated operations. Different types of security mode settings are implemented, which trigger a reset in the case of reconfigurable measurement units. The restriction authorization design logic is operable when the measurement unit does not reach the measurement limit. The measurement unit provides enable logic triggering, which further enables the actual design to operate; however, if the measurement unit reaches the measurement limit, the measurement unit triggers enable logic, rendering the actual design inoperable.

A compare circuitry that can be implemented in a memory circuit includes: selection logic coupled to a sense amplifier of the memory circuit, the selection logic structured to receive a sense amplifier enable signal, a column output from the sense amplifier, and a column output bar from the sense amplifier, wherein the selection logic is structured to pass through the column output and the column output bar when the sense amplifier enable signal is active and hold the column output and the column output bar at a same value when the sense amplifier enable signal is inactive; and an XNOR gate structured to receive the column output and the column output bar passed through the selection logic, a data input, and a data input bar and output a bit compare output.

The utility model relates to a multipath FV converter comprising a circuit assembly. The circuit assembly comprises resistors R1-R5, a capacitor C1, an operational amplifier U4, triodes Q1 and Q2, an XNOR gate circuit U1B, XNOR gate circuits U2A and U2B, a D trigger U3A and an operational amplifier U4; the XNOR gate circuits U2A and U2B are connected to output signals of an external rotor position sensor, the input end of the XNOR gate circuit U1B is connected to the output end of the XNOR gate circuit U2B, and the other input end of the XNOR gate circuit U1B is connected to the data input end 5 of the D trigger U3A and is connected with the complementary output end 2 of the D trigger U3A; the output end of the XNOR gate circuit U1B is connected with the clock input end 3 of the D trigger U3A and connected with the base electrode of the triode Q1 through the resistor R1. The device is reasonable in design, compact in structure and convenient to use.

The present invention discloses a radiation-hardened foreground calibration circuit and device. The foreground calibration circuit of the present invention includes a comparator, a first trigger, a counter and accumulator, a digital-to-analog converter, and a radiation-hardened unit. The radiation-hardened unit includes a delay module, a second trigger, an XNOR gate, and an AND gate. The delay module and the second trigger delay the result signal output by the comparator to obtain a second result signal, perform an XNOR operation on the result signal obtained by the first trigger, and then perform an AND operation on the result signal with the clock signal to serve as the response signal of the counter and accumulator. The present invention aims to solve the problem that traditional foreground calibration circuits are easily affected by single particles when operating in a radiation environment, resulting in single particle function interruption and leading to space mission failure, improve the radiation-hardened capability of the foreground calibration circuit when operating in a radiation environment, and realize the radiation-hardened optimized design of the foreground calibration circuit.

The application belongs to the technical field of integrated circuits, and particularly relates to a storage operation circuit, an SRAM in-memory computing circuit with TCAM and logic operation functions and a chip. Each basic storage operation circuit comprises two storage units T1 and T2 for storing data and two operation logic units ALU1 and ALU2. The operation logic units ALU1 and ALU2 each comprise a control end, a first input end, a second input end and an output end. The operation logic unit ALU1 is an AND gate when the control end is connected to VSS and is an XNOR gate when the control end is connected to VDD. The operation logic unit ALU2 is an XOR gate when the control end is connected to VSS and is an OR gate when the control end is connected to VDD. The input end of the operation logic unit ALU1 is connected to an external input IN and the storage unit T1. The input end of the operation logic unit ALU2 is connected to the output of the operation logic unit ALU1 and the storage unit T2. The application solves the problem that a conventional SRAM storage operation circuit is difficult to implement a composite Boolean logic operation in a single cycle, and improves the operation performance and stability of the storage operation circuit.

The invention discloses a digital signal overall scaling method, device and equipment based on thermometer coding, relates to the field of digital signal processing, and solves the problems that hardware is high in complexity and long in critical path in overall scaling calculation. Comprising the following steps: performing XNOR gate operation and AND gate logic operation on each element in an input vector to generate a zoom coefficient of a thermometer coding format; carrying out AND gate logic operation on the zoom coefficient, calculating a minimum value, and obtaining a minimum zoom coefficient under the coding representation of the thermometer; converting the minimum zoom coefficient into a binary format to obtain a binary zoom coefficient; performing numerical scaling and bit width reduction on each element in an input vector according to the binary scaling coefficient to obtain a scaled vector; the technical effects of low overall zooming complexity and short key path are achieved.

The invention provides a sequential self-adjustment-based successive approximation analog-to-digital converter. The sequential self-adjustment-based successive approximation analog-to-digital converter comprises a sampling and holding switch, a capacitive digital-to-analog converter, a dynamic comparator COM, an XNOR gate, a phase inverter and M delay units Mlt, the bit number N of the analog-to-digital converter, the frequency selector, the output holding circuit and the input end of the sampling holding switch are connected with an external signal VIN, and the output end of the sampling holding switch is connected with an upper board of the capacitive digital-to-analog converter and the positive input end VP of the dynamic comparator COM; the negative input end VN of the dynamic comparator COM is connected with a reference voltage Vref, and the output ends OUTN and OUTP of the dynamic comparator COM are respectively connected with the input end of the XNOR gate and the input end of the output holding circuit; according to the invention, the successive comparison switching time after the sampling of the successive approximation type analog-to-digital converter is finished can be effectively reduced, so that the sampling speed of the whole successive approximation type analog-to-digital converter is improved.

The invention relates to devices for generating true random numbers, comprising a digital chaotically oscillating autonomous Boolean network as a source of entropy. According to the invention, the proposed digital chaotically oscillating autonomous Boolean network consists in three logic elements connected to each other, two of which represent two-input “Exclusive OR” and / or “Exclusive NOR” gates, and the third logic element has three inputs and one output, and implements a logic “counting ones” function, in which its output is set to a logic one if a logic one is present at no more than one of its inputs, otherwise it is set to a logic zero. The achieved technical result consists in an increase in true random number generation rate while decreasing energy consumption.

The invention discloses a silicon-based reconfigurable optical logic gate structure based on a uniformly distributed phase change material, which is characterized in that a 6 [mu] m * 6 [mu] m waveguide region is designed on a silicon-based substrate, and the silicon-based reconfigurable optical logic gate structure comprises two bent input waveguides, a bias input waveguide and two output ports. The middle design area is etched into a 7 * 7 nanopore array, the pores are filled with phase change materials, and the materials can be switched between a crystalline state and an amorphous state so as to change the refractive index. The phase state of the phase change material is changed through an external electric heating control, so that the device is equivalent to different logic gate structures in different refractive index states, and the functions of an AND gate, an OR gate, an XOR gate and an XNOR gate can be reconfigured on the same chip. According to the invention, a binary particle swarm optimization algorithm is also adopted to optimize hole array arrangement so as to maximize the logic function output contrast. The device is excellent in output contrast ratio under the wavelength of 1550 nm, and expected logic function switching can be achieved. The reconfigurable optical logic gate is compact in structure, non-volatile and flexible in function, and a potential scheme is provided for integrated optical calculation.

The present invention discloses an asynchronous micro-pipeline structure based on a "send-relay-receive" structure, which includes an asynchronous control component. The asynchronous control component includes one or more of a Sender, a Relay, a Receiver, or a Permitted Relay (PmtRelay). The Sender includes a trigger, an inverter, and a delay module; the Relay is composed of an exclusive-OR gate, an exclusive-NOR gate, an AND gate, a D flip-flop, an inverter, and a delay module, and is implemented based on a Click asynchronous controller; the Receiver includes a trigger; the PmtRelay adds a pmt control mechanism to the Click controller; the asynchronous control component is one of a Fifo, a PmtFifo, a Selector, a Splitter, a WaitMerge, and a MutexMerge, and an asynchronous micro-pipeline structure is built by one or more of the asynchronous control components. The asynchronous micro-pipeline structure of the present invention provides fine-grained control, uses event flow to drive control, adopts a unified control chain template, is more straightforward and simple in design, pays more attention to the delay and generation conditions of event signals, and is more flexible and efficient in the design process.