Circuit capable of realizing multiplexing of exclusive-OR gate or XNOR gate

A circuit and gating circuit technology, applied in the direction of logic circuits with logic functions, etc., can solve the problem of reducing the scale of the circuit, and achieve the effect of reducing the number of transistors, reducing the power consumption of the circuit, and reducing the number of tubes

Active Publication Date: 2016-04-06
WUXI XINXIANG ELECTRONICS TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The invention whose application number is 200510075399.0 designs an AES encryption and decryption circuit optimization method and multiplexes Sbox modules, which reduces the circuit scale and reduces circuit power consumption and area by ma

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  • Circuit capable of realizing multiplexing of exclusive-OR gate or XNOR gate
  • Circuit capable of realizing multiplexing of exclusive-OR gate or XNOR gate

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Embodiment Construction

[0032] The technical solution of the invention will be described in detail below in conjunction with the accompanying drawings.

[0033] The present invention provides a figure 1 , figure 2 The shown logic gate circuit based on the two-stage circuit connection realizes the multiplexing of the XOR gate and the NOR gate. The first-stage circuit is a composite logic gate circuit of an XOR gate / XOR gate, including: a NOR gate composed of a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2 A unit, an NOR gate unit composed of the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5, and the sixth The first inverter INV1 composed of the PMOS transistor P6 and the sixth NMOS transistor N6; the second stage circuit is a two-to-one selection circuit, including: the first transmission gate comp...

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Abstract

The invention discloses a circuit capable of realizing multiplexing of an exclusive-OR gate or an XNOR gate, belonging to the technical field of integrated circuits. The circuit comprises a compound logic gate circuit and an either-or gating circuit which are cascaded; the compound logic gate circuit comprises a NOR gate unit, an AND-OR-NOT gate unit and a first phase inverter, an input end of the NOR gate unit and the input end of the AND-OR-NOT gate unit are respectively connected with two paths of input signals, an output end of the NOR gate unit is connected with a control end of the AND-OR-NOT gate unit, the output end of the AND-OR-NOT gate unit is connected with the input end of the first phase inverter and outputs an exclusive-OR operation result, and the output end of the first phase inverter outputs an XNOR operation result; and the either-or gating circuit performs gating on an exclusive-OR gate unit composed of the NOR gate unit and the AND-OR-NOT gate unit, or an XNOR gate unit composed of the NOR gate unit, the AND-OR-NOT gate unit and the first phase inverter. The circuit provided by the invention realizes simple multiplexing of the exclusive-OR gate or XNOR gate circuit, reduces the number of transistors of the whole circuit system, and consequently reduces the layout area and circuit power consumption.

Description

technical field [0001] The invention discloses a circuit capable of realizing the multiplexing of the exclusive OR gate or the same OR gate, and belongs to the technical field of integrated circuits. Background technique [0002] In the encryption and decryption operations in the field of integrated circuits, XOR gates and NOR gates are widely used logic gate circuits, which makes them occupy a considerable part of the area on the circuit layout. The invention whose application number is 200510075399.0 designs an AES encryption and decryption circuit optimization method and multiplexes Sbox modules, which reduces the circuit scale and reduces circuit power consumption and area by making the encryption and decryption circuits share one Sbox module; the existing encryption and decryption operation circuits Most of them use separate XOR gates or XOR gates, and there are few circuits that realize XOR gates or XOR gates. It is urgent to design a reusable logic gate circuit, so t...

Claims

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Application Information

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IPC IPC(8): H03K19/20
Inventor 周烨黄刚季海梅杨凡李芳芳
Owner WUXI XINXIANG ELECTRONICS TECH
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